coreboot-gerrit March 2022

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Change in coreboot[master]: mb/google/brya: Set pciexp_hotplug_dummy_ops.set_resources as no-op
by Felix Held (Code Review) 27 Mar '22

27 Mar '22

Attention is currently required from: John Su. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63101 ) Change subject: mb/google/brya: Set pciexp_hotplug_dummy_ops.set_resources as no-op ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/63101/comment/1e43cda0_ac946495 PS1, Line 7: mb/google/brya this isn't a change in mb/gogle/brya, but in device/pciexp_device, so the prefix should be device/pciexp_device instead -- To view, visit https://review.coreboot.org/c/coreboot/+/63101 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifee7479c69cf16025dbd4e3924056ed7f8e253cf Gerrit-Change-Number: 63101 Gerrit-PatchSet: 1 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Sun, 27 Mar 2022 15:35:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: tests/lib: Add space before single line comment termination
by Felix Held (Code Review) 27 Mar '22

27 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62935 ) Change subject: tests/lib: Add space before single line comment termination ...................................................................... tests/lib: Add space before single line comment termination Change-Id: I9321391cc06afddff94fbba79f93851b553c74b1 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62935 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jakub Czapiga <jacz(a)semihalf.com> --- M tests/lib/bootmem-test.c M tests/lib/imd-test.c 2 files changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Jakub Czapiga: Looks good to me, approved diff --git a/tests/lib/bootmem-test.c b/tests/lib/bootmem-test.c index 6059833..ddd62ae 100644 --- a/tests/lib/bootmem-test.c +++ b/tests/lib/bootmem-test.c @@ -311,7 +311,7 @@ ret = bootmem_region_targets_type(RAMSTAGE_START, RAMSTAGE_SIZE, BM_MEM_RESERVED); assert_int_equal(ret, 0); - /* Range covering one more byte than one region*/ + /* Range covering one more byte than one region */ ret = bootmem_region_targets_type(RAMSTAGE_START, RAMSTAGE_SIZE + 1, BM_MEM_RAMSTAGE); assert_int_equal(ret, 0); diff --git a/tests/lib/imd-test.c b/tests/lib/imd-test.c index 28a4456..de42e08 100644 --- a/tests/lib/imd-test.c +++ b/tests/lib/imd-test.c @@ -49,7 +49,7 @@ struct imd imd; uintptr_t test_inputs[] = { 0, /* Lowest possible address */ - 0xA000, /* Fits in 16 bits, should not get rounded down*/ + 0xA000, /* Fits in 16 bits, should not get rounded down */ 0xDEAA, /* Fits in 16 bits */ 0xB0B0B000, /* Fits in 32 bits, should not get rounded down */ 0xF0F0F0F0, /* Fits in 32 bits */ -- To view, visit https://review.coreboot.org/c/coreboot/+/62935 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9321391cc06afddff94fbba79f93851b553c74b1 Gerrit-Change-Number: 62935 Gerrit-PatchSet: 2 Gerrit-Owner: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/var/banshee: Add mic mute switch setting
by Felix Held (Code Review) 27 Mar '22

27 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62804 ) Change subject: mb/google/brya/var/banshee: Add mic mute switch setting ...................................................................... mb/google/brya/var/banshee: Add mic mute switch setting Using the GPP_F22 as mic mute switch based on the latest schematic. BUG=b:223737606, b:216110896 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot chromeos-bootimage The mic_mute event is changed when the mic_mute GPIO pin is switched. Event: time 1647939954.639995, type 5 (EV_SW), code 14 (SW_MUTE_DEVICE), value 0 Event: time 1647939954.639995, -------------- SYN_REPORT ------------ Event: time 1647939954.648152, type 5 (EV_SW), code 14 (SW_MUTE_DEVICE), value 1 Event: time 1647939954.648152, -------------- SYN_REPORT ------------ Signed-off-by: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Change-Id: I6f7176afbd64f7c080f02369f195043a2df88e5d Reviewed-on: https://review.coreboot.org/c/coreboot/+/62804 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/Kconfig.name M src/mainboard/google/brya/variants/banshee/gpio.c M src/mainboard/google/brya/variants/banshee/overridetree.cb 3 files changed, 14 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index f1cab9d..b3917d2 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -174,6 +174,7 @@ select BOARD_GOOGLE_BASEBOARD_BRYA select MEMORY_SODIMM select CHROMEOS_WIFI_SAR if CHROMEOS + select DRIVERS_GENERIC_GPIO_KEYS config BOARD_GOOGLE_CROTA bool "-> Crota" diff --git a/src/mainboard/google/brya/variants/banshee/gpio.c b/src/mainboard/google/brya/variants/banshee/gpio.c index a6f6854..b8f4dab 100644 --- a/src/mainboard/google/brya/variants/banshee/gpio.c +++ b/src/mainboard/google/brya/variants/banshee/gpio.c @@ -186,7 +186,8 @@ PAD_NC(GPP_F20, NONE), /* F21 : EXT_PWR_GATE2# ==> NC */ PAD_NC(GPP_F21, NONE), - /* F22 : NC */ + /* F22 : NC ==> MIC_SW */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_F22, NONE, DEEP), /* F23 : NC */ /* H0 : GPPH0_BOOT_STRAP1 */ diff --git a/src/mainboard/google/brya/variants/banshee/overridetree.cb b/src/mainboard/google/brya/variants/banshee/overridetree.cb index ea81874..866bbd6 100644 --- a/src/mainboard/google/brya/variants/banshee/overridetree.cb +++ b/src/mainboard/google/brya/variants/banshee/overridetree.cb @@ -196,6 +196,17 @@ register "property_list[0].integer" = "1" device i2c 1a on end end + chip drivers/generic/gpio_keys + register "name" = ""MUTE"" + register "label" = ""mic_mute_switch"" + register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_HIGH(GPP_F22)" + register "key.wakeup_route" = "WAKEUP_ROUTE_DISABLED" + register "key.dev_name" = ""MMSW"" + register "key.linux_code" = "SW_MUTE_DEVICE" + register "key.linux_input_type" = "EV_SW" + register "key.label" = ""mic_mute_switch_key"" + device generic 0 on end + end end #I2C0 device ref i2c1 on chip drivers/i2c/tpm -- To view, visit https://review.coreboot.org/c/coreboot/+/62804 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6f7176afbd64f7c080f02369f195043a2df88e5d Gerrit-Change-Number: 62804 Gerrit-PatchSet: 9 Gerrit-Owner: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Ricky Chang <rickytlchang(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/variants/baseboard/brask: set GPP_D0 to GPO
by Felix Held (Code Review) 27 Mar '22

27 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63090 ) Change subject: mb/google/brya/variants/baseboard/brask: set GPP_D0 to GPO ...................................................................... mb/google/brya/variants/baseboard/brask: set GPP_D0 to GPO Currently, we control the GPP_D0 in the flash_fp_mcu in order to program the component's firmware. If we set this pin to NC, then we can't control the GPP_D0 output low/high and that make the system fails to program the component's firmware. This patch sets the GPP_D0 to GPO to fix it. BUG=b:204679292 BRANCH=firmware-brya-14505.B TEST=program the component's firmware Change-Id: I2f58c324f807a067dbe338f044a33dc9622ca469 Signed-off-by: Zhuohao Lee <zhuohao(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63090 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/variants/baseboard/brask/gpio.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/baseboard/brask/gpio.c b/src/mainboard/google/brya/variants/baseboard/brask/gpio.c index ed0416b..c540d76 100644 --- a/src/mainboard/google/brya/variants/baseboard/brask/gpio.c +++ b/src/mainboard/google/brya/variants/baseboard/brask/gpio.c @@ -118,7 +118,7 @@ PAD_NC(GPP_C7, NONE), /* D0 : ISH_GP0 ==> PCH_FP_BOOT0 */ - PAD_NC_LOCK(GPP_D0, NONE, LOCK_CONFIG), + PAD_CFG_GPO_LOCK(GPP_D0, 0, LOCK_CONFIG), /* D1 : ISH_GP1 ==> FP_RST_ODL */ PAD_CFG_GPO_LOCK(GPP_D1, 1, LOCK_CONFIG), /* D2 : ISH_GP2 ==> EN_FP_PWR */ -- To view, visit https://review.coreboot.org/c/coreboot/+/63090 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2f58c324f807a067dbe338f044a33dc9622ca469 Gerrit-Change-Number: 63090 Gerrit-PatchSet: 2 Gerrit-Owner: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/mediatek: Include 'console/console.h' when appropriate
by Felix Held (Code Review) 27 Mar '22

27 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61043 ) Change subject: soc/mediatek: Include 'console/console.h' when appropriate ...................................................................... soc/mediatek: Include 'console/console.h' when appropriate Found using: diff <(git grep -l '#include <console/console.h>' -- src/) <(git grep -l 'console_time_report\|console_time_get_and_reset\|do_putchar\|vprintk\|printk\|console_log_level\|console_init\|get_log_level\|CONSOLE_ENABLE\|get_console_loglevel\|die_notify\|die_with_post_code\|die\|arch_post_code\|mainboard_post\|post_code\|RAM_SPEW\|RAM_DEBUG\|BIOS_EMERG\|BIOS_ALERT\|BIOS_CRIT\|BIOS_ERR\|BIOS_WARNING\|BIOS_NOTICE\|BIOS_INFO\|BIOS_DEBUG\|BIOS_SPEW\|BIOS_NEVER' -- src/) Change-Id: I93f930de5a2a477ec4c0d8e5c8c57b25f5e4252c Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61043 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Hung-Te Lin <hungte(a)chromium.org> Reviewed-by: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> --- M src/soc/mediatek/common/include/soc/msdc.h M src/soc/mediatek/common/msdc.c M src/soc/mediatek/mt8173/include/soc/dramc_pi_api.h M src/soc/mediatek/mt8183/i2c.c M src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h M src/soc/mediatek/mt8192/i2c.c 6 files changed, 4 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Hung-Te Lin: Looks good to me, approved Xixi Chen: Looks good to me, but someone else must approve diff --git a/src/soc/mediatek/common/include/soc/msdc.h b/src/soc/mediatek/common/include/soc/msdc.h index 798b0f6..0f8ba7a 100644 --- a/src/soc/mediatek/common/include/soc/msdc.h +++ b/src/soc/mediatek/common/include/soc/msdc.h @@ -4,6 +4,7 @@ #define SOC_MEDIATEK_COMMON_MSDC_H #include <commonlib/sd_mmc_ctrlr.h> +#include <console/console.h> /*------------------------------*/ /* Register Offset */ diff --git a/src/soc/mediatek/common/msdc.c b/src/soc/mediatek/common/msdc.c index a5a8a6b..8208886 100644 --- a/src/soc/mediatek/common/msdc.c +++ b/src/soc/mediatek/common/msdc.c @@ -6,6 +6,7 @@ #include <cbmem.h> #include <commonlib/bsd/helpers.h> #include <commonlib/storage/sd_mmc.h> +#include <console/console.h> #include <delay.h> #include <device/mmio.h> #include <lib.h> diff --git a/src/soc/mediatek/mt8173/include/soc/dramc_pi_api.h b/src/soc/mediatek/mt8173/include/soc/dramc_pi_api.h index 8ead392..8eb58d0 100644 --- a/src/soc/mediatek/mt8173/include/soc/dramc_pi_api.h +++ b/src/soc/mediatek/mt8173/include/soc/dramc_pi_api.h @@ -6,7 +6,6 @@ #include <soc/dramc_common.h> #include <soc/dramc_soc.h> #include <soc/emi.h> -#include <console/console.h> enum { MAX_CLKO_DELAY = 15 diff --git a/src/soc/mediatek/mt8183/i2c.c b/src/soc/mediatek/mt8183/i2c.c index 193f4b9..1aaa236 100644 --- a/src/soc/mediatek/mt8183/i2c.c +++ b/src/soc/mediatek/mt8183/i2c.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <assert.h> +#include <console/console.h> #include <device/mmio.h> #include <soc/i2c.h> #include <soc/gpio.h> diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h index 5ee6300..707c867 100644 --- a/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h +++ b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h @@ -6,7 +6,6 @@ #include <types.h> #include <soc/dramc_common.h> #include <soc/emi.h> -#include <console/console.h> #define DATLAT_TAP_NUMBER 32 #define HW_REG_SHUFFLE_MAX 4 diff --git a/src/soc/mediatek/mt8192/i2c.c b/src/soc/mediatek/mt8192/i2c.c index 5f1e3a0..6d88833 100644 --- a/src/soc/mediatek/mt8192/i2c.c +++ b/src/soc/mediatek/mt8192/i2c.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <assert.h> +#include <console/console.h> #include <device/mmio.h> #include <soc/i2c.h> #include <soc/gpio.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/61043 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I93f930de5a2a477ec4c0d8e5c8c57b25f5e4252c Gerrit-Change-Number: 61043 Gerrit-PatchSet: 4 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: src/soc/mediatek: Remove unused <console/console.h>
by Felix Held (Code Review) 27 Mar '22

27 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60917 ) Change subject: src/soc/mediatek: Remove unused <console/console.h> ...................................................................... src/soc/mediatek: Remove unused <console/console.h> Found using: diff <(git grep -l '#include <console/console.h>' -- src/) <(git grep -l 'console_time_report\|console_time_get_and_reset\|do_putchar\|vprintk\|printk\|console_log_level\|console_init\|get_log_level\|CONSOLE_ENABLE\|get_console_loglevel\|die_notify\|die_with_post_code\|die\|arch_post_code\|mainboard_post\|post_code\|RAM_SPEW\|RAM_DEBUG\|BIOS_EMERG\|BIOS_ALERT\|BIOS_CRIT\|BIOS_ERR\|BIOS_WARNING\|BIOS_NOTICE\|BIOS_INFO\|BIOS_DEBUG\|BIOS_SPEW\|BIOS_NEVER' -- src/) |grep "<" Change-Id: Ifc85ed8b5660eca11be50fddda0cf32aa1dd611c Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60917 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Hung-Te Lin <hungte(a)chromium.org> --- M src/soc/mediatek/common/dram_init.c M src/soc/mediatek/mt8192/pmif_clk.c M src/soc/mediatek/mt8195/dp_intf.c M src/soc/mediatek/mt8195/pmif_clk.c 4 files changed, 0 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Hung-Te Lin: Looks good to me, approved diff --git a/src/soc/mediatek/common/dram_init.c b/src/soc/mediatek/common/dram_init.c index cfcf84b..d94c3fc 100644 --- a/src/soc/mediatek/common/dram_init.c +++ b/src/soc/mediatek/common/dram_init.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <console/console.h> #include <stdint.h> #include <soc/dramc_common.h> #include <soc/dramc_param.h> diff --git a/src/soc/mediatek/mt8192/pmif_clk.c b/src/soc/mediatek/mt8192/pmif_clk.c index e5c0d1d..c814e81 100644 --- a/src/soc/mediatek/mt8192/pmif_clk.c +++ b/src/soc/mediatek/mt8192/pmif_clk.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <commonlib/helpers.h> -#include <console/console.h> #include <delay.h> #include <device/mmio.h> #include <soc/infracfg.h> diff --git a/src/soc/mediatek/mt8195/dp_intf.c b/src/soc/mediatek/mt8195/dp_intf.c index aba7d78..69a7740 100644 --- a/src/soc/mediatek/mt8195/dp_intf.c +++ b/src/soc/mediatek/mt8195/dp_intf.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <console/console.h> #include <device/mmio.h> #include <edid.h> #include <soc/addressmap.h> diff --git a/src/soc/mediatek/mt8195/pmif_clk.c b/src/soc/mediatek/mt8195/pmif_clk.c index c6d65ce..074657e 100644 --- a/src/soc/mediatek/mt8195/pmif_clk.c +++ b/src/soc/mediatek/mt8195/pmif_clk.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <commonlib/helpers.h> -#include <console/console.h> #include <delay.h> #include <device/mmio.h> #include <soc/infracfg.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/60917 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifc85ed8b5660eca11be50fddda0cf32aa1dd611c Gerrit-Change-Number: 60917 Gerrit-PatchSet: 4 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: src: Remove unused <bootmode.h>
by Felix Held (Code Review) 27 Mar '22

27 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60911 ) Change subject: src: Remove unused <bootmode.h> ...................................................................... src: Remove unused <bootmode.h> Found using: diff <(git grep -l '#include <bootmode.h>' -- src/) <(git grep -l 'platform_is_resuming\|gfx_set_init_done\|gfx_get_init_done\|display_init_required\|get_ec_is_trusted\|get_lid_switch\|get_wipeout_mode_switch\|clear_recovery_mode_switch\|get_recovery_mode_retrain_switch\|get_recovery_mode_switch\|get_recovery_mode_retrain_switch\|get_recovery_mode_switch\|get_write_protect_state\|init_bootmode_straps' -- src/) |grep "<" Change-Id: I2ebd472e0cfc641bd7e465b8d29272fd2f7520a1 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60911 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Hung-Te Lin <hungte(a)chromium.org> --- M src/drivers/intel/fsp2_0/memory_init.c M src/soc/mediatek/common/memory.c M src/soc/qualcomm/common/qclib.c 3 files changed, 0 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Hung-Te Lin: Looks good to me, approved diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index 1612089..4f95462 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -3,7 +3,6 @@ #include <security/vboot/antirollback.h> #include <arch/symbols.h> #include <assert.h> -#include <bootmode.h> #include <cbfs.h> #include <cbmem.h> #include <cf9_reset.h> diff --git a/src/soc/mediatek/common/memory.c b/src/soc/mediatek/common/memory.c index 2e460ae..0850d0f 100644 --- a/src/soc/mediatek/common/memory.c +++ b/src/soc/mediatek/common/memory.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <assert.h> -#include <bootmode.h> #include <cbfs.h> #include <cbmem.h> #include <commonlib/bsd/mem_chip_info.h> diff --git a/src/soc/qualcomm/common/qclib.c b/src/soc/qualcomm/common/qclib.c index 9a485db..43b6399 100644 --- a/src/soc/qualcomm/common/qclib.c +++ b/src/soc/qualcomm/common/qclib.c @@ -2,7 +2,6 @@ #include <console/cbmem_console.h> #include <cbmem.h> -#include <bootmode.h> #include <string.h> #include <fmap.h> #include <assert.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/60911 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2ebd472e0cfc641bd7e465b8d29272fd2f7520a1 Gerrit-Change-Number: 60911 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/var/brya0: Replace amp max98357 with max98360
by Felix Held (Code Review) 27 Mar '22

27 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62998 ) Change subject: mb/google/brya/var/brya0: Replace amp max98357 with max98360 ...................................................................... mb/google/brya/var/brya0: Replace amp max98357 with max98360 Based on Brya EVT schametic, replace audio amp max98357 with max98360. Add a new audio FW_CONFIG field to support ALC5682I+MAX98360. BUG=b:224423056 BRANCH=firmware-brya-14505.B TEST=dmidecode -t 11 Change-Id: I3033e31cf5c2dade02dc19531f5e5365eeeb7a78 Signed-off-by: Amanda Huang <amanda_hwang(a)compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62998 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/variants/brya0/fw_config.c M src/mainboard/google/brya/variants/brya0/overridetree.cb 2 files changed, 22 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Frank Wu: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/brya0/fw_config.c b/src/mainboard/google/brya/variants/brya0/fw_config.c index 17d284a..e1c6f89 100644 --- a/src/mainboard/google/brya/variants/brya0/fw_config.c +++ b/src/mainboard/google/brya/variants/brya0/fw_config.c @@ -126,5 +126,10 @@ printk(BIOS_INFO, "Configure audio over I2S with ALC1019 NAU88L25B.\n"); enable_i2s(); } + + if (fw_config_probe(FW_CONFIG(AUDIO, MAX98360_ALC5682I_I2S_AMP_SSP2))) { + printk(BIOS_INFO, "Configure audio over I2S with MAX98360 ALC5682I.\n"); + enable_i2s(); + } } BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL); diff --git a/src/mainboard/google/brya/variants/brya0/overridetree.cb b/src/mainboard/google/brya/variants/brya0/overridetree.cb index 0f1c693..e566067 100644 --- a/src/mainboard/google/brya/variants/brya0/overridetree.cb +++ b/src/mainboard/google/brya/variants/brya0/overridetree.cb @@ -12,11 +12,12 @@ option KB_BL_PRESENT 1 end field AUDIO 8 10 - option AUDIO_UNKNOWN 0 - option MAX98357_ALC5682I_I2S 1 - option MAX98373_ALC5682_SNDW 2 - option MAX98373_NAU88L25B_I2S 3 - option ALC1019_NAU88L25B_I2S 4 + option AUDIO_UNKNOWN 0 + option MAX98357_ALC5682I_I2S 1 + option MAX98373_ALC5682_SNDW 2 + option MAX98373_NAU88L25B_I2S 3 + option ALC1019_NAU88L25B_I2S 4 + option MAX98360_ALC5682I_I2S_AMP_SSP2 5 end field DB_LTE 11 12 option LTE_ABSENT 0 @@ -254,6 +255,7 @@ register "property_list[0].integer" = "1" device i2c 1a on probe AUDIO MAX98357_ALC5682I_I2S + probe AUDIO MAX98360_ALC5682I_I2S_AMP_SSP2 end end chip drivers/i2c/nau8825 @@ -611,6 +613,16 @@ end end + chip drivers/generic/max98357a + register "hid" = ""MX98360A"" + register "sdmode_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)" + register "sdmode_delay" = "5" + device generic 0 on + probe AUDIO MAX98360_ALC5682I_I2S_AMP_SSP2 + end + end + chip drivers/intel/soundwire device generic 0 on probe AUDIO MAX98373_ALC5682_SNDW -- To view, visit https://review.coreboot.org/c/coreboot/+/62998 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3033e31cf5c2dade02dc19531f5e5365eeeb7a78 Gerrit-Change-Number: 62998 Gerrit-PatchSet: 5 Gerrit-Owner: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/intel/adlrvp: Select VBOOT_MOCK_SECDATA for ADL-N
by Felix Held (Code Review) 27 Mar '22

27 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62957 ) Change subject: mb/intel/adlrvp: Select VBOOT_MOCK_SECDATA for ADL-N ...................................................................... mb/intel/adlrvp: Select VBOOT_MOCK_SECDATA for ADL-N Use MOCK TPM in vboot, since TPM is not enabled in ADLN RVP. BRANCH:NONE TEST=build and boot ADL-N RVP. Verify no TPM errors in depthcharge. Signed-off-by: Usha P <usha.p(a)intel.com> Change-Id: Ibc0112545dbd80921d89d48eff58c512729243af Reviewed-on: https://review.coreboot.org/c/coreboot/+/62957 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Reviewed-by: Reka Norman <rekanorman(a)chromium.org> Reviewed-by: Kangheui Won <khwon(a)chromium.org> --- M src/mainboard/intel/adlrvp/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Rizwan Qureshi: Looks good to me, approved Kangheui Won: Looks good to me, approved Reka Norman: Looks good to me, approved diff --git a/src/mainboard/intel/adlrvp/Kconfig b/src/mainboard/intel/adlrvp/Kconfig index 927b8ed..0d32746 100644 --- a/src/mainboard/intel/adlrvp/Kconfig +++ b/src/mainboard/intel/adlrvp/Kconfig @@ -150,7 +150,7 @@ config VBOOT select VBOOT_LID_SWITCH - select VBOOT_MOCK_SECDATA if BOARD_INTEL_ADLRVP_P_EXT_EC + select VBOOT_MOCK_SECDATA if BOARD_INTEL_ADLRVP_P_EXT_EC || BOARD_INTEL_ADLRVP_N_EXT_EC select EC_GOOGLE_CHROMEEC_SWITCHES if ADL_CHROME_EC select VBOOT_EARLY_EC_SYNC if BOARD_INTEL_ADLRVP_M_EXT_EC -- To view, visit https://review.coreboot.org/c/coreboot/+/62957 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibc0112545dbd80921d89d48eff58c512729243af Gerrit-Change-Number: 62957 Gerrit-PatchSet: 2 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: amdfwtool: Add ISH header support for A/B recovery layout
by Felix Held (Code Review) 27 Mar '22

27 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/57747 ) Change subject: amdfwtool: Add ISH header support for A/B recovery layout ...................................................................... amdfwtool: Add ISH header support for A/B recovery layout Image Slot Header (ISH) is a new feature. The rom layout for A/B recovery with ISH: EFS -> PSP L1 0x48 -> ISH A -> PSP L2 A -> BIOS L2 A 0x4A -> ISH B -> PSP L2 B -> BIOS L2 B The newer 55758 will updated about the boot priority and update retry in ISH header. Change-Id: Ib0690cde1dce949514c7aacebe13096b7814ceff Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57747 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M util/amdfwtool/Makefile M util/amdfwtool/Makefile.inc M util/amdfwtool/amdfwtool.c M util/amdfwtool/amdfwtool.h 4 files changed, 62 insertions(+), 12 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/util/amdfwtool/Makefile b/util/amdfwtool/Makefile index 1805459..7b77935 100644 --- a/util/amdfwtool/Makefile +++ b/util/amdfwtool/Makefile @@ -5,7 +5,7 @@ SRC = amdfwtool.c data_parse.c OBJ = $(SRC:%.c=%.o) TARGET = amdfwtool -WERROR=-Werror -Wno-unused-function +WERROR=-Werror CFLAGS=-O2 -Wall -Wextra -Wshadow ${WERROR} all: $(TARGET) diff --git a/util/amdfwtool/Makefile.inc b/util/amdfwtool/Makefile.inc index f772299..4b7db76 100644 --- a/util/amdfwtool/Makefile.inc +++ b/util/amdfwtool/Makefile.inc @@ -2,7 +2,7 @@ amdfwtoolobj = amdfwtool.o data_parse.o -AMDFWTOOLCFLAGS=-O2 -Wall -Wextra -Wshadow -Werror -Wno-unused-function +AMDFWTOOLCFLAGS=-O2 -Wall -Wextra -Wshadow -Werror $(objutil)/amdfwtool/%.o: $(top)/util/amdfwtool/%.c # $(HEADER) $(HOSTCC) $(AMDFWTOOLCFLAGS) $(HOSTCFLAGS) -c -o $@ $< diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index 263336a..f0fdd0a 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -421,6 +421,15 @@ return ptr; } +static void *new_ish_dir(context *ctx) +{ + void *ptr; + ctx->current = ALIGN(ctx->current, TABLE_ALIGNMENT); + ptr = BUFF_CURRENT(*ctx); + ctx->current += TABLE_ALIGNMENT; + return ptr; +} + #if PSP_COMBO static void *new_combo_dir(context *ctx) { @@ -672,7 +681,8 @@ } static void integrate_psp_ab(context *ctx, psp_directory_table *pspdir, - psp_directory_table *pspdir2, amd_fw_type ab) + psp_directory_table *pspdir2, ish_directory_table *ish, + amd_fw_type ab, enum platform soc_id) { uint32_t count; uint32_t current_table_save; @@ -684,11 +694,28 @@ pspdir->entries[count].type = (uint8_t)ab; pspdir->entries[count].subprog = 0; pspdir->entries[count].rsvd = 0; - pspdir->entries[count].addr = BUFF_TO_RUN_MODE(*ctx, pspdir2, ADDRESS_MODE_1_REL_BIOS); - pspdir->entries[count].address_mode = SET_ADDR_MODE(pspdir, ADDRESS_MODE_1_REL_BIOS); - pspdir->entries[count].size = pspdir2->header.num_entries * + if (ish != NULL) { + ish->pl2_location = BUFF_TO_RUN_MODE(*ctx, pspdir2, ADDRESS_MODE_1_REL_BIOS); + ish->boot_priority = ab == AMD_FW_RECOVERYAB_A ? 0xFFFFFFFF : 1; + ish->update_retry_count = 2; + ish->glitch_retry_count = 0; + ish->psp_id = get_psp_id(soc_id); + ish->checksum = fletcher32(&ish->boot_priority, + sizeof(ish_directory_table) - sizeof(uint32_t)); + pspdir->entries[count].addr = + BUFF_TO_RUN_MODE(*ctx, ish, ADDRESS_MODE_1_REL_BIOS); + pspdir->entries[count].address_mode = + SET_ADDR_MODE(pspdir, ADDRESS_MODE_1_REL_BIOS); + pspdir->entries[count].size = TABLE_ALIGNMENT; + } else { + pspdir->entries[count].addr = + BUFF_TO_RUN_MODE(*ctx, pspdir2, ADDRESS_MODE_1_REL_BIOS); + pspdir->entries[count].address_mode = + SET_ADDR_MODE(pspdir, ADDRESS_MODE_1_REL_BIOS); + pspdir->entries[count].size = pspdir2->header.num_entries * sizeof(psp_directory_entry) + sizeof(psp_directory_header); + } count++; pspdir->header.num_entries = count; @@ -701,6 +728,7 @@ psp_directory_table *pspdir2_b, amd_fw_entry *fw_table, uint32_t cookie, + enum platform soc_id, amd_cb_config *cb_config) { ssize_t bytes; @@ -708,6 +736,7 @@ int level; uint32_t current_table_save; bool recovery_ab = cb_config->recovery_ab; + ish_directory_table *ish_a_dir = NULL, *ish_b_dir = NULL; /* This function can create a primary table, a secondary table, or a * flattened table which contains all applicable types. These if-else @@ -815,10 +844,17 @@ } if (recovery_ab && (pspdir2 != NULL)) { + if (cb_config->need_ish) { /* Need ISH */ + ish_a_dir = new_ish_dir(ctx); + if (pspdir2_b != NULL) + ish_b_dir = new_ish_dir(ctx); + } pspdir->header.num_entries = count; - integrate_psp_ab(ctx, pspdir, pspdir2, AMD_FW_RECOVERYAB_A); + integrate_psp_ab(ctx, pspdir, pspdir2, ish_a_dir, + AMD_FW_RECOVERYAB_A, soc_id); if (pspdir2_b != NULL) - integrate_psp_ab(ctx, pspdir, pspdir2_b, AMD_FW_RECOVERYAB_B); + integrate_psp_ab(ctx, pspdir, pspdir2_b, ish_b_dir, + AMD_FW_RECOVERYAB_B, soc_id); count = pspdir->header.num_entries; } else if (pspdir2 != NULL) { assert_fw_entry(count, MAX_PSP_ENTRIES, ctx); @@ -1455,6 +1491,7 @@ cb_config.s0i3 = false; cb_config.multi_level = false; cb_config.recovery_ab = false; + cb_config.need_ish = false; while (1) { int optindex = 0; @@ -1777,25 +1814,25 @@ /* Do 2nd PSP directory followed by 1st */ pspdir2 = new_psp_dir(&ctx, cb_config.multi_level); integrate_psp_firmwares(&ctx, pspdir2, NULL, NULL, - amd_psp_fw_table, PSPL2_COOKIE, &cb_config); + amd_psp_fw_table, PSPL2_COOKIE, soc_id, &cb_config); if (cb_config.recovery_ab) { /* B is same as above directories for A */ /* Skip creating pspdir2_b here to save flash space. Related * biosdir2_b will be skipped automatically. */ pspdir2_b = new_psp_dir(&ctx, cb_config.multi_level); integrate_psp_firmwares(&ctx, pspdir2_b, NULL, NULL, - amd_psp_fw_table, PSPL2_COOKIE, &cb_config); + amd_psp_fw_table, PSPL2_COOKIE, soc_id, &cb_config); } else { pspdir2_b = NULL; /* More explicitly */ } pspdir = new_psp_dir(&ctx, cb_config.multi_level); integrate_psp_firmwares(&ctx, pspdir, pspdir2, pspdir2_b, - amd_psp_fw_table, PSP_COOKIE, &cb_config); + amd_psp_fw_table, PSP_COOKIE, soc_id, &cb_config); } else { /* flat: PSP 1 cookie and no pointer to 2nd table */ pspdir = new_psp_dir(&ctx, cb_config.multi_level); integrate_psp_firmwares(&ctx, pspdir, NULL, NULL, - amd_psp_fw_table, PSP_COOKIE, &cb_config); + amd_psp_fw_table, PSP_COOKIE, soc_id, &cb_config); } if (comboable) diff --git a/util/amdfwtool/amdfwtool.h b/util/amdfwtool/amdfwtool.h index ff2f63b..a241316 100644 --- a/util/amdfwtool/amdfwtool.h +++ b/util/amdfwtool/amdfwtool.h @@ -235,6 +235,18 @@ int level; } amd_bios_entry; +typedef struct _ish_directory_table { + uint32_t checksum; + uint32_t boot_priority; + uint32_t update_retry_count; + uint8_t glitch_retry_count; + uint8_t glitch_higherbits_reserved[3]; + uint32_t pl2_location; + uint32_t psp_id; + uint32_t slot_max_size; + uint32_t reserved; +} __attribute__((packed)) ish_directory_table; + #define EMBEDDED_FW_SIGNATURE 0x55aa55aa #define PSP_COOKIE 0x50535024 /* 'PSP$' */ #define PSPL2_COOKIE 0x324c5024 /* '2LP$' */ @@ -265,6 +277,7 @@ bool s0i3; bool have_mb_spl; bool recovery_ab; + bool need_ish; } amd_cb_config; void register_fw_fuse(char *str); -- To view, visit https://review.coreboot.org/c/coreboot/+/57747 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib0690cde1dce949514c7aacebe13096b7814ceff Gerrit-Change-Number: 57747 Gerrit-PatchSet: 67 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bao Zheng <zheng.bao(a)amd.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: merged

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