coreboot-gerrit March 2022

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Change in coreboot[master]: src/acpi/acpigen_usb.c: Fix Memory leak error
by vaibhav (Code Review) 27 Mar '22

27 Mar '22

vaibhav has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/62968 ) Change subject: src/acpi/acpigen_usb.c: Fix Memory leak error ...................................................................... Abandoned The error detected by scan-build is trivial -- To view, visit https://review.coreboot.org/c/coreboot/+/62968 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifed611bd0b9c1da3678386bff33bca3eac0311b4 Gerrit-Change-Number: 62968 Gerrit-PatchSet: 1 Gerrit-Owner: vaibhav <vrockz747(a)gmail.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: soc/intel/common: Add IOE SBI access for TCSS functions
by build bot (Jenkins) (Code Review) 27 Mar '22

27 Mar '22

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63128 ) Change subject: soc/intel/common: Add IOE SBI access for TCSS functions ...................................................................... Patch Set 2: Verified+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/63128 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I324242a018fb47207dd426fc8acd103f677d5cab Gerrit-Change-Number: 63128 Gerrit-PatchSet: 2 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 27 Mar 2022 16:31:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Abstract the common TCSS functions
by build bot (Jenkins) (Code Review) 27 Mar '22

27 Mar '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Paul Menzel, Eric Lai, Angel Pons, Patrick Rudolph, EricR Lai. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62723 ) Change subject: soc/intel/common: Abstract the common TCSS functions ...................................................................... Patch Set 11: Verified+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/62723 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3302aabfb5f540c41da6359f11376b4202c6310b Gerrit-Change-Number: 62723 Gerrit-PatchSet: 11 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Sun, 27 Mar 2022 16:31:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Add IOE SBI access for TCSS functions
by John Zhao (Code Review) 27 Mar '22

27 Mar '22

John Zhao has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/63128 ) Change subject: soc/intel/common: Add IOE SBI access for TCSS functions ...................................................................... soc/intel/common: Add IOE SBI access for TCSS functions Meteor Lake has the IOE Die for TCSS. This change adds IOE SBI access for TCSS pad configuration and Thunderbolt authentication. BUG=b:213574324 TEST=Build platforms coreboot images successfully. Change-Id: I324242a018fb47207dd426fc8acd103f677d5cab Signed-off-by: John Zhao <john.zhao(a)intel.com> --- M src/soc/intel/common/block/include/intelblocks/tcss.h M src/soc/intel/common/block/tcss/tcss.c 2 files changed, 20 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/63128/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63128 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I324242a018fb47207dd426fc8acd103f677d5cab Gerrit-Change-Number: 63128 Gerrit-PatchSet: 2 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common: Abstract the common TCSS functions
by John Zhao (Code Review) 27 Mar '22

27 Mar '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Paul Menzel, Eric Lai, Angel Pons, Patrick Rudolph, EricR Lai. Hello build bot (Jenkins), Subrata Banik, Wonkyu Kim, Eric Lai, Angel Pons, Patrick Rudolph, EricR Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62723 to look at the new patch set (#11). Change subject: soc/intel/common: Abstract the common TCSS functions ...................................................................... soc/intel/common: Abstract the common TCSS functions This change abstracts the common TCSS functions for pad configuration and Thunderbolt authentication. BUG=b:213574324 TEST=Build platforms coreboot images successfully. Change-Id: I3302aabfb5f540c41da6359f11376b4202c6310b Signed-off-by: John Zhao <john.zhao(a)intel.com> --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/common/block/include/intelblocks/cfg.h M src/soc/intel/common/block/include/intelblocks/tcss.h M src/soc/intel/common/block/tcss/Kconfig M src/soc/intel/common/block/tcss/tcss.c M src/soc/intel/common/block/usb4/usb4.c M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/fsp_params.c 9 files changed, 41 insertions(+), 42 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/62723/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/62723 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3302aabfb5f540c41da6359f11376b4202c6310b Gerrit-Change-Number: 62723 Gerrit-PatchSet: 11 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common: Add IOE SBI access for TCSS functions
by John Zhao (Code Review) 27 Mar '22

27 Mar '22

John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63128 ) Change subject: soc/intel/common: Add IOE SBI access for TCSS functions ...................................................................... soc/intel/common: Add IOE SBI access for TCSS functions Meteor Lake has the IOE Die for TCSS. This change adds IOE SBI access for TCSS pad configuration and Thunderbolt authentication. BUG=b:213574324 TEST=Build platforms coreboot images successfully. Change-Id: I324242a018fb47207dd426fc8acd103f677d5cab Signed-off-by: John Zhao <john.zhao(a)intel.com> --- M src/soc/intel/common/block/include/intelblocks/tcss.h M src/soc/intel/common/block/tcss/tcss.c 2 files changed, 20 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/63128/1 diff --git a/src/soc/intel/common/block/include/intelblocks/tcss.h b/src/soc/intel/common/block/include/intelblocks/tcss.h index e08b42c..894648d 100644 --- a/src/soc/intel/common/block/include/intelblocks/tcss.h +++ b/src/soc/intel/common/block/include/intelblocks/tcss.h @@ -144,6 +144,7 @@ /* Method to configure pads */ void tcss_configure_aux_bias_pads_regbar(const struct typec_aux_bias_pads *pads); +void ioe_tcss_configure_aux_bias_pads_sbi(const struct typec_aux_bias_pads *pads); /* * 1) Initialize TCSS muxes to disconnected state @@ -162,5 +163,6 @@ /* Method to validate the Thunderbolt authentication */ bool tcss_valid_tbt_auth(void); +bool ioe_tcss_valid_tbt_auth(void); #endif /* _TCSS_H_ */ diff --git a/src/soc/intel/common/block/tcss/tcss.c b/src/soc/intel/common/block/tcss/tcss.c index 7ceeedc..e738b1a 100644 --- a/src/soc/intel/common/block/tcss/tcss.c +++ b/src/soc/intel/common/block/tcss/tcss.c @@ -368,6 +368,19 @@ } } +void ioe_tcss_configure_aux_bias_pads_sbi( + const struct typec_aux_bias_pads *pads) +{ + for (size_t i = 0; i < MAX_TYPE_C_PORTS; i++) { + if (pads[i].pad_auxn_dc && pads[i].pad_auxp_dc) { + ioe_p2sb_sbi_write(PID_IOM, IOM_AUX_BIAS_CTRL_PULLUP_OFFSET(i), + calc_bias_ctrl_reg_value(pads[i].pad_auxp_dc)); + ioe_p2sb_sbi_write(PID_IOM, IOM_AUX_BIAS_CTRL_PULLDOWN_OFFSET(i), + calc_bias_ctrl_reg_value(pads[i].pad_auxn_dc)); + } + } +} + const struct tcss_port_map *tcss_get_port_info(size_t *num_ports) { static struct tcss_port_map port_map[MAX_TYPE_C_PORTS]; @@ -424,3 +437,8 @@ { return REGBAR32(PID_IOM, IOM_CSME_IMR_TBT_STATUS) & TBT_VALID_AUTHENTICATION; } + +bool ioe_tcss_valid_tbt_auth(void) +{ + return ioe_p2sb_sbi_read(PID_IOM, IOM_CSME_IMR_TBT_STATUS) & TBT_VALID_AUTHENTICATION; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/63128 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I324242a018fb47207dd426fc8acd103f677d5cab Gerrit-Change-Number: 63128 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common: Abstract the common TCSS functions
by John Zhao (Code Review) 27 Mar '22

27 Mar '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Paul Menzel, Eric Lai, Angel Pons, Patrick Rudolph, EricR Lai. Hello build bot (Jenkins), Subrata Banik, Wonkyu Kim, Eric Lai, Angel Pons, Patrick Rudolph, EricR Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62723 to look at the new patch set (#10). Change subject: soc/intel/common: Abstract the common TCSS functions ...................................................................... soc/intel/common: Abstract the common TCSS functions This change abstracts the common TCSS functions for pad configuration and Thunderbolt authentication. BUG=b:213574324 TEST=Build platforms coreboot images successfully. Change-Id: I3302aabfb5f540c41da6359f11376b4202c6310b Signed-off-by: John Zhao <john.zhao(a)intel.com> --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/common/block/include/intelblocks/cfg.h M src/soc/intel/common/block/include/intelblocks/tcss.h M src/soc/intel/common/block/tcss/Kconfig M src/soc/intel/common/block/tcss/tcss.c M src/soc/intel/common/block/usb4/usb4.c M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/fsp_params.c 9 files changed, 41 insertions(+), 42 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/62723/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/62723 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3302aabfb5f540c41da6359f11376b4202c6310b Gerrit-Change-Number: 62723 Gerrit-PatchSet: 10 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/sabrina/Kconfig: update SOC_AMD_COMMON_BLOCK_UCODE_SIZE
by Felix Held (Code Review) 27 Mar '22

27 Mar '22

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63127 ) Change subject: soc/amd/sabrina/Kconfig: update SOC_AMD_COMMON_BLOCK_UCODE_SIZE ...................................................................... soc/amd/sabrina/Kconfig: update SOC_AMD_COMMON_BLOCK_UCODE_SIZE The Sabrina microcode update files are 3200 bytes large and not 5568 like it is the case on Cezanne where this file was originally copied from. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I12209d523096781195ba8957ec797d8c80eecbe5 --- M src/soc/amd/sabrina/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/63127/1 diff --git a/src/soc/amd/sabrina/Kconfig b/src/soc/amd/sabrina/Kconfig index 8392e2f..bef4160 100644 --- a/src/soc/amd/sabrina/Kconfig +++ b/src/soc/amd/sabrina/Kconfig @@ -87,7 +87,7 @@ default n config SOC_AMD_COMMON_BLOCK_UCODE_SIZE - default 5568 + default 3200 config CHIPSET_DEVICETREE string -- To view, visit https://review.coreboot.org/c/coreboot/+/63127 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I12209d523096781195ba8957ec797d8c80eecbe5 Gerrit-Change-Number: 63127 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/skyrim: Add DXIO descriptors
by Felix Held (Code Review) 27 Mar '22

27 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62903 ) Change subject: mb/google/skyrim: Add DXIO descriptors ...................................................................... mb/google/skyrim: Add DXIO descriptors Add Skyrim DXIO descriptors using info from AMD and skyrim bouard shematics. BUG=b:225179599 TEST=Boots to OS on Skyrim Board Signed-off-by: Jon Murphy <jpmurphy(a)google.com> Change-Id: Ib68cf3d64641b006e0f2c4805af22b44a505a0d1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62903 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/mainboard/google/skyrim/port_descriptors.c M src/mainboard/google/skyrim/variants/baseboard/devicetree.cb M src/mainboard/google/skyrim/variants/baseboard/include/baseboard/variants.h 3 files changed, 83 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/mainboard/google/skyrim/port_descriptors.c b/src/mainboard/google/skyrim/port_descriptors.c index 56bd9f3..64255f2 100644 --- a/src/mainboard/google/skyrim/port_descriptors.c +++ b/src/mainboard/google/skyrim/port_descriptors.c @@ -1,11 +1,86 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <baseboard/variants.h> +#include <soc/gpio.h> #include <soc/platform_descriptors.h> #include <types.h> +static const fsp_dxio_descriptor skyrim_sbna_dxio_descriptors[] = { + { /* WLAN */ + .engine_type = PCIE_ENGINE, + .port_present = true, + .start_logical_lane = 0, + .end_logical_lane = 0, + .device_number = PCI_SLOT(WLAN_DEVFN), + .function_number = PCI_FUNC(WLAN_DEVFN), + .link_speed_capability = GEN3, + .turn_off_unused_lanes = true, + .link_aspm = 2, + .link_hotplug = 3, + .clk_req = CLK_REQ2, + }, + { /* SD */ + .engine_type = PCIE_ENGINE, + .port_present = true, + .start_logical_lane = 1, + .end_logical_lane = 1, + .device_number = PCI_SLOT(SD_DEVFN), + .function_number = PCI_FUNC(SD_DEVFN), + .link_speed_capability = GEN3, + .turn_off_unused_lanes = true, + .gpio_group_id = GPIO_27, + .clk_req = CLK_REQ1, + }, + { /* SSD */ + .engine_type = PCIE_ENGINE, + .port_present = true, + .start_logical_lane = 2, + .end_logical_lane = 3, + .device_number = PCI_SLOT(NVME_DEVFN), + .function_number = PCI_FUNC(NVME_DEVFN), + .link_speed_capability = GEN3, + .turn_off_unused_lanes = true, + .link_aspm = 2, + .link_hotplug = 3, + .gpio_group_id = GPIO_6, + .clk_req = CLK_REQ0, + }, +}; + +static const fsp_ddi_descriptor skyrim_sbna_ddi_descriptors[] = { + { /* DDI0 - eDP */ + .connector_type = DDI_EDP, + .aux_index = DDI_AUX1, + .hdp_index = DDI_HDP1 + }, + { /* DDI1 - DP (type C) */ + .connector_type = DDI_DP, + .aux_index = DDI_AUX2, + .hdp_index = DDI_HDP2 + }, + { /* DDI2 - DP (type C) */ + .connector_type = DDI_DP, + .aux_index = DDI_AUX3, + .hdp_index = DDI_HDP3, + }, + { /* DDI3 - DP (type C) */ + .connector_type = DDI_DP, + .aux_index = DDI_AUX4, + .hdp_index = DDI_HDP4, + }, + { /* DDI4 - Unused */ + .connector_type = DDI_UNUSED_TYPE, + .aux_index = DDI_AUX5, + .hdp_index = DDI_HDP5, + }, +}; + void mainboard_get_dxio_ddi_descriptors( const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num, const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num) { - /* TODO: Initialize DXIO and DDI descriptors */ + *dxio_descs = skyrim_sbna_dxio_descriptors; + *dxio_num = ARRAY_SIZE(skyrim_sbna_dxio_descriptors); + *ddi_descs = skyrim_sbna_ddi_descriptors; + *ddi_num = ARRAY_SIZE(skyrim_sbna_ddi_descriptors); } diff --git a/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb b/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb index 03bb55e..8fa6ba5 100644 --- a/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb @@ -62,8 +62,7 @@ end end device ref gpp_bridge_1 on end # SD - device ref gpp_bridge_2 on end # WWAN - device ref gpp_bridge_3 on end # NVMe + device ref gpp_bridge_2 on end # NVMe device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A device ref gfx on end # Internal GPU (GFX) diff --git a/src/mainboard/google/skyrim/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/skyrim/variants/baseboard/include/baseboard/variants.h index 0fa3491..64a414b 100644 --- a/src/mainboard/google/skyrim/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/skyrim/variants/baseboard/include/baseboard/variants.h @@ -4,6 +4,12 @@ #define __BASEBOARD_VARIANTS_H__ #include <amdblocks/gpio.h> +#include <soc/pci_devs.h> +#include <platform_descriptors.h> + +#define WLAN_DEVFN PCIE_GPP_2_0_DEVFN +#define SD_DEVFN PCIE_GPP_2_1_DEVFN +#define NVME_DEVFN PCIE_GPP_2_2_DEVFN /* * This function provides base GPIO configuration table. It is typically provided by -- To view, visit https://review.coreboot.org/c/coreboot/+/62903 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib68cf3d64641b006e0f2c4805af22b44a505a0d1 Gerrit-Change-Number: 62903 Gerrit-PatchSet: 14 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/hatch/moonbuggy: Update GPIOs
by Felix Held (Code Review) 27 Mar '22

27 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63014 ) Change subject: mb/google/hatch/moonbuggy: Update GPIOs ...................................................................... mb/google/hatch/moonbuggy: Update GPIOs Implement the GPIOs that have been changed from genesis. - Connect scaler UART on pins C12/C13 - Connect the HDMI redriver I2C on C18/C19 - Connect the iMX8 signals on D1/D2/D3/D21/D22 - Connect the EC interrupt on D14 (same as on scout) - Connect PCH_TYPEC_UPFB on E15 (same as on genesis) - Configure as not connected the following unused pins: D23, E11, E12, F11 -> F22, H0, H8, H9 BUG=b:200876872 TEST=moonbuggy boots Change-Id: Ie9cafe81e391bce6ab7ffbe23c2d57b407d146f3 Signed-off-by: Pablo Ceballos <pceballos(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63014 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/hatch/variants/moonbuggy/gpio.c M src/mainboard/google/hatch/variants/moonbuggy/include/variant/gpio.h M src/mainboard/google/hatch/variants/moonbuggy/overridetree.cb 3 files changed, 59 insertions(+), 40 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/hatch/variants/moonbuggy/gpio.c b/src/mainboard/google/hatch/variants/moonbuggy/gpio.c index ba75fb7..d8f3920 100644 --- a/src/mainboard/google/hatch/variants/moonbuggy/gpio.c +++ b/src/mainboard/google/hatch/variants/moonbuggy/gpio.c @@ -33,65 +33,79 @@ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* C1 : SMBDATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), - /* C3 : PCH_MBCLK1_R (i350) */ + /* C3 : PCH_MBCLK1_R (i350) */ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), - /* C4 : PCH_MBDAT1_R (i350) */ + /* C4 : PCH_MBDAT1_R (i350) */ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), - /* C6: M2_WLAN_WAKE_ODL */ + /* C6 : M2_WLAN_WAKE_ODL */ PAD_CFG_GPI_SCI_LOW(GPP_C6, NONE, DEEP, EDGE_SINGLE), /* C7 : LAN_WAKE_ODL */ PAD_CFG_GPI_SCI_LOW(GPP_C7, NONE, DEEP, EDGE_SINGLE), /* C10 : PCH_PCON_RST_ODL */ PAD_CFG_GPO(GPP_C10, 1, DEEP), - /* C11 : PCH_PCON_PDB_ODL */ + /* C11 : PCH_PCON1_PDB_ODL */ PAD_CFG_GPO(GPP_C11, 1, DEEP), - /* C15 : WLAN_OFF_L */ + /* C12 : PCH_UART1_RX_ADB_TX */ + PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), + /* C13 : PCH_UART1_TX_ADB_RX */ + PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), + /* C15 : WLAN_OFF_L */ PAD_CFG_GPO(GPP_C15, 1, DEEP), + /* C16 : PCH_I2C_RFU_SDA (NC) */ + PAD_NC(GPP_C16, NONE), + /* C17 : PCH_I2C_RFU_SCL (NC) */ + PAD_NC(GPP_C17, NONE), + /* C18 : EC_I2C_HDMI_RE_SCL */ + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), + /* C19 : EC_12C_HDMI_RE_SDA */ + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), + + /* D1 : REC_MODE */ + PAD_CFG_GPO(GPP_D1, 1, DEEP), + /* D2 : DEV_MODE_CTRL */ + PAD_CFG_GPO(GPP_D2, 1, DEEP), + /* D3 : BOOT_IND */ + PAD_CFG_GPI(GPP_D3, NONE, DEEP), + /* D14 : EC_PCH_INT_L */ + PAD_CFG_GPI_APIC(GPP_D14, NONE, PLTRST, LEVEL, INVERT), + /* D21 : BOOT_SEL_N */ + PAD_CFG_GPO(GPP_D21, 1, DEEP), + /* D22 : QSPI_MR_N */ + PAD_CFG_GPO(GPP_D22, 1, DEEP), + /* D23 : Not connected */ + PAD_NC(GPP_D23, NONE), /* E2 : Not connected */ PAD_NC(GPP_E2, NONE), - /* E3 : TPU_RST_PIN40 */ + /* E3 : TPU_BOOT_DELAY_PIN40 */ PAD_CFG_GPO(GPP_E3, 1, DEEP), - /* E7 : TPU_RST_PIN42 */ + /* E7 : TPU_BOOT_DELAY_PIN42 */ PAD_CFG_GPO(GPP_E7, 1, DEEP), /* E9 : PU 10K to PP3300_SOC_A */ PAD_NC(GPP_E9, NONE), /* E10 : USB_A1_OC_ODL */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), + /* E11 : PU 10K to PP3300_SOC_A */ + PAD_NC(GPP_E11, NONE), + /* E12 : PU 10K to PP3300_SOC_A */ + PAD_NC(GPP_E12, NONE), + /* E15 : PCH_TYPEC_UPFB */ + PAD_CFG_GPI(GPP_E15, NONE, DEEP), - /* F11 : EMMC_CMD */ - PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1), - /* F12 : EMMC_DATA0 */ - PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), - /* F13 : EMMC_DATA1 */ - PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), - /* F14 : EMMC_DATA2 */ - PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), - /* F15 : EMMC_DATA3 */ - PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), - /* F16 : EMMC_DATA4 */ - PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), - /* F17 : EMMC_DATA5 */ - PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), - /* F18 : EMMC_DATA6 */ - PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), - /* F19 : EMMC_DATA7 */ - PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), - /* F20 : EMMC_RCLK */ - PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), - /* F21 : EMMC_CLK */ - PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), - /* F22 : EMMC_RST_L */ - PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), - - /* H4: PCH_I2C_PCON_SDA */ + /* H0 : Not connected */ + PAD_NC(GPP_H0, NONE), + /* H4 : PCH_I2C_PCON_SDA */ PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), - /* H5: PCH_I2C_PCON_SCL */ + /* H5 : PCH_I2C_PCON_SCL */ PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), - /* H6 : PCH_I2C_TPU_SDA */ + /* H6 : PCH_I2C_TPU_SDA */ PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), - /* H7 : PCH_I2C_TPU_SCL */ + /* H7 : PCH_I2C_TPU_SCL */ PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), + /* H8 : Not connected */ + PAD_NC(GPP_H8, NONE), + /* H9 : Not connected */ + PAD_NC(GPP_H9, NONE), /* H22 : PWM_PP3300_BIOZZER */ PAD_CFG_GPO(GPP_H22, 0, DEEP), }; @@ -122,7 +136,7 @@ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), /* C14 : BT_DISABLE_L */ PAD_CFG_GPO(GPP_C14, 0, DEEP), - /* PCH_WP_OD */ + /* C20 : PCH_WP_OD */ PAD_CFG_GPI(GPP_C20, NONE, DEEP), /* C21 : H1_PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), @@ -130,9 +144,9 @@ PAD_CFG_GPI(GPP_C22, NONE, DEEP), /* C23 : WLAN_PE_RST# */ PAD_CFG_GPO(GPP_C23, 1, DEEP), - /* E1 : M2_SSD_PEDET */ + /* E1 : M2_SSD_PEDET */ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), - /* E5 : SATA_DEVSLP1 */ + /* E5 : SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1), }; diff --git a/src/mainboard/google/hatch/variants/moonbuggy/include/variant/gpio.h b/src/mainboard/google/hatch/variants/moonbuggy/include/variant/gpio.h index 79a1410..9dd2434 100644 --- a/src/mainboard/google/hatch/variants/moonbuggy/include/variant/gpio.h +++ b/src/mainboard/google/hatch/variants/moonbuggy/include/variant/gpio.h @@ -5,4 +5,7 @@ #include <baseboard/gpio.h> +#undef EC_SYNC_IRQ +#define EC_SYNC_IRQ GPP_D14_IRQ + #endif diff --git a/src/mainboard/google/hatch/variants/moonbuggy/overridetree.cb b/src/mainboard/google/hatch/variants/moonbuggy/overridetree.cb index dd83f4d..1049805 100644 --- a/src/mainboard/google/hatch/variants/moonbuggy/overridetree.cb +++ b/src/mainboard/google/hatch/variants/moonbuggy/overridetree.cb @@ -13,7 +13,7 @@ [PchSerialIoIndexSPI1] = PchSerialIoPci, [PchSerialIoIndexSPI2] = PchSerialIoDisabled, [PchSerialIoIndexUART0] = PchSerialIoSkipInit, - [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART1] = PchSerialIoPci, [PchSerialIoIndexUART2] = PchSerialIoDisabled, }" @@ -451,6 +451,8 @@ device pci 1d.5 on end # PCI Root Port 14 (non-root) device pci 1d.6 on end # PCI Root Port 15 (non-root) device pci 1d.7 on end # PCI Root Port 16 (non-root) + device pci 1e.0 on end # UART #0 + device pci 1e.1 on end # UART #1 device pci 1e.3 off end # GSPI #1 end -- To view, visit https://review.coreboot.org/c/coreboot/+/63014 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie9cafe81e391bce6ab7ffbe23c2d57b407d146f3 Gerrit-Change-Number: 63014 Gerrit-PatchSet: 2 Gerrit-Owner: Pablo Ceballos <pceballos(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit March 2022