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Change subject: mb/intel/adlrvp: Set half_populated true for ADL-N
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
When you did this for nissa, Tim made a comment which I agree with: this feels like a hack, and it would be better to generalise the structures in meminit.h to handle this case properly. It doesn't have to be done now, but I think we should at least file a bug to clean this up at some point.
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Change subject: mb/clevo/tgl-u: add new board L14xMU
......................................................................
Patch Set 13:
(6 comments)
File src/mainboard/clevo/tgl-u/variants/l140mu/gpio.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-144812):
https://review.coreboot.org/c/coreboot/+/59548/comment/3afa195a_9b7bda3a
PS13, Line 94: PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* I2C1_SDA / PCH_I2C_SDA (retimer rom) */
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-144812):
https://review.coreboot.org/c/coreboot/+/59548/comment/fb6ec064_bc0a6862
PS13, Line 95: PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* I2C1_SCL / PCH_I2C_SCL (retimer rom) */
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-144812):
https://review.coreboot.org/c/coreboot/+/59548/comment/59822148_95349945
PS13, Line 99: PAD_NC(GPP_C23, UP_20K), /* GPP_C23 / PCH_GPP_C23 (WLAN_WAKEUP#) */
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-144812):
https://review.coreboot.org/c/coreboot/+/59548/comment/f10bd961_ba4b376e
PS13, Line 104: PAD_NC(GPP_D2, NONE), /* LEDKB_DET# (unused; not sold w/o KBLED) */
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-144812):
https://review.coreboot.org/c/coreboot/+/59548/comment/9e1e38c6_22fb71e9
PS13, Line 107: PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), /* SRCCLKREQ0# / SSD1_CLKREQ# (for SSD2!) */
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-144812):
https://review.coreboot.org/c/coreboot/+/59548/comment/1d9ade38_6622d11c
PS13, Line 110: PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), /* SRCCLKREQ3# / SSD2_CLKREQ# (for SSD1!) */
line over 96 characters
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Change subject: mb/clevo/tgl-u: add new board L14xMU
......................................................................
Patch Set 13:
(7 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/59548/comment/de119df2_bace8c3d
PS8, Line 56:
> Too make it crystal clear, maybe mention “vendor firmware”.
Done
Commit Message:
https://review.coreboot.org/c/coreboot/+/59548/comment/c517ca15_45e2f3ce
PS12, Line 7: mb: add new board clevo/tgl-u/l140mu
> Why not our usual scheme? Suggestion: […]
"our"? CB:45624 ;)
Done, I don't care
File src/mainboard/clevo/tgl-u/Kconfig:
https://review.coreboot.org/c/coreboot/+/59548/comment/b400c0a5_c7dc8672
PS12, Line 48: config VGA_BIOS_ID
: default "8086,9b41"
> This is only needed when an option rom is used. It's not the case here, so remove it.
true, thanks
https://review.coreboot.org/c/coreboot/+/59548/comment/32dc48d8_7a65a573
PS12, Line 51: config TPM_PIRQ
: default 0x77 if BOARD_CLEVO_L140MU # GPP_C9_IRQ
> I would move this to the other options on the top, so that the variant specific options are not scat […]
I don't agree on this one; it doesn't really matter. also, l140cu is the same ;)
https://review.coreboot.org/c/coreboot/+/59548/comment/37d597cf_679b6a70
PS12, Line 57: config VARIANT_DIR
: default "l140mu" if BOARD_CLEVO_L140MU
> Same here.
this file is mostly a copy of l140cu^^ I agree that it fits better near the mainboard dir, though. -> Done
File src/mainboard/clevo/tgl-u/Kconfig.name:
https://review.coreboot.org/c/coreboot/+/59548/comment/c2bdd78f_f84f2152
PS12, Line 4: bool "L140MU / L141MU / L142MU"
> What are the differences between these variants?
just the color, same as for L140CU
File src/mainboard/clevo/tgl-u/variants/l140mu/gpio_early.c:
https://review.coreboot.org/c/coreboot/+/59548/comment/18aa2367_4389dc0e
PS12, Line 10: PAD_NC(GPP_C22, UP_20K),
: PA
> Not needed here. Please remove.
first, it's the same as l140cu here. also, the default is rts/cts, so it makes sense to set them to NC. if you really insist on removing them, reopen please
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Hello Felix Singer, build bot (Jenkins), Paul Menzel, Tim Wawrzynczak,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/59548
to look at the new patch set (#13).
Change subject: mb/clevo/tgl-u: add new board L14xMU
......................................................................
mb/clevo/tgl-u: add new board L14xMU
Add new board Clevo L14xMU (TGL).
GPIOs were configured based on schematics.
Tested and working:
- On-board RAM (M471A1G44AB0-CWE)
- DIMM slot (tested Crucial CT16G4SFD8266.16FJ1 / MTA16ATF2G64HZ-2G6J1)
- Graphics (GOP driver), including HDMI
- Keyboard
- I2C touchpad (including interrupt)
- TPM (with interrupt on Windows, only polling on Linux [1])
- microSD Card reader
- both NVME ports
- Speakers
- Microphone
- Camera
- WLAN/BT (CNVi)
- All USB2/3 ports including Type-C
- Thunderbolt detects my work laptop in TB Control Center
(I couldn't test anything more due to security policy.)
- TianoCore
- internal flashing with flashrom on vendor firmware
Note on TPM:
The vendor sets Intel PTT to default-on in newer CSME images, which
conflicts with the dTPM. Currently, there are two ways to make it work:
1) Boot vendor firmware once to let it disable PTT via CSME firmware
feature override.
2) Use Intel Flash Image Tool (FIT) to set "initial power-up state" to
disabled.
Boots fine:
- Debian testing, unstable (Linux 5.16.14, 5.17.0-rc6)
- Windows 10 21H2 (Build 19044.1586)
Untested:
- Thunderbolt (see above)
- Type-C DisplayPort
- S-ATA
- 3G/LTE
- 3G/LTE depends on mising EC driver
- tested board is non-LTE version with a second NVME port instead
- LTE version has a USB-only M.2 slot (supported by this port)
Doesn't work:
- TPM interrupt on Linux [1]
- WLAN/BT (PCIe) - gets detected but can't be enabled
- All EC related functions - EC driver is WIP
- Fn-Keys
- S0ix
- UCSI
- Fan control
- Battery info
[1] https://lkml.org/lkml/2021/5/1/103
Change-Id: I4c4bef3827da10241e9b01e12ecc4276e131a620
Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de>
---
M src/mainboard/clevo/cml-u/Kconfig
A src/mainboard/clevo/tgl-u/Kconfig
A src/mainboard/clevo/tgl-u/Kconfig.name
A src/mainboard/clevo/tgl-u/Makefile.inc
A src/mainboard/clevo/tgl-u/board_info.txt
A src/mainboard/clevo/tgl-u/bootblock.c
A src/mainboard/clevo/tgl-u/cmos.default
A src/mainboard/clevo/tgl-u/cmos.layout
A src/mainboard/clevo/tgl-u/dsdt.asl
A src/mainboard/clevo/tgl-u/include/variant/gpio.h
A src/mainboard/clevo/tgl-u/include/variant/ramstage.h
A src/mainboard/clevo/tgl-u/include/variant/romstage.h
A src/mainboard/clevo/tgl-u/ramstage.c
A src/mainboard/clevo/tgl-u/romstage.c
A src/mainboard/clevo/tgl-u/spd/samsung-M471A1G44AB0-CWE.spd.hex
A src/mainboard/clevo/tgl-u/variants/l140mu/Makefile.inc
A src/mainboard/clevo/tgl-u/variants/l140mu/board_info.txt
A src/mainboard/clevo/tgl-u/variants/l140mu/data.vbt
A src/mainboard/clevo/tgl-u/variants/l140mu/devicetree.cb
A src/mainboard/clevo/tgl-u/variants/l140mu/gpio.c
A src/mainboard/clevo/tgl-u/variants/l140mu/gpio_early.c
A src/mainboard/clevo/tgl-u/variants/l140mu/hda_verb.c
A src/mainboard/clevo/tgl-u/variants/l140mu/ramstage.c
A src/mainboard/clevo/tgl-u/variants/l140mu/romstage.c
24 files changed, 901 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/59548/13
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Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59548 )
Change subject: mb: add new board clevo/tgl-u/l140mu
......................................................................
Patch Set 12:
(6 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/59548/comment/332edfef_13e8fa0d
PS12, Line 7: mb: add new board clevo/tgl-u/l140mu
Why not our usual scheme? Suggestion:
mb/clevo/tgl-u/l140mu: Add new mainboard
File src/mainboard/clevo/tgl-u/Kconfig:
https://review.coreboot.org/c/coreboot/+/59548/comment/8a10c6fa_4de668bf
PS12, Line 48: config VGA_BIOS_ID
: default "8086,9b41"
This is only needed when an option rom is used. It's not the case here, so remove it.
https://review.coreboot.org/c/coreboot/+/59548/comment/b897a4f8_7108780f
PS12, Line 51: config TPM_PIRQ
: default 0x77 if BOARD_CLEVO_L140MU # GPP_C9_IRQ
I would move this to the other options on the top, so that the variant specific options are not scattered over the file too much.
https://review.coreboot.org/c/coreboot/+/59548/comment/343d819a_441effec
PS12, Line 57: config VARIANT_DIR
: default "l140mu" if BOARD_CLEVO_L140MU
Same here.
File src/mainboard/clevo/tgl-u/Kconfig.name:
https://review.coreboot.org/c/coreboot/+/59548/comment/68d0cd1e_00000fc0
PS12, Line 4: bool "L140MU / L141MU / L142MU"
What are the differences between these variants?
File src/mainboard/clevo/tgl-u/variants/l140mu/gpio_early.c:
https://review.coreboot.org/c/coreboot/+/59548/comment/8221229e_debc82e6
PS12, Line 10: PAD_NC(GPP_C22, UP_20K),
: PA
Not needed here. Please remove.
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Change subject: mb/google/brya: Set pciexp_hotplug_dummy_ops.set_resources as no-op
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63101/comment/2e170313_3232d0c2
PS1, Line 7: mb/google/brya
> this isn't a change in mb/gogle/brya, but in device/pciexp_device, so the prefix should be device/pc […]
Oops good catch 😄
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Change subject: Documentation: gpio: Update table as per coreboot guidelines
......................................................................
Patch Set 1:
(2 comments)
File Documentation/getting_started/gpio.md:
https://review.coreboot.org/c/coreboot/+/63126/comment/6696cd39_d12ecfc6
PS1, Line 177: (GPP: RSMRST,
this won't work - just tested this locally. You have to prefix the lines to make the cell become a multiline cell:
```
+------------------------+----------------+-------------+-------------+
| | 00 - Power Good | Warm Reset | N | N |
| | (GPP: RSMRST, +----------------+-------------+-------------+
| | GPD: DSW_PWROK) | Cold Reset | N | N |
+------------------------+----------------+-------------+-------------+
```
https://review.coreboot.org/c/coreboot/+/63126/comment/79805243_7d9bf281
PS1, Line 212: 11 - Resume Reset | Warm Reset | - | N |
: | (GPP: Reserved, +----------------+-------------+-------------+
: | GPD:
prefix | needed as above
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Change subject: Documentation: gpio: Update table as per coreboot guidelines
......................................................................
Patch Set 1:
(1 comment)
File Documentation/getting_started/gpio.md:
https://review.coreboot.org/c/coreboot/+/63126/comment/d0a88c24_0e2a1a30
PS1, Line 175: +------------------------+----------------+-------------+-------------+
=====, since it's a header
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vaibhav has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62968 )
Change subject: src/acpi/acpigen_usb.c: Fix Memory leak error
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Patch Set 1:
(1 comment)
File src/acpi/acpigen_usb.c:
https://review.coreboot.org/c/coreboot/+/62968/comment/a3048c49_fe519877
PS1, Line 89: free(fresh);
> Yes, please abandon. Maybe you find a way how to make scan-build ignore this error.
Done
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Gerrit-Project: coreboot
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Gerrit-Change-Id: Ifed611bd0b9c1da3678386bff33bca3eac0311b4
Gerrit-Change-Number: 62968
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Gerrit-Owner: vaibhav <vrockz747(a)gmail.com>
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Gerrit-Comment-Date: Sun, 27 Mar 2022 16:53:36 +0000
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