Attention is currently required from: Hung-Te Lin, Rex-BC Chen, Yu-Ping Wu.
Hello Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/61729
to look at the new patch set (#3).
Change subject: soc/mediatek: Only update required bits when triggering WDT reset
......................................................................
soc/mediatek: Only update required bits when triggering WDT reset
To prevent to modify original value of wdt_mode, we use setbits32 to
update required bits.
BUG=b:218420108
TEST=build pass
Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com>
Change-Id: I743c1af3583c18ec8500fc1eb89f31cdbce5317c
---
M src/soc/mediatek/common/wdt.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/61729/3
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Gerrit-Change-Number: 61729
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Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/blobs/+/61733 )
Change subject: soc/mediatek/mt8195: Update dram.elf from 1.7.1 to 1.8.1
......................................................................
Patch Set 2:
(4 comments)
Commit Message:
https://review.coreboot.org/c/blobs/+/61733/comment/d2021f67_b9cc2ef4
PS1, Line 7: soc/mediatek/mt8195: Update dram.elf to 1.8.1
> … from 1.7.1 to 1.8. […]
Done
https://review.coreboot.org/c/blobs/+/61733/comment/a037cec5_962702d6
PS1, Line 9: Move some structures to common folder (CB:61132).
> So this blob requires a certain coreboot version?
yes, this modification is corresponding to CB:61132.
File soc/mediatek/mt8195/dram_release_notes.txt:
https://review.coreboot.org/c/blobs/+/61733/comment/e5bdb5e3_7cee917a
PS1, Line 6: Include
> Included?
Done
https://review.coreboot.org/c/blobs/+/61733/comment/aa14964d_4d453bbf
PS1, Line 8: CL:*4389197: mtk-dramk/mt8186,8192,8195: Extract dramc_param_header to common header
> Add one more space in the beginning?
Done
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Attention is currently required from: Hung-Te Lin, Rex-BC Chen, Yu-Ping Wu.
Hello Hung-Te Lin, Yu-Ping Wu,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/blobs/+/61733
to look at the new patch set (#2).
Change subject: soc/mediatek/mt8195: Update dram.elf from 1.7.1 to 1.8.1
......................................................................
soc/mediatek/mt8195: Update dram.elf from 1.7.1 to 1.8.1
Move some structures to common folder (CB:61132).
BUG=b:218577927
TEST=dram calibration pass
Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com>
Change-Id: If0e48b914fa951b4fc07ff1f25c4b4837131508a
---
M soc/mediatek/mt8195/dram.elf
M soc/mediatek/mt8195/dram.elf.md5
M soc/mediatek/mt8195/dram_release_notes.txt
3 files changed, 10 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/blobs refs/changes/33/61733/2
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Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/blobs/+/61733 )
Change subject: soc/mediatek/mt8195: Update dram.elf to 1.8.1
......................................................................
Patch Set 1:
(4 comments)
Commit Message:
https://review.coreboot.org/c/blobs/+/61733/comment/bb83b3cc_8418ad9e
PS1, Line 7: soc/mediatek/mt8195: Update dram.elf to 1.8.1
… from 1.7.1 to 1.8.1
https://review.coreboot.org/c/blobs/+/61733/comment/45cabc53_7138953f
PS1, Line 9: Move some structures to common folder (CB:61132).
So this blob requires a certain coreboot version?
File soc/mediatek/mt8195/dram_release_notes.txt:
https://review.coreboot.org/c/blobs/+/61733/comment/967d57a7_05a68046
PS1, Line 6: Include
Included?
https://review.coreboot.org/c/blobs/+/61733/comment/f0a86f54_1febc6e9
PS1, Line 8: CL:*4389197: mtk-dramk/mt8186,8192,8195: Extract dramc_param_header to common header
Add one more space in the beginning?
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Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60405 )
Change subject: soc/intel/common/cse: Add `finalize` operation for CSE
......................................................................
Patch Set 25:
(1 comment)
File src/soc/intel/common/block/cse/cse.c:
https://review.coreboot.org/c/coreboot/+/60405/comment/78522f9b_b29118d3
PS24, Line 1195: static void cse_final(struct device *dev)
: {
: if (CONFIG(SKIP_FSP_NOTIFY_PHASE_READY_TO_BOOT)) {
: cse_send_end_of_post();
:
: cse_control_global_reset_lock();
:
: if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT)) {
: cse_set_to_d0i3();
: heci1_disable();
: }
: }
:
: if (CONFIG(SKIP_FSP_NOTIFY_PHASE_END_OF_FIRMWARE))
: heci_set_to_d0i3();
: }
> >Even thats the case with FSP-NotifyPhase API call as well today, Please check the log below: […]
hi Sridhar, I am not following your statement, but seems like you are not too familiar with FSP and coreboot design..
Or else you would have known that any new changes in FSP spec will only comes with next version, and then we can then design accordingly based on latest FSP spec, but the current implementation should be consistent across FSP2.0.
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