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Change subject: drivers/net/r8168: Add ASPM control mechanism
......................................................................
Patch Set 4:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/61267/comment/194baa11_764e4531
PS4, Line 12: enable ASPM L1.2.
What code is it exactly in the Linux kernel? I only found in `drivers/net/ethernet/realtek/r8169_main.c`:
```
/* Disable ASPM L1 as that cause random device stop working
* problems as well as full system hangs for some PCIe devices users.
* Chips from RTL8168h partially have issues with L1.2, but seem
* to work fine with L1 and L1.1.
*/
if (tp->mac_version >= RTL_GIGA_MAC_VER_45)
rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L1_2);
else
rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L1);
tp->aspm_manageable = !rc;
```
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Change subject: drivers/net/r8168: Add ASPM control mechanism
......................................................................
Patch Set 4:
(1 comment)
File src/drivers/net/chip.h:
https://review.coreboot.org/c/coreboot/+/61267/comment/ae2c6034_04506677
PS4, Line 36: bool enable_aspm;
Should the level be part of the variable name?
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Change subject: drivers/net/r8168: Add ASPM control mechanism
......................................................................
Patch Set 4:
(3 comments)
File src/drivers/net/r8168.c:
https://review.coreboot.org/c/coreboot/+/61267/comment/a13d9c75_c0bcf48d
PS4, Line 252: struct drivers_net_config *config = dev->chip_info;
: if (!config || !config->enable_aspm)
: return;
Seeing the function name, I’d move this outside the function before calling it.
https://review.coreboot.org/c/coreboot/+/61267/comment/b2244cd4_c57ce372
PS4, Line 256: printk(BIOS_INFO, "rtl: enable_aspm_L1.2\n");
Maybe:
rtl: Enable ASPM L1.2
https://review.coreboot.org/c/coreboot/+/61267/comment/d638b719_be5bfdaa
PS4, Line 363: /* Enable ASPM_L1.2 */
Comment not needed, as the function name says the same.
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Change subject: soc/mediatek/mt8195: Update dram.elf from 1.7.1 to 1.8.1
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/blobs/+/61733/comment/87b597c8_3be66270
PS1, Line 9: Move some structures to common folder (CB:61132).
> yes, this modification is corresponding to CB:61132.
Done
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Change subject: mb/google/brya/var/brask: Enable ASPM of RTL8125
......................................................................
Patch Set 4: Code-Review+1
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Change subject: soc/intel/common: Re-use Alder Lake-M device IDs for Alder Lake-N
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/61162/comment/9957911e_04839f98
PS3, Line 11: Hence rename those device IDs as ADL_M_N and use them for Alder Lake-N
No new paragraph needed.
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Change subject: mb/google/brya: Adjust CSE RO and Data partition in the CSE region
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/61728/comment/af63571c_e2e8ecaf
PS1, Line 14: stitch method and revert these changes of partition size.
Please remove the trailing space.
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Change subject: util/spd_tools/spd_gen/lp5: Encode Optional SDRAM features
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Patch Set 1:
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https://review.coreboot.org/c/coreboot/+/61730/comment/24c11d63_ee254fd9
PS1, Line 11: advisories.
Please reference the section in the datasheet with the name and revesion.
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Change subject: soc/mediatek: Only update required bits when triggering WDT reset
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Patch Set 3:
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https://review.coreboot.org/c/coreboot/+/61729/comment/47be06c3_6250c95d
PS2, Line 7: soc/mediatek: Update required bits when triggering WDT reset
> Maybe “Only update”, so it’s clear, these bits were updated also before this patch.
Done
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