Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: Update blobs submodule to upstream master
......................................................................
Update blobs submodule to upstream master
Updating from commit id b8e3eaf:
2021-07-15 08:09:11 +0000 - (mainboard/starlabs: Add files for Star Labs laptops)
to commit id 5dfc5da:
2022-01-24 16:48:56 +0800 - (soc/mediatek/mt8186: Add dram.elf version 0.1.0 for DRAM calibration)
This brings in 9 new commits:
5dfc5da soc/mediatek/mt8186: Add dram.elf version 0.1.0 for DRAM calibration
6355817 soc/mediatek/mt8186: List `sspm.bin` in README
54ca015 soc/mediatek/mt8186: Add SSPM firmware
27eb91b soc/mediatek/mt8186: Add SPM firmware
a2f02b4 soc/mediatek/mt8186: Add MT8186 basic files
f836ff3 soc/mediatek/mt8195: Update MCUPM firmware from v1.01.00 to v1.02.00
bb02df0 soc/mediatek/mt8195: Add dpm.pm and dpm.dm version 1.0
7f00baa soc/mediatek/mt8195: Add dram.elf for full calibration flow
19e1e69 soc/mediatek/mt8195: Update MCUPM firmware from v1.00.00 to v1.01.00
Signed-off-by: Martin Roth <gaumless(a)gmail.com>
Change-Id: Ieff9a5d9ba5ad9abcb9eb3e8117995235ffab1e9
---
M 3rdparty/blobs
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/60819/2
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Change subject: mb/google/brya/var/brask: Enable ASPM of RTL8125
......................................................................
Set Ready For Review
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Martin Roth - Personal has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/60826 )
Change subject: Update stm submodule to upstream master
......................................................................
Abandoned
Eugene says that this shouldn't be merged.
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Change subject: mb/google/brya/variants/brask: Enable Bluetooth offload support
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/61404/comment/ec987647_39775682
PS2, Line 13: t
> nit: remove this extra letter
Done
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Hello build bot (Jenkins), Tim Wawrzynczak, Zhuohao Lee,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/61404
to look at the new patch set (#3).
Change subject: mb/google/brya/variants/brask: Enable Bluetooth offload support
......................................................................
mb/google/brya/variants/brask: Enable Bluetooth offload support
Add fw_config NAU88L25B_I2S field, I2S2 configuration and
enabling CnviBtAudioOffload UPD bit.
BUG=none
TEST=emerge-brask coreboot
Signed-off-by: Mac Chiang <mac.chiang(a)intel.com>
Change-Id: Id5da8c5c471be176bc0fe1eda4da7faf8ed2e8d2
---
M src/mainboard/google/brya/variants/brask/Makefile.inc
A src/mainboard/google/brya/variants/brask/fw_config.c
M src/mainboard/google/brya/variants/brask/overridetree.cb
A src/mainboard/google/brya/variants/brask/variant.c
4 files changed, 64 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/61404/3
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Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60405 )
Change subject: soc/intel/common/cse: Add `finalize` operation for CSE
......................................................................
Patch Set 25:
(1 comment)
File src/soc/intel/common/block/cse/cse.c:
https://review.coreboot.org/c/coreboot/+/60405/comment/29563125_6435994c
PS24, Line 1195: static void cse_final(struct device *dev)
: {
: if (CONFIG(SKIP_FSP_NOTIFY_PHASE_READY_TO_BOOT)) {
: cse_send_end_of_post();
:
: cse_control_global_reset_lock();
:
: if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT)) {
: cse_set_to_d0i3();
: heci1_disable();
: }
: }
:
: if (CONFIG(SKIP_FSP_NOTIFY_PHASE_END_OF_FIRMWARE))
: heci_set_to_d0i3();
: }
> > CB_INTEL_SOC_RUN_OPS_BEFORE_PAYLOAD_LAUNCH?? seriously?! A Kconfig option that says coreboot runs […]
>Even thats the case with FSP-NotifyPhase API call as well today, Please check the log below:
NotifyPhaseApi() - Begin [Phase: 00000040]
FSP Ready To Boot ...
......
NotifyPhaseApi() - End [Status: 0x00000000]
PROGRESS CODE: V0000487F I0
PROGRESS CODE: V00002800 I0
NotifyPhaseApi() - Begin [Phase: 000000F0]
FSP End of Firmware ...
......
NotifyPhaseApi() - End [Status: 0x00000000]
Because coreboot chose to give call those FSP Notify APIs sequentially. But, the flow can be changed later with existing desing. But, can your new flow allows such flexibility?
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#2).
Change subject: Update arm-trusted-firmware submodule to upstream master
......................................................................
Update arm-trusted-firmware submodule to upstream master
Updating from commit id 73193689c:
2021-12-06 16:47:33 +0100 - (Merge changes I7c9f8490,Ia92c6d19 into integration)
to commit id e0a6a512b:
2022-02-03 22:59:34 +0100 - (Merge changes from topic "msm8916" into integration)
This brings in 324 new commits.
Signed-off-by: Martin Roth <gaumless(a)gmail.com>
Change-Id: I44bca36f4b05e08fe7d7de0966131be84c0a7d2b
---
M 3rdparty/arm-trusted-firmware
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/60818/2
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Change subject: mb/google/dedede/var/pirika: Add Wifi SAR for pasara
......................................................................
Patch Set 3:
(2 comments)
File src/mainboard/google/dedede/variants/pirika/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/61705/comment/de59815c_6bc7ebd0
PS1, Line 3: $(CONFIG_FW_CONFIG)
> ramstage-y since variant.c is not looking anything in FW_CONFIG.
Done
File src/mainboard/google/dedede/variants/pirika/variant.c:
https://review.coreboot.org/c/coreboot/+/61705/comment/ccf5adab_6fc455ce
PS1, Line 4: #include <fw_config.h>
> Is it required?
Done
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Change subject: spd/lp5: Generate initial SPDs for Sabrina SoC
......................................................................
Patch Set 3: Code-Review+2
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Change subject: drivers/net/r8168: Add ASPM control mechanism
......................................................................
Patch Set 4: Code-Review+2
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/61267/comment/11867212_2a9c72c3
PS1, Line 13:
> We're not sure if it's necessary for other devices, so we make it optional. […]
I think may also depend on board design.
File src/drivers/net/chip.h:
https://review.coreboot.org/c/coreboot/+/61267/comment/06568f9f_b08a44f1
PS2, Line 35: /* Allow kernel driver to enable ASPM L1.2. */
: bool enable_aspm;
> So coreboot already has a Kconfig option to enable ASPM on PCIe links (PCIEXP_ASPM, see https://revi […]
Done
File src/drivers/net/r8168.c:
https://review.coreboot.org/c/coreboot/+/61267/comment/587cf6b6_237f2ca1
PS3, Line 40: ASPM_L1_2 0xe059000f
> nit: […]
Ack
https://review.coreboot.org/c/coreboot/+/61267/comment/af4d600d_30e149eb
PS3, Line 359: /* Enable ASPM_L1.2 */
: if (CONFIG(PCIEXP_ASPM))
: enable_aspm_l1_2(io_base);
> I see, thank you for the explanation. […]
Done
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