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Change in coreboot[master]: soc/amd/common/acp: add acp_gen2
by Fred Reitberger (Code Review) 11 Feb '22

11 Feb '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held. Fred Reitberger has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61832 ) Change subject: soc/amd/common/acp: add acp_gen2 ...................................................................... soc/amd/common/acp: add acp_gen2 The gen2 ACP register definitions and locations are different from previous models. Specific code is refactored into acp_gen1 and acp_gen2. Update ACP register locations and definitions for gen2. Change-Id: If665b93cddf22435512f1276fcfee2f497dc6ef5 Signed-off-by: Fred Reitberger <reitbergerfred(a)gmail.com> --- M src/soc/amd/common/block/acp/Kconfig M src/soc/amd/common/block/acp/Makefile.inc M src/soc/amd/common/block/acp/acp.c A src/soc/amd/common/block/acp/acp_gen2.c M src/soc/amd/common/block/include/amdblocks/acp.h 5 files changed, 70 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/61832/1 diff --git a/src/soc/amd/common/block/acp/Kconfig b/src/soc/amd/common/block/acp/Kconfig index 7747c93..df17f71 100644 --- a/src/soc/amd/common/block/acp/Kconfig +++ b/src/soc/amd/common/block/acp/Kconfig @@ -3,3 +3,9 @@ help Select this option to perform Audio Co-Processor(ACP) configuration. Used by the ACP in AMD family 17h, 19h, and earlier (picasso, cezanne) + +config SOC_AMD_COMMON_BLOCK_ACP_GEN2 + bool + help + Select this option to perform Audio Co-Processor(ACP) configuration. + Used by the ACP in AMD sabrina (family 17h) and possibly newer CPUs. diff --git a/src/soc/amd/common/block/acp/Makefile.inc b/src/soc/amd/common/block/acp/Makefile.inc index 311fb75..c1fa6ec 100644 --- a/src/soc/amd/common/block/acp/Makefile.inc +++ b/src/soc/amd/common/block/acp/Makefile.inc @@ -1,2 +1,5 @@ ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACP_GEN1) += acp.c ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACP_GEN1) += acp_gen1.c + +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACP_GEN2) += acp.c +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACP_GEN2) += acp_gen2.c diff --git a/src/soc/amd/common/block/acp/acp.c b/src/soc/amd/common/block/acp/acp.c index 057d50a..63ceeaa 100644 --- a/src/soc/amd/common/block/acp/acp.c +++ b/src/soc/amd/common/block/acp/acp.c @@ -12,6 +12,8 @@ #include <commonlib/helpers.h> #include "acp_def.h" +_Static_assert(CONFIG(SOC_AMD_COMMON_BLOCK_ACP_GEN1) != CONFIG(SOC_AMD_COMMON_BLOCK_ACP_GEN2), + "Cannot select both ACP_GEN1 and ACP_GEN2 - check your config"); static const char *acp_acpi_name(const struct device *dev) { diff --git a/src/soc/amd/common/block/acp/acp_gen2.c b/src/soc/amd/common/block/acp/acp_gen2.c new file mode 100644 index 0000000..ff037b9 --- /dev/null +++ b/src/soc/amd/common/block/acp/acp_gen2.c @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <amdblocks/acp.h> +#include <amdblocks/chip.h> +#include <device/device.h> +#include <device/mmio.h> +#include <console/console.h> +#include "acp_def.h" + +/* ACP registers and associated fields */ +#define ACP_I2S_PIN_CONFIG 0x41440 /* HDA, Soundwire, I2S */ +#define PIN_CONFIG_MASK (0xf << 0) +#define ACP_I2S_WAKE_EN 0x4145C +#define WAKE_EN_MASK (1 << 0) +#define ACP_PME_EN 0x41400 +#define PME_EN_MASK (1 << 0) + +static void acp_update32(uintptr_t bar, uint32_t reg, uint32_t clear, uint32_t set) +{ + clrsetbits32((void *)(bar + reg), clear, set); +} + +void acp_init(struct device *dev) +{ + const struct soc_amd_common_config *cfg = soc_get_common_config(); + struct resource *res; + uintptr_t bar; + + res = dev->resource_list; + if (!res || !res->base) { + printk(BIOS_ERR, "Error, unable to configure pin in %s\n", __func__); + return; + } + + /* Set the proper I2S_PIN_CONFIG state */ + bar = (uintptr_t)res->base; + acp_update32(bar, ACP_I2S_PIN_CONFIG, PIN_CONFIG_MASK, cfg->acp_config.acp_pin_cfg); + + /* Enable ACP_PME_EN and ACP_I2S_WAKE_EN for I2S_WAKE event */ + acp_update32(bar, ACP_I2S_WAKE_EN, WAKE_EN_MASK, !!cfg->acp_config.acp_i2s_wake_enable); + acp_update32(bar, ACP_PME_EN, PME_EN_MASK, !!cfg->acp_config.acp_pme_enable); +} diff --git a/src/soc/amd/common/block/include/amdblocks/acp.h b/src/soc/amd/common/block/include/amdblocks/acp.h index 13254e4..f7e7ac8 100644 --- a/src/soc/amd/common/block/include/amdblocks/acp.h +++ b/src/soc/amd/common/block/include/amdblocks/acp.h @@ -7,12 +7,29 @@ struct acp_config { enum { +#if CONFIG(SOC_AMD_COMMON_BLOCK_ACP_GEN2) + ACP_PINS_HDA_3SDI = 1, /* HDA 3xSDI */ + ACP_PINS_HDA_1SDI_1SW = 2, /* HDA 1xSDI, SW w/Data0 */ + ACP_PINS_4SW_1SW = 3, /* SW w/Data0-3, SW w/Data0 */ + ACP_PINS_HDA_3SDI_PDM2 = 4, /* HDA 3xSDI, PDM 2CH */ + ACP_PINS_HDA_1SDI_PDM6 = 5, /* HDA 1xSDI, PDM 6CH */ + ACP_PINS_HDA_1SDI_1SW_PDM2 = 6, /* HDA 1xDI, SW w/Data0, PDM 2CH */ + ACP_PINS_4SW_PDM6 = 7, /* SW w/Data0-3, PDM 6CH */ + ACP_PINS_4SW_1SW_PDM2 = 8, /* SW w/Data0-3, SW w/Data0, PDM 2CH */ + ACP_PINS_I2S = 9, /* 3xI2S, Refclk, Intr */ + ACP_PINS_HDA_3SDI_PDM6_I2S = 10,/* HDA 3xSDI, PDM 6CH, I2S */ + ACP_PINS_HDA_3SDI_PDM8 = 11, /* HDA 3xSDI, PDM 8CH */ + ACP_PINS_HDA_1SDI_PDM6_I2S = 12,/* HDA 1xSDI, PDM 6CH, I2S */ + ACP_PINS_4SW_1SW_PDM6_I2S = 13, /* SW w/Data0-3, SW w/Data0, PDM 6CH, I2S */ + ACP_PINS_4SW_1SW_PDM8 = 14, /* SW w/Data0-3, SW w/Data0, PDM 8CH */ +#else I2S_PINS_MAX_HDA = 0, /* HDA w/reset 3xSDI, SW w/Data0 */ I2S_PINS_MAX_MHDA = 1, /* HDA no reset 3xSDI, SW w/Data0-1 */ I2S_PINS_MIN_HDA = 2, /* HDA w/reset 1xSDI, SW w/Data0-2 */ I2S_PINS_MIN_MHDA = 3, /* HDA no reset 1xSDI, SW w/Data0-3 */ I2S_PINS_I2S_TDM = 4, I2S_PINS_UNCONF = 7, /* All pads will be input mode */ +#endif } acp_pin_cfg; /* Enable ACP I2S wake feature (0 = disable, 1 = enable) */ -- To view, visit https://review.coreboot.org/c/coreboot/+/61832 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If665b93cddf22435512f1276fcfee2f497dc6ef5 Gerrit-Change-Number: 61832 Gerrit-PatchSet: 1 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/common/acp: introduce acp_gen1
by Fred Reitberger (Code Review) 11 Feb '22

11 Feb '22

Fred Reitberger has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61831 ) Change subject: soc/amd/common/acp: introduce acp_gen1 ...................................................................... soc/amd/common/acp: introduce acp_gen1 Refactor existing acp code into acp_gen1 variant as preparation for gen2 variant in sabrina. Change-Id: Id9248584237196b5404b79d3a8552cb90fe4491e Signed-off-by: Fred Reitberger <reitbergerfred(a)gmail.com> --- M src/soc/amd/cezanne/Kconfig M src/soc/amd/common/block/acp/Kconfig M src/soc/amd/common/block/acp/Makefile.inc M src/soc/amd/common/block/acp/acp.c A src/soc/amd/common/block/acp/acp_def.h A src/soc/amd/common/block/acp/acp_gen1.c M src/soc/amd/picasso/Kconfig M src/soc/amd/sabrina/Kconfig 8 files changed, 60 insertions(+), 41 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/61831/1 diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index f0b7c27..fa11868 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -37,7 +37,7 @@ select RESET_VECTOR_IN_RAM select RTC select SOC_AMD_COMMON - select SOC_AMD_COMMON_BLOCK_ACP + select SOC_AMD_COMMON_BLOCK_ACP_GEN1 select SOC_AMD_COMMON_BLOCK_ACPI select SOC_AMD_COMMON_BLOCK_ACPIMMIO select SOC_AMD_COMMON_BLOCK_ACPI_ALIB diff --git a/src/soc/amd/common/block/acp/Kconfig b/src/soc/amd/common/block/acp/Kconfig index ca733cd..7747c93 100644 --- a/src/soc/amd/common/block/acp/Kconfig +++ b/src/soc/amd/common/block/acp/Kconfig @@ -1,4 +1,5 @@ -config SOC_AMD_COMMON_BLOCK_ACP +config SOC_AMD_COMMON_BLOCK_ACP_GEN1 bool help Select this option to perform Audio Co-Processor(ACP) configuration. + Used by the ACP in AMD family 17h, 19h, and earlier (picasso, cezanne) diff --git a/src/soc/amd/common/block/acp/Makefile.inc b/src/soc/amd/common/block/acp/Makefile.inc index cdff5bd..311fb75 100644 --- a/src/soc/amd/common/block/acp/Makefile.inc +++ b/src/soc/amd/common/block/acp/Makefile.inc @@ -1 +1,2 @@ -ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACP) += acp.c +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACP_GEN1) += acp.c +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACP_GEN1) += acp_gen1.c diff --git a/src/soc/amd/common/block/acp/acp.c b/src/soc/amd/common/block/acp/acp.c index 465a44e..057d50a 100644 --- a/src/soc/amd/common/block/acp/acp.c +++ b/src/soc/amd/common/block/acp/acp.c @@ -5,47 +5,13 @@ #include <amdblocks/acp.h> #include <amdblocks/acpimmio.h> #include <amdblocks/chip.h> -#include <console/console.h> #include <device/device.h> -#include <device/mmio.h> #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> #include <commonlib/helpers.h> +#include "acp_def.h" -/* ACP registers and associated fields */ -#define ACP_I2S_PIN_CONFIG 0x1400 /* HDA, Soundwire, I2S */ -#define PIN_CONFIG_MASK (7 << 0) -#define ACP_I2S_WAKE_EN 0x1414 -#define WAKE_EN_MASK (1 << 0) -#define ACP_PME_EN 0x1418 -#define PME_EN_MASK (1 << 0) - -static void acp_update32(uintptr_t bar, uint32_t reg, uint32_t clear, uint32_t set) -{ - clrsetbits32((void *)(bar + reg), clear, set); -} - -static void init(struct device *dev) -{ - const struct soc_amd_common_config *cfg = soc_get_common_config(); - struct resource *res; - uintptr_t bar; - - res = dev->resource_list; - if (!res || !res->base) { - printk(BIOS_ERR, "Error, unable to configure pin in %s\n", __func__); - return; - } - - /* Set the proper I2S_PIN_CONFIG state */ - bar = (uintptr_t)res->base; - acp_update32(bar, ACP_I2S_PIN_CONFIG, PIN_CONFIG_MASK, cfg->acp_config.acp_pin_cfg); - - /* Enable ACP_PME_EN and ACP_I2S_WAKE_EN for I2S_WAKE event */ - acp_update32(bar, ACP_I2S_WAKE_EN, WAKE_EN_MASK, !!cfg->acp_config.acp_i2s_wake_enable); - acp_update32(bar, ACP_PME_EN, PME_EN_MASK, !!cfg->acp_config.acp_pme_enable); -} static const char *acp_acpi_name(const struct device *dev) { @@ -78,7 +44,7 @@ .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = init, + .init = acp_init, .ops_pci = &pci_dev_ops_pci, .scan_bus = scan_static_bus, .acpi_name = acp_acpi_name, diff --git a/src/soc/amd/common/block/acp/acp_def.h b/src/soc/amd/common/block/acp/acp_def.h new file mode 100644 index 0000000..55af01a --- /dev/null +++ b/src/soc/amd/common/block/acp/acp_def.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __AMD_ACP_DEF_H__ +#define __AMD_ACP_DEF_H__ + +/* This command needs to be implemented by the generation specific code. */ +void acp_init(struct device *dev); + +#endif /* __AMD_ACP_DEF_H__ */ diff --git a/src/soc/amd/common/block/acp/acp_gen1.c b/src/soc/amd/common/block/acp/acp_gen1.c new file mode 100644 index 0000000..0fe37f3 --- /dev/null +++ b/src/soc/amd/common/block/acp/acp_gen1.c @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <amdblocks/acp.h> +#include <amdblocks/chip.h> +#include <device/device.h> +#include <device/mmio.h> +#include <console/console.h> +#include "acp_def.h" + +/* ACP registers and associated fields */ +#define ACP_I2S_PIN_CONFIG 0x1400 /* HDA, Soundwire, I2S */ +#define PIN_CONFIG_MASK (7 << 0) +#define ACP_I2S_WAKE_EN 0x1414 +#define WAKE_EN_MASK (1 << 0) +#define ACP_PME_EN 0x1418 +#define PME_EN_MASK (1 << 0) + +static void acp_update32(uintptr_t bar, uint32_t reg, uint32_t clear, uint32_t set) +{ + clrsetbits32((void *)(bar + reg), clear, set); +} + +void acp_init(struct device *dev) +{ + const struct soc_amd_common_config *cfg = soc_get_common_config(); + struct resource *res; + uintptr_t bar; + + res = dev->resource_list; + if (!res || !res->base) { + printk(BIOS_ERR, "Error, unable to configure pin in %s\n", __func__); + return; + } + + /* Set the proper I2S_PIN_CONFIG state */ + bar = (uintptr_t)res->base; + acp_update32(bar, ACP_I2S_PIN_CONFIG, PIN_CONFIG_MASK, cfg->acp_config.acp_pin_cfg); + + /* Enable ACP_PME_EN and ACP_I2S_WAKE_EN for I2S_WAKE event */ + acp_update32(bar, ACP_I2S_WAKE_EN, WAKE_EN_MASK, !!cfg->acp_config.acp_i2s_wake_enable); + acp_update32(bar, ACP_PME_EN, PME_EN_MASK, !!cfg->acp_config.acp_pme_enable); +} diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index ebcbd62..e41dbaa 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -27,7 +27,7 @@ select HAVE_ACPI_TABLES select HAVE_EM100_SUPPORT select SOC_AMD_COMMON - select SOC_AMD_COMMON_BLOCK_ACP + select SOC_AMD_COMMON_BLOCK_ACP_GEN1 select SOC_AMD_COMMON_BLOCK_ACPI select SOC_AMD_COMMON_BLOCK_ACPIMMIO select SOC_AMD_COMMON_BLOCK_ACPI_ALIB diff --git a/src/soc/amd/sabrina/Kconfig b/src/soc/amd/sabrina/Kconfig index 43c96c0..86d97d5 100644 --- a/src/soc/amd/sabrina/Kconfig +++ b/src/soc/amd/sabrina/Kconfig @@ -39,7 +39,7 @@ select RESET_VECTOR_IN_RAM select RTC select SOC_AMD_COMMON - select SOC_AMD_COMMON_BLOCK_ACP # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_ACP_GEN1 # TODO: Check if this is still correct - change to GEN2 select SOC_AMD_COMMON_BLOCK_ACPI # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_ACPIMMIO select SOC_AMD_COMMON_BLOCK_ACPI_ALIB # TODO: Check if this is still correct -- To view, visit https://review.coreboot.org/c/coreboot/+/61831 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9248584237196b5404b79d3a8552cb90fe4491e Gerrit-Change-Number: 61831 Gerrit-PatchSet: 1 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/var/{taeko, taeko4es}: Use ACPI _PLD macro
by Subrata Banik (Code Review) 11 Feb '22

11 Feb '22

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61830 ) Change subject: mb/google/var/{taeko, taeko4es}: Use ACPI _PLD macro ...................................................................... mb/google/var/{taeko, taeko4es}: Use ACPI _PLD macro This patch uses ACPI _PLD macros for USB Type A and C ports. BUG=b:216490477 TEST=emerge-brya coreboot Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Ie304b08b0b1bbad5547a0169ea8056d703141391 --- M src/mainboard/google/brya/variants/taeko/overridetree.cb M src/mainboard/google/brya/variants/taeko4es/overridetree.cb 2 files changed, 12 insertions(+), 72 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/61830/1 diff --git a/src/mainboard/google/brya/variants/taeko/overridetree.cb b/src/mainboard/google/brya/variants/taeko/overridetree.cb index b70b05e..15b0665 100644 --- a/src/mainboard/google/brya/variants/taeko/overridetree.cb +++ b/src/mainboard/google/brya/variants/taeko/overridetree.cb @@ -459,24 +459,14 @@ register "desc" = ""USB3 Type-C Port C0 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "{ - .visible = true, - .panel = PLD_PANEL_LEFT, - .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT, - .shape = PLD_SHAPE_OVAL, - .group = ACPI_PLD_GROUP(1, 1)}" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" device ref tcss_usb3_port1 on end end chip drivers/usb/acpi register "desc" = ""USB3 Type-C Port C1 (DB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "{ - .visible = true, - .panel = PLD_PANEL_RIGHT, - .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT, - .shape = PLD_SHAPE_OVAL, - .group = ACPI_PLD_GROUP(2, 1)}" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))" device ref tcss_usb3_port3 on probe DB_USB DB_USB3_NO_A probe DB_USB DB_USB3_1C_1A @@ -492,24 +482,14 @@ register "desc" = ""USB2 Type-C Port C0 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "{ - .visible = true, - .panel = PLD_PANEL_LEFT, - .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT, - .shape = PLD_SHAPE_OVAL, - .group = ACPI_PLD_GROUP(1, 1)}" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" device ref usb2_port1 on end end chip drivers/usb/acpi register "desc" = ""USB2 Type-C Port C1 (DB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "{ - .visible = true, - .panel = PLD_PANEL_RIGHT, - .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT, - .shape = PLD_SHAPE_OVAL, - .group = ACPI_PLD_GROUP(2, 1)}" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))" device ref usb2_port3 on probe DB_USB DB_USB3_NO_A probe DB_USB DB_USB3_1C_1A @@ -533,12 +513,7 @@ register "desc" = ""USB2 Type-A Port (MLB)"" register "type" = "UPC_TYPE_A" register "use_custom_pld" = "true" - register "custom_pld" = "{ - .visible = true, - .panel = PLD_PANEL_LEFT, - .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT, - .shape = PLD_SHAPE_HORIZONTAL_RECTANGLE, - .group = ACPI_PLD_GROUP(4, 1)}" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, LEFT, ACPI_PLD_GROUP(4, 1))" device ref usb2_port9 on end end chip drivers/usb/acpi @@ -552,12 +527,7 @@ register "desc" = ""USB3 Type-A Port (MLB)"" register "type" = "UPC_TYPE_USB3_A" register "use_custom_pld" = "true" - register "custom_pld" = "{ - .visible = true, - .panel = PLD_PANEL_LEFT, - .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT, - .shape = PLD_SHAPE_HORIZONTAL_RECTANGLE, - .group = ACPI_PLD_GROUP(4, 1)}" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, LEFT, ACPI_PLD_GROUP(4, 1))" device ref usb3_port1 on end end chip drivers/usb/acpi diff --git a/src/mainboard/google/brya/variants/taeko4es/overridetree.cb b/src/mainboard/google/brya/variants/taeko4es/overridetree.cb index 569f223..f358c14 100644 --- a/src/mainboard/google/brya/variants/taeko4es/overridetree.cb +++ b/src/mainboard/google/brya/variants/taeko4es/overridetree.cb @@ -441,24 +441,14 @@ register "desc" = ""USB3 Type-C Port C0 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "{ - .visible = true, - .panel = PLD_PANEL_LEFT, - .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT, - .shape = PLD_SHAPE_OVAL, - .group = ACPI_PLD_GROUP(1, 1)}" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" device ref tcss_usb3_port1 on end end chip drivers/usb/acpi register "desc" = ""USB3 Type-C Port C1 (DB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "{ - .visible = true, - .panel = PLD_PANEL_RIGHT, - .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT, - .shape = PLD_SHAPE_OVAL, - .group = ACPI_PLD_GROUP(2, 1)}" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))" device ref tcss_usb3_port3 on probe DB_USB DB_USB3_NO_A end @@ -473,24 +463,14 @@ register "desc" = ""USB2 Type-C Port C0 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "{ - .visible = true, - .panel = PLD_PANEL_LEFT, - .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT, - .shape = PLD_SHAPE_OVAL, - .group = ACPI_PLD_GROUP(1, 1)}" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" device ref usb2_port1 on end end chip drivers/usb/acpi register "desc" = ""USB2 Type-C Port C1 (DB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "{ - .visible = true, - .panel = PLD_PANEL_RIGHT, - .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT, - .shape = PLD_SHAPE_OVAL, - .group = ACPI_PLD_GROUP(2, 1)}" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))" device ref usb2_port3 on probe DB_USB DB_USB3_NO_A end @@ -505,12 +485,7 @@ register "desc" = ""USB2 Type-A Port (MLB)"" register "type" = "UPC_TYPE_A" register "use_custom_pld" = "true" - register "custom_pld" = "{ - .visible = true, - .panel = PLD_PANEL_LEFT, - .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT, - .shape = PLD_SHAPE_HORIZONTAL_RECTANGLE, - .group = ACPI_PLD_GROUP(4, 1)}" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, LEFT, ACPI_PLD_GROUP(4, 1))" device ref usb2_port9 on end end chip drivers/usb/acpi @@ -524,12 +499,7 @@ register "desc" = ""USB3 Type-A Port (MLB)"" register "type" = "UPC_TYPE_USB3_A" register "use_custom_pld" = "true" - register "custom_pld" = "{ - .visible = true, - .panel = PLD_PANEL_LEFT, - .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT, - .shape = PLD_SHAPE_HORIZONTAL_RECTANGLE, - .group = ACPI_PLD_GROUP(4, 1)}" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, LEFT, ACPI_PLD_GROUP(4, 1))" device ref usb3_port1 on end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/61830 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie304b08b0b1bbad5547a0169ea8056d703141391 Gerrit-Change-Number: 61830 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/var/{redrix, redrix4es}: Use ACPI _PLD macro
by Subrata Banik (Code Review) 11 Feb '22

11 Feb '22

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61829 ) Change subject: mb/google/var/{redrix, redrix4es}: Use ACPI _PLD macro ...................................................................... mb/google/var/{redrix, redrix4es}: Use ACPI _PLD macro This patch uses ACPI _PLD macros for USB Type A and C ports. BUG=b:216490477 TEST=emerge-brya coreboot Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I61f8f39ce7651d499756f4975840f32f89b04ca7 --- M src/mainboard/google/brya/variants/redrix/overridetree.cb M src/mainboard/google/brya/variants/redrix4es/overridetree.cb 2 files changed, 12 insertions(+), 72 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/61829/1 diff --git a/src/mainboard/google/brya/variants/redrix/overridetree.cb b/src/mainboard/google/brya/variants/redrix/overridetree.cb index b29e42e..8c8254f 100644 --- a/src/mainboard/google/brya/variants/redrix/overridetree.cb +++ b/src/mainboard/google/brya/variants/redrix/overridetree.cb @@ -474,24 +474,14 @@ register "desc" = ""USB3 Type-C Port C0 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "{ - .visible = true, - .panel = PLD_PANEL_LEFT, - .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT, - .shape = PLD_SHAPE_OVAL, - .group = ACPI_PLD_GROUP(1, 1)}" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" device ref tcss_usb3_port1 on end end chip drivers/usb/acpi register "desc" = ""USB3 Type-C Port C2 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "{ - .visible = true, - .panel = PLD_PANEL_RIGHT, - .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT, - .shape = PLD_SHAPE_OVAL, - .group = ACPI_PLD_GROUP(3, 1)}" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(3, 1))" device ref tcss_usb3_port3 on end end end @@ -504,24 +494,14 @@ register "desc" = ""USB2 Type-C Port C0 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "{ - .visible = true, - .panel = PLD_PANEL_LEFT, - .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT, - .shape = PLD_SHAPE_OVAL, - .group = ACPI_PLD_GROUP(1, 1)}" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" device ref usb2_port1 on end end chip drivers/usb/acpi register "desc" = ""USB2 Type-C Port C2 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "{ - .visible = true, - .panel = PLD_PANEL_RIGHT, - .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT, - .shape = PLD_SHAPE_OVAL, - .group = ACPI_PLD_GROUP(3, 1)}" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(3, 1))" device ref usb2_port3 on end end chip drivers/usb/acpi @@ -538,12 +518,7 @@ register "desc" = ""USB2 Type-A Port (MLB)"" register "type" = "UPC_TYPE_A" register "use_custom_pld" = "true" - register "custom_pld" = "{ - .visible = true, - .panel = PLD_PANEL_RIGHT, - .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT, - .shape = PLD_SHAPE_HORIZONTAL_RECTANGLE, - .group = ACPI_PLD_GROUP(4, 1)}" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))" device ref usb2_port9 on end end chip drivers/usb/acpi @@ -557,12 +532,7 @@ register "desc" = ""USB3 Type-A Port (MLB)"" register "type" = "UPC_TYPE_USB3_A" register "use_custom_pld" = "true" - register "custom_pld" = "{ - .visible = true, - .panel = PLD_PANEL_RIGHT, - .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT, - .shape = PLD_SHAPE_HORIZONTAL_RECTANGLE, - .group = ACPI_PLD_GROUP(4, 1)}" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))" device ref usb3_port1 on end end chip drivers/usb/acpi diff --git a/src/mainboard/google/brya/variants/redrix4es/overridetree.cb b/src/mainboard/google/brya/variants/redrix4es/overridetree.cb index 40cc0cd..1bfac5f 100644 --- a/src/mainboard/google/brya/variants/redrix4es/overridetree.cb +++ b/src/mainboard/google/brya/variants/redrix4es/overridetree.cb @@ -460,24 +460,14 @@ register "desc" = ""USB3 Type-C Port C0 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "{ - .visible = true, - .panel = PLD_PANEL_LEFT, - .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT, - .shape = PLD_SHAPE_OVAL, - .group = ACPI_PLD_GROUP(1, 1)}" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" device ref tcss_usb3_port1 on end end chip drivers/usb/acpi register "desc" = ""USB3 Type-C Port C2 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "{ - .visible = true, - .panel = PLD_PANEL_RIGHT, - .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT, - .shape = PLD_SHAPE_OVAL, - .group = ACPI_PLD_GROUP(3, 1)}" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(3, 1))" device ref tcss_usb3_port3 on end end end @@ -490,24 +480,14 @@ register "desc" = ""USB2 Type-C Port C0 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "{ - .visible = true, - .panel = PLD_PANEL_LEFT, - .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT, - .shape = PLD_SHAPE_OVAL, - .group = ACPI_PLD_GROUP(1, 1)}" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" device ref usb2_port1 on end end chip drivers/usb/acpi register "desc" = ""USB2 Type-C Port C2 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "{ - .visible = true, - .panel = PLD_PANEL_RIGHT, - .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT, - .shape = PLD_SHAPE_OVAL, - .group = ACPI_PLD_GROUP(3, 1)}" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(3, 1))" device ref usb2_port3 on end end chip drivers/usb/acpi @@ -524,12 +504,7 @@ register "desc" = ""USB2 Type-A Port (MLB)"" register "type" = "UPC_TYPE_A" register "use_custom_pld" = "true" - register "custom_pld" = "{ - .visible = true, - .panel = PLD_PANEL_RIGHT, - .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT, - .shape = PLD_SHAPE_HORIZONTAL_RECTANGLE, - .group = ACPI_PLD_GROUP(4, 1)}" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))" device ref usb2_port9 on end end chip drivers/usb/acpi @@ -543,12 +518,7 @@ register "desc" = ""USB3 Type-A Port (MLB)"" register "type" = "UPC_TYPE_USB3_A" register "use_custom_pld" = "true" - register "custom_pld" = "{ - .visible = true, - .panel = PLD_PANEL_RIGHT, - .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT, - .shape = PLD_SHAPE_HORIZONTAL_RECTANGLE, - .group = ACPI_PLD_GROUP(4, 1)}" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))" device ref usb3_port1 on end end chip drivers/usb/acpi -- To view, visit https://review.coreboot.org/c/coreboot/+/61829 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I61f8f39ce7651d499756f4975840f32f89b04ca7 Gerrit-Change-Number: 61829 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/sabrina: Move EFS into FMAP section
by Raul Rangel (Code Review) 11 Feb '22

11 Feb '22

Attention is currently required from: Jason Glenesk, Marshall Dawson, Paul Menzel, Fred Reitberger. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61559 ) Change subject: soc/amd/sabrina: Move EFS into FMAP section ...................................................................... Patch Set 4: (1 comment) File src/mainboard/amd/chausie/board.fmd: https://review.coreboot.org/c/coreboot/+/61559/comment/8ec95866_434216cb PS1, Line 4: 3M > if i understood things correctly, there is a requirement to use the first possible efs location on s […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/61559 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifa9333f4097705a5c572756ac3ead3ae7a0b22a4 Gerrit-Change-Number: 61559 Gerrit-PatchSet: 4 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Thu, 10 Feb 2022 15:46:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Fred Reitberger <reitbergerfred(a)gmail.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede/var/vell: Add Wifi SAR for vell
by Tim Wawrzynczak (Code Review) 11 Feb '22

11 Feb '22

Attention is currently required from: Robert Chen. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61780 ) Change subject: mb/google/dedede/var/vell: Add Wifi SAR for vell ...................................................................... Patch Set 1: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/61780/comment/75e77164_52d03210 PS1, Line 7: dedede `brya` 😊 File src/mainboard/google/brya/variants/vell/variant.c: https://review.coreboot.org/c/coreboot/+/61780/comment/331a4a78_d7f170e6 PS1, Line 7: wifi_sar-vell.hex If you are using the SAR table generator in `config.star`, then your SAR filename is probably `wifi_sar_0.hex` -- To view, visit https://review.coreboot.org/c/coreboot/+/61780 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9797069d9d050bdae9e819c72c80179fa468a6f7 Gerrit-Change-Number: 61780 Gerrit-PatchSet: 1 Gerrit-Owner: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Thu, 10 Feb 2022 15:45:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/var/{primus, primus4es}: Use ACPI _PLD macro
by Subrata Banik (Code Review) 11 Feb '22

11 Feb '22

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61828 ) Change subject: mb/google/var/{primus, primus4es}: Use ACPI _PLD macro ...................................................................... mb/google/var/{primus, primus4es}: Use ACPI _PLD macro This patch uses ACPI _PLD macros for USB Type A and C ports. BUG=b:216490477 TEST=emerge-brya coreboot Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I1a4bc1aae8e815b882a607432e40caf1066453b2 --- M src/mainboard/google/brya/variants/primus/overridetree.cb M src/mainboard/google/brya/variants/primus4es/overridetree.cb 2 files changed, 16 insertions(+), 96 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/61828/1 diff --git a/src/mainboard/google/brya/variants/primus/overridetree.cb b/src/mainboard/google/brya/variants/primus/overridetree.cb index 6d4522b..f3690ad 100644 --- a/src/mainboard/google/brya/variants/primus/overridetree.cb +++ b/src/mainboard/google/brya/variants/primus/overridetree.cb @@ -319,24 +319,14 @@ register "desc" = ""USB3 Type-C Port C0 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "{ - .visible = true, - .panel = PLD_PANEL_LEFT, - .horizontal_position = PLD_HORIZONTAL_POSITION_CENTER, - .shape = PLD_SHAPE_OVAL, - .group = ACPI_PLD_GROUP(1, 1)}" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, CENTER, ACPI_PLD_GROUP(1, 1))" device ref tcss_usb3_port1 on end end chip drivers/usb/acpi register "desc" = ""USB3 Type-C Port C2 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "{ - .visible = true, - .panel = PLD_PANEL_LEFT, - .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT, - .shape = PLD_SHAPE_OVAL, - .group = ACPI_PLD_GROUP(2, 1)}" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))" device ref tcss_usb3_port3 on end end end @@ -349,24 +339,14 @@ register "desc" = ""USB2 Type-C Port C0 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "{ - .visible = true, - .panel = PLD_PANEL_LEFT, - .horizontal_position = PLD_HORIZONTAL_POSITION_CENTER, - .shape = PLD_SHAPE_OVAL, - .group = ACPI_PLD_GROUP(1, 1)}" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, CENTER, ACPI_PLD_GROUP(1, 1))" device ref usb2_port1 on end end chip drivers/usb/acpi register "desc" = ""USB2 Type-C Port C2 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "{ - .visible = true, - .panel = PLD_PANEL_LEFT, - .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT, - .shape = PLD_SHAPE_OVAL, - .group = ACPI_PLD_GROUP(2, 1)}" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))" device ref usb2_port3 on end end chip drivers/usb/acpi @@ -383,24 +363,14 @@ register "desc" = ""USB2 Type-A Port (MLB)"" register "type" = "UPC_TYPE_A" register "use_custom_pld" = "true" - register "custom_pld" = "{ - .visible = true, - .panel = PLD_PANEL_LEFT, - .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT, - .shape = PLD_SHAPE_HORIZONTAL_RECTANGLE, - .group = ACPI_PLD_GROUP(4, 1)}" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, LEFT, ACPI_PLD_GROUP(4, 1))" device ref usb2_port8 on end end chip drivers/usb/acpi register "desc" = ""USB2 Type-A Port A0 (DB)"" register "type" = "UPC_TYPE_A" register "use_custom_pld" = "true" - register "custom_pld" = "{ - .visible = true, - .panel = PLD_PANEL_RIGHT, - .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT, - .shape = PLD_SHAPE_HORIZONTAL_RECTANGLE, - .group = ACPI_PLD_GROUP(1, 2)}" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(1, 2))" device ref usb2_port9 on end end chip drivers/usb/acpi @@ -414,24 +384,14 @@ register "desc" = ""USB3 Type-A Port A0 (DB)"" register "type" = "UPC_TYPE_USB3_A" register "use_custom_pld" = "true" - register "custom_pld" = "{ - .visible = true, - .panel = PLD_PANEL_RIGHT, - .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT, - .shape = PLD_SHAPE_HORIZONTAL_RECTANGLE, - .group = ACPI_PLD_GROUP(1, 2)}" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(1, 2))" device ref usb3_port1 on end end chip drivers/usb/acpi register "desc" = ""USB3 Type-A Port (MLB)"" register "type" = "UPC_TYPE_USB3_A" register "use_custom_pld" = "true" - register "custom_pld" = "{ - .visible = true, - .panel = PLD_PANEL_LEFT, - .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT, - .shape = PLD_SHAPE_HORIZONTAL_RECTANGLE, - .group = ACPI_PLD_GROUP(4, 1)}" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, LEFT, ACPI_PLD_GROUP(4, 1))" device ref usb3_port2 on end end chip drivers/usb/acpi diff --git a/src/mainboard/google/brya/variants/primus4es/overridetree.cb b/src/mainboard/google/brya/variants/primus4es/overridetree.cb index d4f7237..cb3aeeb 100644 --- a/src/mainboard/google/brya/variants/primus4es/overridetree.cb +++ b/src/mainboard/google/brya/variants/primus4es/overridetree.cb @@ -313,24 +313,14 @@ register "desc" = ""USB3 Type-C Port C0 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "{ - .visible = true, - .panel = PLD_PANEL_LEFT, - .horizontal_position = PLD_HORIZONTAL_POSITION_CENTER, - .shape = PLD_SHAPE_OVAL, - .group = ACPI_PLD_GROUP(1, 1)}" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, CENTER, ACPI_PLD_GROUP(1, 1))" device ref tcss_usb3_port1 on end end chip drivers/usb/acpi register "desc" = ""USB3 Type-C Port C2 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "{ - .visible = true, - .panel = PLD_PANEL_LEFT, - .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT, - .shape = PLD_SHAPE_OVAL, - .group = ACPI_PLD_GROUP(2, 1)}" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))" device ref tcss_usb3_port3 on end end end @@ -343,24 +333,14 @@ register "desc" = ""USB2 Type-C Port C0 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "{ - .visible = true, - .panel = PLD_PANEL_LEFT, - .horizontal_position = PLD_HORIZONTAL_POSITION_CENTER, - .shape = PLD_SHAPE_OVAL, - .group = ACPI_PLD_GROUP(1, 1)}" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, CENTER, ACPI_PLD_GROUP(1, 1))" device ref usb2_port1 on end end chip drivers/usb/acpi register "desc" = ""USB2 Type-C Port C2 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "{ - .visible = true, - .panel = PLD_PANEL_LEFT, - .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT, - .shape = PLD_SHAPE_OVAL, - .group = ACPI_PLD_GROUP(2, 1)}" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))" device ref usb2_port3 on end end chip drivers/usb/acpi @@ -377,24 +357,14 @@ register "desc" = ""USB2 Type-A Port (MLB)"" register "type" = "UPC_TYPE_A" register "use_custom_pld" = "true" - register "custom_pld" = "{ - .visible = true, - .panel = PLD_PANEL_LEFT, - .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT, - .shape = PLD_SHAPE_HORIZONTAL_RECTANGLE, - .group = ACPI_PLD_GROUP(4, 1)}" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, LEFT, ACPI_PLD_GROUP(4, 1))" device ref usb2_port8 on end end chip drivers/usb/acpi register "desc" = ""USB2 Type-A Port A0 (DB)"" register "type" = "UPC_TYPE_A" register "use_custom_pld" = "true" - register "custom_pld" = "{ - .visible = true, - .panel = PLD_PANEL_RIGHT, - .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT, - .shape = PLD_SHAPE_HORIZONTAL_RECTANGLE, - .group = ACPI_PLD_GROUP(1, 2)}" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(1, 2))" device ref usb2_port9 on end end chip drivers/usb/acpi @@ -408,24 +378,14 @@ register "desc" = ""USB3 Type-A Port A0 (DB)"" register "type" = "UPC_TYPE_USB3_A" register "use_custom_pld" = "true" - register "custom_pld" = "{ - .visible = true, - .panel = PLD_PANEL_RIGHT, - .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT, - .shape = PLD_SHAPE_HORIZONTAL_RECTANGLE, - .group = ACPI_PLD_GROUP(1, 2)}" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(1, 2))" device ref usb3_port1 on end end chip drivers/usb/acpi register "desc" = ""USB3 Type-A Port (MLB)"" register "type" = "UPC_TYPE_USB3_A" register "use_custom_pld" = "true" - register "custom_pld" = "{ - .visible = true, - .panel = PLD_PANEL_LEFT, - .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT, - .shape = PLD_SHAPE_HORIZONTAL_RECTANGLE, - .group = ACPI_PLD_GROUP(4, 1)}" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, LEFT, ACPI_PLD_GROUP(4, 1))" device ref usb3_port2 on end end chip drivers/usb/acpi -- To view, visit https://review.coreboot.org/c/coreboot/+/61828 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1a4bc1aae8e815b882a607432e40caf1066453b2 Gerrit-Change-Number: 61828 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/amd/chausie: Move EFS into FMAP section
by Fred Reitberger (Code Review) 11 Feb '22

11 Feb '22

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Fred Reitberger has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61717 ) Change subject: mb/amd/chausie: Move EFS into FMAP section ...................................................................... Patch Set 4: (1 comment) File src/mainboard/amd/chausie/Kconfig: https://review.coreboot.org/c/coreboot/+/61717/comment/4663ea56_c5b5a2db PS3, Line 28: default 5 > this can be dropped since 5 is the default AMD_FWM_POSITION_INDEX for BOARD_ROMSIZE_KB_16384 Done -- To view, visit https://review.coreboot.org/c/coreboot/+/61717 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8b5bddef199f5082bc5b541ef39a668160e9afff Gerrit-Change-Number: 61717 Gerrit-PatchSet: 4 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 10 Feb 2022 15:03:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/amd/chausie: Move EFS into FMAP section
by Fred Reitberger (Code Review) 11 Feb '22

11 Feb '22

Attention is currently required from: Jason Glenesk, Marshall Dawson, Fred Reitberger. Hello build bot (Jenkins), Jason Glenesk, Marshall Dawson, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61717 to look at the new patch set (#4). Change subject: mb/amd/chausie: Move EFS into FMAP section ...................................................................... mb/amd/chausie: Move EFS into FMAP section The chausie mainboard uses the first 128kByte of SPI flash for the EC firmware. The EFS/amdfw should be placed at the 128kByte offset. Due to this, there is no room for the CBFS headers. The AMD_SOC_SEPARATE_EFS_SECTION option is used to locate the EFS/amdfw via FMAP outside of the main CBFS, and move the CBFS to a later location. This patch enables AMD_SOC_SEPARATE_EFS_SECTION for chausie mainboards. Change-Id: I8b5bddef199f5082bc5b541ef39a668160e9afff Signed-off-by: Fred Reitberger <reitbergerfred(a)gmail.com> --- M src/mainboard/amd/chausie/Kconfig M src/mainboard/amd/chausie/board.fmd 2 files changed, 3 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/61717/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/61717 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8b5bddef199f5082bc5b541ef39a668160e9afff Gerrit-Change-Number: 61717 Gerrit-PatchSet: 4 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/siemens/mc_apl{2,4,5,6}: Enable recovery MRC cache
by Werner Zeh (Code Review) 11 Feb '22

11 Feb '22

Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61827 ) Change subject: mb/siemens/mc_apl{2,4,5,6}: Enable recovery MRC cache ...................................................................... mb/siemens/mc_apl{2,4,5,6}: Enable recovery MRC cache The mainboards mc_apl{2,4,5,6} use VBOOT for verification and can be in a recovery state for different reasons. In this case we still want the MRC cache to be around to avoid the DRAM retraining on every boot. This patch enables the Kconfig switch HAS_RECOVERY_MRC_CACHE which makes the already available MRC recovery region in FMAP useable. Test=Boot mc_apl2 in recovery mode and make sure the recovery MRC cache is used. Change-Id: I2ea4993f05dd87a0e637f55e84b4fc06f5e29ecc Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/mainboard/siemens/mc_apl1/variants/mc_apl2/Kconfig M src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig M src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig M src/mainboard/siemens/mc_apl1/variants/mc_apl6/Kconfig 4 files changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/61827/1 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/Kconfig b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/Kconfig index 3e062a4..af1a572 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/Kconfig +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/Kconfig @@ -11,6 +11,7 @@ select MAINBOARD_HAS_LPC_TPM select TPM_ON_FAST_SPI select TPM_MEASURED_BOOT + select HAS_RECOVERY_MRC_CACHE config CBFS_SIZE default 0xb4e000 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig index 6cf02ab..53729c2 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig @@ -10,6 +10,7 @@ select TPM_ON_FAST_SPI select DRIVERS_I2C_PTN3460 select TPM_MEASURED_BOOT + select HAS_RECOVERY_MRC_CACHE config UART_FOR_CONSOLE default 1 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig index 877470f..00d65ce 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig @@ -14,6 +14,7 @@ select TPM_ON_FAST_SPI select DRIVERS_I2C_PTN3460 select TPM_MEASURED_BOOT + select HAS_RECOVERY_MRC_CACHE config CBFS_SIZE default 0xb4e000 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/Kconfig b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/Kconfig index 812c4af..af8d058 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/Kconfig +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/Kconfig @@ -13,6 +13,7 @@ select MAINBOARD_HAS_LPC_TPM select TPM_ON_FAST_SPI select TPM_MEASURED_BOOT + select HAS_RECOVERY_MRC_CACHE config VBOOT select VBOOT_VBNV_FLASH -- To view, visit https://review.coreboot.org/c/coreboot/+/61827 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2ea4993f05dd87a0e637f55e84b4fc06f5e29ecc Gerrit-Change-Number: 61827 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newchange

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coreboot-gerrit February 2022