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Change subject: soc/intel/graphics: Create Kconfig for mapping graphic memory base
......................................................................
soc/intel/graphics: Create Kconfig for mapping graphic memory base
create SOC_INTEL_GFX_MEMBASE_OFFSET for platform to map graphic memory
base if required, because it may vary by platfrom.
BUG=b:216756721
TEST= Check default offset for existing platform and
update platform specific offset in Kconfig under SoC directory.
Change-Id: I6b1e34ada9b895dabcdc8116d2470e8831ed0a9e
Signed-off-by: Ethan Tsao <ethan.tsao(a)intel.com>
---
M src/soc/intel/common/block/graphics/Kconfig
M src/soc/intel/common/block/graphics/graphics.c
2 files changed, 16 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/61389/20
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Change subject: mb/google/var/agah: Use ACPI _PLD macro
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
> > oh, I mean for the port in the left/right, we can use acpi_pld_vertical_position. […]
When I check ACPI specification, front/back/left/right panels shall be viewed with the system resting on its bottom panel. So, I think vertical positions should indicate upper/center/lower positions.
https://uefi.org/specs/ACPI/6.4/06_Device_Configuration/Device_Configuratio…
In this case, since we were considering just laptops, vertical position is not added and would be set to default (upper), but I think we can also add vertical position for chrome box.
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Change subject: soc/amd/cezanne,picasso,sabrina: Fix incorrect values of CBFS amdfw position makefile variables
......................................................................
Patch Set 9: Code-Review+2
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Change subject: soc/intel/xeon_sp: Add function to clear PMCON status bits
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Patch Set 3: Code-Review+2
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Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Rob Barnes, Karthik Ramasubramanian, Felix Held,
I'd like you to reexamine a change. Please visit
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Change subject: soc/amd/cezanne: Turn off gpp clock request for disabled devices
......................................................................
soc/amd/cezanne: Turn off gpp clock request for disabled devices
The current behavior does not actually check if a device is present before enabling the corresponding gpp_clkx_clock_request_mapping bits which may cause issues with L1SS. This change sets the corresponding gpp_clkx_clock_request_mapping to off if the corresponding device is disabled.
BUG=b:202252869
TEST=Checked that value of GPP_CLK_CNTRL matched the expected value when devices are enabled/disabled
FIXED=b:202252869
BRANCH=guybrush
Signed-off-by: Robert Zieba <robertzieba(a)google.com>
Change-Id: I77389372c60bdec572622a3b49484d4789fd4e4c
---
M src/mainboard/amd/majolica/Makefile.inc
M src/mainboard/google/guybrush/Makefile.inc
M src/soc/amd/cezanne/chip.h
M src/soc/amd/cezanne/fch.c
4 files changed, 112 insertions(+), 14 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/61259/22
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Change subject: mb/google/var/agah: Use ACPI _PLD macro
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
> oh, I mean for the port in the left/right, we can use acpi_pld_vertical_position. And for the port in the front/back we can use acpi_pld_horizontal_position (chrome box).
https://patchwork.kernel.org/project/linux-acpi/patch/56D4B9BFEADA5948B1454…
I was referring to this one, where having panel and either horizontal or vertical alignment based on panel should be enough for device physical location. WYT?
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Change subject: mb/google/brya/variants/primus: add dram part id
......................................................................
Patch Set 2: Code-Review+2
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Change subject: mb/google/brya/var/primus4es: reconfig USE_PM_ACPI_TIMER
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
> > Could we submit this CL to enable S0iX on ES CPU? […]
suspend_stress_test checks the S0ix residency after each resume attempt and will fail if it does not detect an increase in the residency counter (https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/pla…), therefore this must be helping ES silicon achieve S0ix... sometimes things are very weird in pre-QS silicon
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Change subject: mb/google/var/agah: Use ACPI _PLD macro
......................................................................
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(1 comment)
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oh, I mean for the port in the left/right, we can use acpi_pld_vertical_position. And for the port in the front/back we can use acpi_pld_horizontal_position (chrome box).
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Change subject: mb/google/reef: Add VBTs for all variants
......................................................................
Patch Set 5: Code-Review+2
(1 comment)
Patchset:
PS5:
> Now I'm confused, sorry. Gerrit shows that it's always the same […]
Nvm. I checked it out and the files differ mostly (counting 6 different files).
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