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Change subject: mb/google/brya: remove the delay from for WWAN _ON method.
......................................................................
mb/google/brya: remove the delay from for WWAN _ON method.
Remove unecessary delay in RTD3 _ON Method after PERST# dessartion.
TEST:
2022-02-10T18:22:53.204391Z INFO kernel: [ 0.190287] ACPI: Power Resource [RTD3] (on)
2022-02-10T18:22:53.204395Z INFO kernel: [ 0.194252] ACPI: Power Resource [RTD3] (off)
Signed-off-by: Cliff Huang <cliff.huang(a)intel.com>
Change-Id: I9bc36af6e6c944fcd3de23b7d49640ad9d25642d
---
M src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb
1 file changed, 0 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/61783/2
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Sridhar Siricilla has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61834 )
Change subject: soc/intel/common: [TEST]Allow CSE boot from RO
......................................................................
soc/intel/common: [TEST]Allow CSE boot from RO
The patch helps system boots to OS in normal mode while CSE boots
from RO. When CSE boots from RO, and it doesn't use data partition
at all. Also, it boots from Soft Temp Disable Mode which is equivalent to
disabling CSE.
Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com>
Change-Id: I13af11d4e3c798d35a500ac772ddc9985fb1ccdc
---
M src/soc/intel/common/block/cse/cse_lite.c
1 file changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/61834/1
diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c
index 67dae1c..953c9ae 100644
--- a/src/soc/intel/common/block/cse/cse_lite.c
+++ b/src/soc/intel/common/block/cse/cse_lite.c
@@ -1068,8 +1068,10 @@
if (!cse_is_rw_bp_status_valid(&cse_bp_info.bp_info))
cse_trigger_vboot_recovery(CSE_LITE_SKU_RW_JUMP_ERROR);
+#if 0
if (!cse_boot_to_rw(&cse_bp_info.bp_info)) {
printk(BIOS_ERR, "cse_lite: Failed to switch to RW\n");
cse_trigger_vboot_recovery(CSE_LITE_SKU_RW_SWITCH_ERROR);
}
+#endif
}
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Robert Zieba has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61259 )
Change subject: soc/amd/cezanne: Turn off gpp clock request for disabled devices
......................................................................
Patch Set 23:
(5 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/61259/comment/caa6f798_6cfa9b06
PS20, Line 14: BRANCH
> Add a new line between this and the Signed-Off-By
Done
File src/soc/amd/cezanne/fch.c:
https://review.coreboot.org/c/coreboot/+/61259/comment/5dd3a5b6_b67c204a
PS20, Line 152: /*
: * The remapping of values is done so that the default of the enum used for the
: * devicetree settings is the clock being enabled, so that a missing devicetree
: * configuration for this will result in an always active clock and not an
: * inactive PCIe clock output.
: */
> we should keep this comment, since what it points out isn't very obvious
Done
https://review.coreboot.org/c/coreboot/+/61259/comment/1d2bf931_f7d98a58
PS20, Line 21: #include "include/soc/platform_descriptors.h"
> this should be #include <soc/platform_descriptors. […]
Done
https://review.coreboot.org/c/coreboot/+/61259/comment/036b0d36_ee86da84
PS20, Line 187: CLK_ENABLE
> this should probably be CLK_DISABLE
Done
https://review.coreboot.org/c/coreboot/+/61259/comment/a290546e_26c59b16
PS20, Line 188: 1
> replacing this 1 with CLK_REQ0 would at least for me make this line easier to understand
Done
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Hello build bot (Jenkins), Subrata Banik, Wonkyu Kim, Ravishankar Sarawadi, Tim Wawrzynczak, Paul Menzel, Raj Astekar, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/graphics: Create Kconfig for mapping graphic memory base
......................................................................
soc/intel/graphics: Create Kconfig for mapping graphic memory base
create SOC_INTEL_GFX_MEMBASE_OFFSET for platform to map graphic memory
base if required, because it may vary by platfrom.
BUG=b:216756721
TEST= Check default offset for existing platform and
update platform specific offset in Kconfig under SoC directory.
Change-Id: I6b1e34ada9b895dabcdc8116d2470e8831ed0a9e
Signed-off-by: Ethan Tsao <ethan.tsao(a)intel.com>
---
M src/soc/intel/common/block/graphics/Kconfig
M src/soc/intel/common/block/graphics/graphics.c
M src/soc/intel/common/block/include/intelblocks/graphics.h
3 files changed, 17 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/61389/21
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Won Chung has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61801 )
Change subject: acpi: Use ACPI macros to configure USB port _PLD object
......................................................................
Patch Set 3: Code-Review+1
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Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Rob Barnes, Karthik Ramasubramanian, Felix Held,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#23).
Change subject: soc/amd/cezanne: Turn off gpp clock request for disabled devices
......................................................................
soc/amd/cezanne: Turn off gpp clock request for disabled devices
The current behavior does not actually check if a device is present before enabling the corresponding gpp_clkx_clock_request_mapping bits which may cause issues with L1SS. This change sets the corresponding gpp_clkx_clock_request_mapping to off if the corresponding device is disabled.
BUG=b:202252869
TEST=Checked that value of GPP_CLK_CNTRL matched the expected value when devices are enabled/disabled
FIXED=b:202252869
BRANCH=guybrush
Signed-off-by: Robert Zieba <robertzieba(a)google.com>
Change-Id: I77389372c60bdec572622a3b49484d4789fd4e4c
---
M src/mainboard/amd/majolica/Makefile.inc
M src/mainboard/google/guybrush/Makefile.inc
M src/soc/amd/cezanne/chip.h
M src/soc/amd/cezanne/fch.c
4 files changed, 113 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/61259/23
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Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61803 )
Change subject: mb/google/var/agah: Use ACPI _PLD macro
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
> When I check ACPI specification, front/back/left/right panels shall be viewed with the system resting on its bottom panel. So, I think vertical positions should indicate upper/center/lower positions.
> https://uefi.org/specs/ACPI/6.4/06_Device_Configuration/Device_Configuratio…
>
> In this case, since we were considering just laptops, vertical position is not added and would be set to default (upper), but I think we can also add vertical position for chrome box.
+1 to what Won mentioned, I have same understanding for laptop devices. For Chromebox FF where multiple USB's are in stack, we could use vertical position also as another macro along side horizontal.
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Change subject: soc/intel/graphics: Create Kconfig for mapping graphic memory base
......................................................................
Patch Set 20:
(1 comment)
File src/soc/intel/common/block/graphics/Kconfig:
https://review.coreboot.org/c/coreboot/+/61389/comment/d51dcc70_712b3a0e
PS19, Line 26: to
: reach at DSM
> > Given that graphics_get_memory_base() is only used to guess the […]
Update function name to graphics_guess_framebuffer_address().
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Cliff Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61783 )
Change subject: mb/google/brya: reduce the time for WWAN _ON method delay.
......................................................................
Patch Set 1:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/61783/comment/0be99cf8_a972865e
PS1, Line 9: During booting to OS, ACPI calls _ON and immediately calls _OFF method.
> I think the logs are just indicating the status of each PowerResource after the kernel has decided w […]
I think you are correct!
https://review.coreboot.org/c/coreboot/+/61783/comment/657d301d_476917e4
PS1, Line 16: INFO kernel: [ 0.189801] ACPI: Power Resource [RTD3] (on)
: INFO kernel: [ 0.206510] ACPI: Power Resource [RTD3] (off)
> Actually, I think this is just the status of the two different RTD3 PowerResource objects (one for W […]
I think you are correct. Thanks for pointing out. However, the log does indicate the time spent for the 1st power resource.
This is the boot log with preivous delay: 1000 msec
[ 0.089461] ACPI: Power Resource [RTD3] (on)
[ 1.125167] ACPI: Power Resource [RTD3] (off) <- there 1+ second due to the delay
[ 1.125577] ACPI: Power Resource [PR00] (on)
[ 1.437048] ACPI: Power Resource [PRIC] (off)
[ 1.437112] ACPI: Power Resource [PRIC] (off)
[ 1.437804] ACPI: Power Resource [TBT0] (on)
[ 1.437820] ACPI: Power Resource [TBT1] (on)
[ 1.437837] ACPI: Power Resource [D3C] (on)
File src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/61783/comment/d60412b7_342062e1
PS1, Line 158: register "reset_delay_ms" = "10"
> What is the minimum time required by the datasheet?
The datasheet only shows there is 20 seconds HW initialization after de-assertion of PERST#. However, drivers needs to ensure that. not in ACPI. The datasheet does not provide data on what time duration needs to meet for the next assertion, though. The purpose of delay is just ensure that it is not causing a glitch by _OFF and immediately followed _ON. Note that we also, turn off/on the L23, modPHY clock, an src clock in the methods.
If this will never be the case, can I drop this delay entirely?
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