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Change subject: mb/google/var/agah: Use ACPI _PLD macro
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
If in the panel left/right the second description should be rear/mid/front;If in the panel rear/front the second description should be left/mid/right. Will this be more intuitive? This description is user faces.
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Change subject: soc/amd/cezanne: Turn off gpp clock request for disabled devices
......................................................................
Patch Set 21:
(2 comments)
File src/soc/amd/cezanne/fch.c:
https://review.coreboot.org/c/coreboot/+/61259/comment/b95f97e7_b8e4554d
PS20, Line 187: CLK_ENABLE
this should probably be CLK_DISABLE
https://review.coreboot.org/c/coreboot/+/61259/comment/64531ff3_95e4c2fb
PS20, Line 188: 1
replacing this 1 with CLK_REQ0 would at least for me make this line easier to understand
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Change subject: src/soc/intel/common/block/i2c: Use early BAR in ENV_PAYLOAD_LOADER
......................................................................
Patch Set 2:
(1 comment)
File src/soc/intel/common/block/i2c/i2c.c:
https://review.coreboot.org/c/coreboot/+/61719/comment/2942b1e9_357ece07
PS2, Line 135: pci_read_config32
> Ack
This is if no resources were found (probe_resource checks the resource_list), in this case the reason is because (with this patch train) I2C communication now will happen in ramstage but before PCI enumeration (other reasons could be because the device was disabled or had requested no resources), so we reuse the BAR that was assigned during early init because resource allocation hasn't happened yet.
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Change subject: mb/google/brya/var/brask: Enable ASPM of RTL8125
......................................................................
Patch Set 5:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/61268/comment/fc63999b_33da6414
PS5, Line 11: Here we add "enable_aspm_l1_2" in devicetree for RTL8125 to enable
: ASPM L1.2.
nit: no need for an extra line break here, you can move up to previous line
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Change subject: mb/google/brya/var/brask: Enable ASPM of RTL8125
......................................................................
Patch Set 5: Code-Review+2
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Change subject: drivers/net/r8168: Add ASPM control mechanism
......................................................................
Patch Set 5: Code-Review+2
(4 comments)
File src/drivers/net/chip.h:
https://review.coreboot.org/c/coreboot/+/61267/comment/654c169a_1b995310
PS4, Line 36: bool enable_aspm;
> Should the level be part of the variable name?
Done
File src/drivers/net/r8168.c:
https://review.coreboot.org/c/coreboot/+/61267/comment/3b2f9a17_cbbd9cef
PS4, Line 252: struct drivers_net_config *config = dev->chip_info;
: if (!config || !config->enable_aspm)
: return;
> Seeing the function name, I’d move this outside the function before calling it.
Done
https://review.coreboot.org/c/coreboot/+/61267/comment/bab96d51_4ef7b184
PS4, Line 256: printk(BIOS_INFO, "rtl: enable_aspm_L1.2\n");
> Maybe: […]
Done
https://review.coreboot.org/c/coreboot/+/61267/comment/40535509_5f81d3d1
PS4, Line 363: /* Enable ASPM_L1.2 */
> Comment not needed, as the function name says the same.
Done
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Change subject: soc/intel/skylake: Add function to clear PMCON status bits
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS2:
> :) Good question. […]
sadly no, I need more than a basic Intel account to access the EDS docs
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Change subject: mb/google/brya: reduce the time for WWAN _ON method delay.
......................................................................
Patch Set 1:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/61783/comment/24488325_fcbfceae
PS1, Line 9: During booting to OS, ACPI calls _ON and immediately calls _OFF method.
I think the logs are just indicating the status of each PowerResource after the kernel has decided what to do with it?
https://review.coreboot.org/c/coreboot/+/61783/comment/20a9f0fa_f181f03c
PS1, Line 16: INFO kernel: [ Â Â 0.189801] ACPI: Power Resource [RTD3] (on)
: INFO kernel: [ Â Â 0.206510] ACPI: Power Resource [RTD3] (off)
Actually, I think this is just the status of the two different RTD3 PowerResource objects (one for WWAN and one for the SD card reader. This is the kernel turning on or off each PowerResource after it has scanned the tables and determined which ones need to be on or off (based on _STA, I suppose).
File src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/61783/comment/5f09eb94_b5697b51
PS1, Line 158: register "reset_delay_ms" = "10"
What is the minimum time required by the datasheet?
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Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Rob Barnes, Karthik Ramasubramanian, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/61259
to look at the new patch set (#21).
Change subject: soc/amd/cezanne: Turn off gpp clock request for disabled devices
......................................................................
soc/amd/cezanne: Turn off gpp clock request for disabled devices
The current behavior does not actually check if a device is present before enabling the corresponding gpp_clkx_clock_request_mapping bits which may cause issues with L1SS. This change sets the corresponding gpp_clkx_clock_request_mapping to off if the corresponding device is disabled.
BUG=b:202252869
TEST=Checked that value of GPP_CLK_CNTRL matched the expected value when devices are enabled/disabled
FIXED=b:202252869
BRANCH=guybrush
Signed-off-by: Robert Zieba <robertzieba(a)google.com>
Change-Id: I77389372c60bdec572622a3b49484d4789fd4e4c
---
M src/mainboard/amd/majolica/Makefile.inc
M src/mainboard/google/guybrush/Makefile.inc
M src/soc/amd/cezanne/chip.h
M src/soc/amd/cezanne/fch.c
4 files changed, 112 insertions(+), 14 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/61259/21
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Fred Reitberger has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61833 )
Change subject: soc/amd/sabrina: Select ACP gen2
......................................................................
soc/amd/sabrina: Select ACP gen2
Select ACP gen2 for Sabrina
Change-Id: I107ebd390732b597629a3236d0e7d1f5e2c51379
Signed-off-by: Fred Reitberger <reitbergerfred(a)gmail.com>
---
M src/soc/amd/sabrina/Kconfig
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/61833/1
diff --git a/src/soc/amd/sabrina/Kconfig b/src/soc/amd/sabrina/Kconfig
index 86d97d5..f9f2ea3 100644
--- a/src/soc/amd/sabrina/Kconfig
+++ b/src/soc/amd/sabrina/Kconfig
@@ -39,7 +39,7 @@
select RESET_VECTOR_IN_RAM
select RTC
select SOC_AMD_COMMON
- select SOC_AMD_COMMON_BLOCK_ACP_GEN1 # TODO: Check if this is still correct - change to GEN2
+ select SOC_AMD_COMMON_BLOCK_ACP_GEN2
select SOC_AMD_COMMON_BLOCK_ACPI # TODO: Check if this is still correct
select SOC_AMD_COMMON_BLOCK_ACPIMMIO
select SOC_AMD_COMMON_BLOCK_ACPI_ALIB # TODO: Check if this is still correct
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