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Change subject: soc/intel/skylake: Add function to clear PMCON status bits
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Patch Set 3: Code-Review+1
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Change subject: soc/intel/skylake: Add function to clear PMCON status bits
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Patch Set 3:
(3 comments)
Patchset:
PS2:
> sadly no, I need more than a basic Intel account to access the EDS docs
checked against doc# 545845
File src/soc/intel/skylake/pmutil.c:
https://review.coreboot.org/c/coreboot/+/61650/comment/70fe2019_366562b0
PS3, Line 269: void pmc_clear_pmcon_sts(void)
this function is all the same for all platforms using common code, so why exactly do we have to copy-pasta it once again instead of finally moving it to soc/intel/common?
https://review.coreboot.org/c/coreboot/+/61650/comment/d82de472_93d096e8
PS3, Line 276: /* Clear SUS_PWR_FLR, GBL_RST_STS, HOST_RST_STS, PWR_FLR bits
: * while retaining MS4V write-1-to-clear bit
nit: not a valid comment according to coreboot codestyle docs ;)
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Change subject: sb,soc/intel: Use register_new_ioapic_gsi0()
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Patch Set 8:
(2 comments)
Patchset:
PS8:
> I don't, but Keith has mentioned that he has p2b-ds, though he didn't have a paired set of processor […]
I have a DS which should be similar enough to a D, but I do not have a pair of matching CPUs.
PS8:
Sorry I am late to the game, but what is the purpose of this patch train?
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Change subject: mb/google/brya: remove the delay from for WWAN _ON method.
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Patch Set 2:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/61783/comment/f5e55233_ff8ba6f2
PS1, Line 9: During booting to OS, ACPI calls _ON and immediately calls _OFF method.
> I think you are correct!
Ack
https://review.coreboot.org/c/coreboot/+/61783/comment/85e862ce_84409bde
PS1, Line 16: INFO kernel: [ 0.189801] ACPI: Power Resource [RTD3] (on)
: INFO kernel: [ 0.206510] ACPI: Power Resource [RTD3] (off)
> I think you are correct. Thanks for pointing out. […]
Yep sure does! _ON has that 1s delay in there.
File src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/61783/comment/72fc65cb_553f8ba9
PS1, Line 158: register "reset_delay_ms" = "10"
> The datasheet only shows there is 20 seconds HW initialization after de-assertion of PERST#. […]
With un-characterized ramp-up and ramp-down times on these signals, a 10ms delay is probably pretty safe and also not excessive. WDYT?
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Change subject: sb,soc/intel: Use register_new_ioapic_gsi0()
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Patch Set 8:
(1 comment)
Patchset:
PS8:
> Branden, Keith: Do you have ASUS P2B-D ?
I don't, but Keith has mentioned that he has p2b-ds, though he didn't have a paired set of processors to use with.
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Change subject: sb,soc/intel: Use register_new_ioapic_gsi0()
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Patch Set 8:
(2 comments)
Patchset:
PS8:
Branden, Keith: Do you have ASUS P2B-D ?
File src/southbridge/intel/i82371eb/isa.c:
https://review.coreboot.org/c/coreboot/+/55314/comment/b5446c80_ba560765
PS8, Line 64: register_new_ioapic_gsi0(VIO_APIC_VADDR);
The hardware uses APIC BUS so IOAPIC must not overlap any LAPIC ID.
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