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Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61652 )
Change subject: soc/intel/xeon_sp: Add function to clear PMCON status bits
......................................................................
Patch Set 3:
(1 comment)
File src/soc/intel/xeon_sp/pmutil.c:
https://review.coreboot.org/c/coreboot/+/61652/comment/e9040c2e_cfb19986
PS3, Line 187: addr = pmc_mmio_regs();
:
: reg_val = read32(addr + GEN_PMCON_A);
:
PCICFG
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Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60818 )
Change subject: Update arm-trusted-firmware submodule to upstream master
......................................................................
Update arm-trusted-firmware submodule to upstream master
Updating from commit id 73193689c:
2021-12-06 16:47:33 +0100 - (Merge changes I7c9f8490,Ia92c6d19 into integration)
to commit id e0a6a512b:
2022-02-03 22:59:34 +0100 - (Merge changes from topic "msm8916" into integration)
This brings in 324 new commits.
Signed-off-by: Martin Roth <gaumless(a)gmail.com>
Change-Id: I44bca36f4b05e08fe7d7de0966131be84c0a7d2b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60818
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Julius Werner <jwerner(a)chromium.org>
---
M 3rdparty/arm-trusted-firmware
1 file changed, 1 insertion(+), 1 deletion(-)
Approvals:
build bot (Jenkins): Verified
Julius Werner: Looks good to me, approved
diff --git a/3rdparty/arm-trusted-firmware b/3rdparty/arm-trusted-firmware
index 7319368..e0a6a51 160000
--- a/3rdparty/arm-trusted-firmware
+++ b/3rdparty/arm-trusted-firmware
@@ -1 +1 @@
-Subproject commit 73193689c0e9cf13ad0ddbb9da25e9a66c4e14b3
+Subproject commit e0a6a512b51558b64eb500e6b731e4c743050af2
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Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60971 )
Change subject: tests/include: Move EMPTY_WRAP() macro to tests/include/test.h
......................................................................
tests/include: Move EMPTY_WRAP() macro to tests/include/test.h
EMPTY_WRAP() might be useful for tests other than CBFS's ones. Move it
to the main tests header file to make it easily accessible.
Change-Id: Ic06c55912488681daf6d2c48cb0c879fa97ba4be
Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60971
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg(a)chromium.org>
---
M tests/include/tests/lib/cbfs_util.h
M tests/include/tests/test.h
2 files changed, 3 insertions(+), 3 deletions(-)
Approvals:
build bot (Jenkins): Verified
Paul Fagerburg: Looks good to me, approved
diff --git a/tests/include/tests/lib/cbfs_util.h b/tests/include/tests/lib/cbfs_util.h
index 8475946..64096d2 100644
--- a/tests/include/tests/lib/cbfs_util.h
+++ b/tests/include/tests/lib/cbfs_util.h
@@ -44,9 +44,6 @@
#define HASH_ATTR_SIZE (offsetof(struct cbfs_file_attr_hash, hash.raw) + VB2_SHA256_DIGEST_SIZE)
-/* This macro basically does nothing but suppresses linter messages */
-#define EMPTY_WRAP(...) __VA_ARGS__
-
#define TEST_DATA_1_FILENAME "test/data/1"
#define TEST_DATA_1_SIZE sizeof((u8[]){TEST_DATA_1})
#define TEST_DATA_1 EMPTY_WRAP( \
diff --git a/tests/include/tests/test.h b/tests/include/tests/test.h
index 523f8fa..45b542e 100644
--- a/tests/include/tests/test.h
+++ b/tests/include/tests/test.h
@@ -14,6 +14,9 @@
#include <setjmp.h>
#include <cmocka.h>
+/* This macro basically does nothing but suppresses linter messages */
+#define EMPTY_WRAP(...) __VA_ARGS__
+
/*
* Set symbol value and make it global.
*/
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Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60825 )
Change subject: Update qc_blobs submodule to upstream master
......................................................................
Update qc_blobs submodule to upstream master
Updating from commit id 98db386:
2021-08-03 11:57:30 -0700 - (herobrine: Add gsi_fw_blobs and Release Notes)
to commit id 9ab0f0b:
2022-01-18 19:01:30 +0530 - (sc7280: Update AOP firmware to version 379)
This brings in 13 new commits:
9ab0f0b sc7280: Update AOP firmware to version 379
826cb9c sc7180/boot : Update qclib blobs binaries and release notes
ddf67d1 sc7280/ boot and shrm blobs updated
8592f11 sc7280: Update AOP firmware to version 364
aef8a0a sc7280/ boot and shrm blobs updated
c72bc4e sc7280/cpucp: Update cpucp blobs binaries and release notes version from 054 to 060
33e57fe sc7280/boot,/shrm : Update qclib blobs binaries and release notes version 13
511851b sc7180/boot : Update qclib blobs binaries and release notes version 30
f91d0ef herobrine: qc_sec blob update
8c50f78 sc7180/boot : Update qclib blobs binaries and release notes
8523ef4 sc7180/qtiseclib: Update version from 26 to 44
5b77a37 sc7280/qtiseclib: Update version from 33 to 44
4815cc2 sc7280: Update AOP firmware to version 360
Signed-off-by: Martin Roth <gaumless(a)gmail.com>
Change-Id: I510141916900507fd29a0e9315a3f8d954bc0cab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60825
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---
M 3rdparty/qc_blobs
1 file changed, 1 insertion(+), 1 deletion(-)
Approvals:
build bot (Jenkins): Verified
Julius Werner: Looks good to me, approved
diff --git a/3rdparty/qc_blobs b/3rdparty/qc_blobs
index 98db386..9ab0f0b 160000
--- a/3rdparty/qc_blobs
+++ b/3rdparty/qc_blobs
@@ -1 +1 @@
-Subproject commit 98db38671b651dd7e7966fb629d65ff5dd23865b
+Subproject commit 9ab0f0b71c25aa8414e72040bad6fe12b0ccb3f3
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Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61650 )
Change subject: soc/intel/skylake: Add function to clear PMCON status bits
......................................................................
Patch Set 3:
(2 comments)
File src/soc/intel/skylake/pmutil.c:
https://review.coreboot.org/c/coreboot/+/61650/comment/11335eb1_3edd22e6
PS3, Line 269: void pmc_clear_pmcon_sts(void)
> > > > > > this function is all the same for all platforms using common code, so why exactly do we have to copy-pasta it once again instead of finally moving it to soc/intel/common?
> > > > >
> > > > > There are few SOCs which eventually uses the IA PMC common code but the SOC EDS does have exact register details. I've tried creating the common code which eventually need to resolve the register definitions from SoC layer as GEN_PMCON_A offset is not same across all SoC. But due to documentation limitation issue, I just avoided pursuing that path.
> > > >
> > > > Well, when the GEN_PMCON_A offset differs, it can be defined in the SoC headers, but the code can still be common code. Same applies to the bit MS4V, which is the only bit offset needed to be known, right?
> > >
> > > Denverton
> >
> > Oh. Yay. Denverton. *sigh* I've had *some* "fun" with denverton, too, in this regard...
> >
>
> And on DNV, it's not the PCI MMIO space instead it's the PCI config space offset hence the access method is not exactly same with other SOCs.
>
> >
> > > Denverton uses PMC IA common code but GEN_PMCON_A is not there is soc/pm.h or soc/pmc.h. I ran into issue due to not having macro resolved by all SOC layer.
> >
> > ```
> > $ grep -r PMCON_A src/soc/intel/
> > src/soc/intel/denverton_ns/include/soc/pmc.h:#define PMC_GEN_PMCON_A 0xA0
>
> It's in PCI config space hence one need to do PCI config read where other PMCON_A belongs to PCI MMIO. It's too much of guarding one need. Hence, I dropped the making common effort.
Ooooh well, check my other comment. What about introducing GEN_PMCON_ON_MMIO? :D
>
> > ```
> >
> > Hmmm? 😊 You just have to rename it
> >
> > > I think there is one more SOC compliant about the same.
> >
> > Probably xeon_sp, or apl/glk...
> >
> > > Moving things common without any guard might need to have all SoC implements the required macro isn't it?
> >
> > Correct. Probably only APL/GLK has to be guarded, though, or... does it? PMCON_A seems to be PMCON_1 there.
>
> yes, both are same but just EDS naming convention difference.
>
> >
> > >
> > > >
> > > > >
> > > > > > btw. this probably should be done in soc_pmc_init instead of finalize.
> > > > >
> > > > > The reason this is being done as part of finalize is to ensure that prior booting to OS, those bits are cleared.
> > > > >
> > > > > Note: FSP can even request a global reset during FSP notify (which is post soc_pmc_init) hence, after global reset, this corresponding bit would have set. And, we might need to clear it prior to boot.
> > > >
> > > > Got it, thanks! Add a short comment for this, please.
>
> I will, thanks,
>
> > > >
> > > > > There is no harm if you would like to call this more than once.
> > > >
> > > > Please don't 😄
> > >
> > > Although EDS says, writing 0 in this bit doesn't take any effect as it's RW/1C. But my comment to ensure we should remove the redundant to keep only one copy.
https://review.coreboot.org/c/coreboot/+/61650/comment/440e415b_da533650
PS3, Line 273: addr = pmc_mmio_regs();
:
: reg_val = read32(addr + GEN_PMCON_A);
whooops. on SPT/KBP this is PCICFG, not MMIO. sorry, I must have been boss-eyed when checking the EDS -.-
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Fred Reitberger has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61461 )
Change subject: mb/amd/chausie: update GPIO for chausie
......................................................................
Patch Set 7:
(3 comments)
File src/mainboard/amd/chausie/early_gpio.c:
https://review.coreboot.org/c/coreboot/+/61461/comment/f7fdcb58_313740a2
PS6, Line 28: /* Deassert PCIe Reset lines */
> i'd put this comment in the same level of indentation as the code
Done
https://review.coreboot.org/c/coreboot/+/61461/comment/8adfb68c_b42715e2
PS6, Line 50: SMBUS0
> this is the I2C2 SCL and not the SMBUS0 SCL, so the comment doesn't match the code. […]
Done
File src/mainboard/amd/chausie/gpio.c:
https://review.coreboot.org/c/coreboot/+/61461/comment/7e2129ef_91e78499
PS6, Line 113: SMBUS0
> see my comment on the other file
Done
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Hello build bot (Jenkins), Jason Glenesk, Marshall Dawson, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/61461
to look at the new patch set (#7).
Change subject: mb/amd/chausie: update GPIO for chausie
......................................................................
mb/amd/chausie: update GPIO for chausie
Add/update initial GPIO pin descriptions and initialization types for
chausie mainboard.
Change-Id: I14ea0e1086f626398a867896ee81ce07cf530182
Signed-off-by: Fred Reitberger <reitbergerfred(a)gmail.com>
---
M src/mainboard/amd/chausie/Makefile.inc
M src/mainboard/amd/chausie/early_gpio.c
A src/mainboard/amd/chausie/gpio.c
M src/mainboard/amd/chausie/gpio.h
M src/mainboard/amd/chausie/mainboard.c
5 files changed, 213 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/61461/7
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Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61451 )
Change subject: soc/intel/cannonlake: Use SBI msg to disable HECI1
......................................................................
Patch Set 8:
(1 comment)
Patchset:
PS8:
> > presumably because heci1_disable() is called from SMM, but the call to disable via PMC is guarded with !ENV_SMM
>
> Disabling via PMC doesn't need to execute in SMM mode, the SBI msg need to run in SBI mode.
>
> Do you see any error with default selection aka SBI msg in SMM mode. I mean, if you have debug time and I don't have board handy.
May be you need to enable DEBUG_SMI config ? to get the log.
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