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Change subject: mb/google/brya/var/nivviks: Initialise overridetree
......................................................................
Patch Set 5:
(1 comment)
File src/mainboard/google/brya/variants/nivviks/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/61605/comment/65ed6f3c_2afd5927
PS1, Line 10: SaGv_Enabled
> System is table with SaGv enabled in the current FSP version.
Thanks Rizwan. That's great to hear.
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Eugene Myers has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60826 )
Change subject: Update stm submodule to upstream master
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> Hi Eugene, […]
Sorry for my tardy response, somehow the notification mechanism didn't let me know that you had sent me a message.
To answer your question, you should mirror this repository: https://github.com/EugeneDMyers/STM branch: stmpe. There have been a couple of updates to the repository.
The upstream repository master (https://github.com/jyao1/STM ) is stale and the stmpe brach there is out-of-date.
Please do not update the pointer for 3rdparty/stm yet. I just found out that there may be an STM issue and I would like to address it before releasing the patches.
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Change subject: mb/google/brya/var/primus4es: reconfig USE_PM_ACPI_TIMER
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
> Thanks, hmmmm... leaves me with more questions, though :D the sysfs attribute read […]
I'm referring to this counter: https://github.com/torvalds/linux/blob/master/drivers/platform/x86/intel/pm… I guess it's the SLP_S0# residency, I don't see anything about shallow or deep there though, and my assumption was that correlated ~100% to S0ix residency
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Change subject: mb/google/brya/var/primus4es: reconfig USE_PM_ACPI_TIMER
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
> suspend_stress_test checks the S0ix residency after each resume attempt and will fail if it does not […]
Thanks, hmmmm... leaves me with more questions, though :D the sysfs attribute read
has only one driver upstream, for Apollo Lake. And there it does count some "deep"
and "shallow" s0ix residency together, whatever that means :)
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Change subject: mb/google/nissa: Set half_populated true
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Patch Set 5: Code-Review+2
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Change subject: soc/intel/common: Re-use Alder Lake-M device IDs for Alder Lake-N
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Patch Set 6: Code-Review+2
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Change subject: mb/google/brya: remove the delay from for WWAN _ON method.
......................................................................
Patch Set 2:
(1 comment)
File src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/61783/comment/d9954c93_d316592d
PS1, Line 158: register "reset_delay_ms" = "10"
> With un-characterized ramp-up and ramp-down times on these signals, a 10ms delay is probably pretty […]
Yes. I think so, too. In addition, I just dropped entire delay and tested to have more boot time budget for the future. we can go ether way. Please let me know.
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Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60830 )
Change subject: util/ifdtool: Add support for Denverton Soc
......................................................................
Patch Set 13:
(1 comment)
Patchset:
PS13:
Hi Jeff,
It looks like this needs to be manually rebased before it can be merged. Paul also had a couple of reviews that need to be resolved before anyone can merge it.
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Change subject: soc/intel/cannonlake: Use SBI msg to disable HECI1
......................................................................
Patch Set 8:
(1 comment)
Patchset:
PS8:
> > > presumably because heci1_disable() is called from SMM, but the call to disable via PMC is guarde […]
[EMERG] Unable to unhide the P2SB device!
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