coreboot-gerrit November 2022

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[S] Change in coreboot[master]: nb/intel/sandybridge: Hook up CPU bus and PCI domain ops to devicetree
by Felix Held (Code Review) 30 Nov '22

30 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69291 ) ( 13 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: nb/intel/sandybridge: Hook up CPU bus and PCI domain ops to devicetree ...................................................................... nb/intel/sandybridge: Hook up CPU bus and PCI domain ops to devicetree Change-Id: I718d9dbc184c8bca38f452efea3202901018cb04 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69291 Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/northbridge/intel/sandybridge/chipset.cb M src/northbridge/intel/sandybridge/northbridge.c 2 files changed, 18 insertions(+), 13 deletions(-) Approvals: build bot (Jenkins): Verified Kyösti Mälkki: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/src/northbridge/intel/sandybridge/chipset.cb b/src/northbridge/intel/sandybridge/chipset.cb index ae02a5b..e7ade19 100644 --- a/src/northbridge/intel/sandybridge/chipset.cb +++ b/src/northbridge/intel/sandybridge/chipset.cb @@ -2,6 +2,7 @@ chip northbridge/intel/sandybridge device cpu_cluster 0 on + ops sandybridge_cpu_bus_ops chip cpu/intel/model_206ax # Magic APIC ID to locate this chip device lapic 0 on end @@ -14,5 +15,6 @@ end device domain 0 on + ops sandybridge_pci_domain_ops end end diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 521044b..ad85d68 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -52,7 +52,7 @@ return NULL; } -static struct device_operations pci_domain_ops = { +struct device_operations sandybridge_pci_domain_ops = { .read_resources = pci_domain_read_resources, .set_resources = pci_domain_set_resources, .scan_bus = pci_domain_scan_bus, @@ -412,23 +412,12 @@ .devices = pci_device_ids, }; -static struct device_operations cpu_bus_ops = { +struct device_operations sandybridge_cpu_bus_ops = { .read_resources = noop_read_resources, .set_resources = noop_set_resources, .init = mp_cpu_bus_init, }; -static void enable_dev(struct device *dev) -{ - /* Set the operations if it is a special bus type */ - if (dev->path.type == DEVICE_PATH_DOMAIN) { - dev->ops = &pci_domain_ops; - } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { - dev->ops = &cpu_bus_ops; - } -} - struct chip_operations northbridge_intel_sandybridge_ops = { CHIP_NAME("Intel SandyBridge/IvyBridge integrated Northbridge") - .enable_dev = enable_dev, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/69291 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I718d9dbc184c8bca38f452efea3202901018cb04 Gerrit-Change-Number: 69291 Gerrit-PatchSet: 15 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/google/brya/acpi: Update NVPCF_FUNC_UPDATE_DYNAMIC_PARAMS
by Tarun Tuli (Code Review) 30 Nov '22

30 Nov '22

Attention is currently required from: Subrata Banik, Paul Menzel, Nick Vaccaro. Tarun Tuli has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69639 ) Change subject: mb/google/brya/acpi: Update NVPCF_FUNC_UPDATE_DYNAMIC_PARAMS ...................................................................... Patch Set 10: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/69639/comment/9ac39119_d6560944 PS9, Line 9: Update location of TGP (MAGA) to Params2[15:0] : Add TPPA (value of 25W) > Please format this as a list. Done https://review.coreboot.org/c/coreboot/+/69639/comment/54edd425_855cea79 PS9, Line 13: . : . : . > Why the three lines? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/69639 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69b80f4af2ecef6cf91034fc15fb6e8715eeca4f Gerrit-Change-Number: 69639 Gerrit-PatchSet: 10 Gerrit-Owner: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Wed, 30 Nov 2022 15:57:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/brya/acpi: Update NVPCF_FUNC_UPDATE_DYNAMIC_PARAMS
by Tarun Tuli (Code Review) 30 Nov '22

30 Nov '22

Attention is currently required from: Tarun Tuli, Subrata Banik, Nick Vaccaro. Hello build bot (Jenkins), Subrata Banik, Nick Vaccaro, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69639 to look at the new patch set (#10). Change subject: mb/google/brya/acpi: Update NVPCF_FUNC_UPDATE_DYNAMIC_PARAMS ...................................................................... mb/google/brya/acpi: Update NVPCF_FUNC_UPDATE_DYNAMIC_PARAMS 1) Update location of TGP (MAGA) to Params2[15:0] 2) Add TPPA (value of 25W) Package: ... Case (0x02) { Local0 = Buffer (0x31) { 0x22, 0x05, 0x10, 0x1C, 0x01 } CreateWordField (Local0, 0x1D, MAGA) CreateWordField (Local0, 0x19, TPPA) CreateDWordField (Local0, 0x15, CEO0) MAGA = 0x50 TPPA = 0xC8 CEO0 = 0x0200 Return (Local0) } ... BUG=b:214581372 TEST=build and verify DSDT on device Signed-off-by: Tarun Tuli <taruntuli(a)google.com> Change-Id: I69b80f4af2ecef6cf91034fc15fb6e8715eeca4f --- M src/mainboard/google/brya/acpi/nvpcf.asl 1 file changed, 39 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/69639/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/69639 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69b80f4af2ecef6cf91034fc15fb6e8715eeca4f Gerrit-Change-Number: 69639 Gerrit-PatchSet: 10 Gerrit-Owner: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: Documentation: Add wake source info to device tree documentation
by Raul Rangel (Code Review) 30 Nov '22

30 Nov '22

Attention is currently required from: Dmitry Torokhov, Tim Wawrzynczak, Paul Menzel, Tim Van Patten, Karthik Ramasubramanian. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67385 ) Change subject: Documentation: Add wake source info to device tree documentation ...................................................................... Patch Set 7: (1 comment) File Documentation/drivers/dt_entries.md: https://review.coreboot.org/c/coreboot/+/67385/comment/302d781a_4637b944 PS7, Line 208: method > Nit: methods Done -- To view, visit https://review.coreboot.org/c/coreboot/+/67385 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifcdbd5371408784bf9b81c1ade90263de8c60e0f Gerrit-Change-Number: 67385 Gerrit-PatchSet: 7 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Dmitry Torokhov <dtor(a)chromium.org> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Mark Hasemeyer <markhas(a)google.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Robert Zieba <robertzieba(a)google.com> Gerrit-CC: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Dmitry Torokhov <dtor(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 30 Nov 2022 15:40:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: Documentation: Add wake source info to device tree documentation
by Raul Rangel (Code Review) 30 Nov '22

30 Nov '22

Attention is currently required from: Dmitry Torokhov, Tim Wawrzynczak, Paul Menzel, Tim Van Patten, Karthik Ramasubramanian. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67385 ) Change subject: Documentation: Add wake source info to device tree documentation ...................................................................... Patch Set 8: (1 comment) File Documentation/drivers/dt_entries.md: https://review.coreboot.org/c/coreboot/+/67385/comment/e782f442_50a9b28c PS7, Line 130: "Level" and "Active" > Nit: "Trigger" and "Polarity" Done -- To view, visit https://review.coreboot.org/c/coreboot/+/67385 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifcdbd5371408784bf9b81c1ade90263de8c60e0f Gerrit-Change-Number: 67385 Gerrit-PatchSet: 8 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Dmitry Torokhov <dtor(a)chromium.org> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Mark Hasemeyer <markhas(a)google.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Robert Zieba <robertzieba(a)google.com> Gerrit-CC: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Dmitry Torokhov <dtor(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 30 Nov 2022 15:39:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: Documentation: Add wake source info to device tree documentation
by Raul Rangel (Code Review) 30 Nov '22

30 Nov '22

Attention is currently required from: Dmitry Torokhov, Tim Wawrzynczak, Paul Menzel, Tim Van Patten, Karthik Ramasubramanian. Hello build bot (Jenkins), Dmitry Torokhov, Jon Murphy, Tim Wawrzynczak, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/67385 to look at the new patch set (#8). Change subject: Documentation: Add wake source info to device tree documentation ...................................................................... Documentation: Add wake source info to device tree documentation The device tree documentation was promoting using a GPIO wake event and a GPE wake event. We should only ever have one. This wasn't actually causing a problem because the wake bit was set on the `irq` property, but the IO-APIC can't actually wake the system, so it was a no-op. This change fixes up the markdown so it's formatted correctly, and also adds a section explaining what the different wake configurations are. BUG=b:243700486 TEST=mdformat Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Ifcdbd5371408784bf9b81c1ade90263de8c60e0f --- M Documentation/drivers/dt_entries.md 1 file changed, 113 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/67385/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/67385 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifcdbd5371408784bf9b81c1ade90263de8c60e0f Gerrit-Change-Number: 67385 Gerrit-PatchSet: 8 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Dmitry Torokhov <dtor(a)chromium.org> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Mark Hasemeyer <markhas(a)google.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Robert Zieba <robertzieba(a)google.com> Gerrit-CC: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Dmitry Torokhov <dtor(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mb/prodrive/atlas: Enable GPP_B14 buzzer support
by Lean Sheng Tan (Code Review) 30 Nov '22

30 Nov '22

Attention is currently required from: Paul Menzel, Christian Walter, Angel Pons, Maximilian Brune. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67553 ) Change subject: mb/prodrive/atlas: Enable GPP_B14 buzzer support ...................................................................... Patch Set 12: (5 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/67553/comment/cd74e94d_cbe1b5c5 PS3, Line 12: will not work as 8254 has to be gated instead. > Could you also include the source of information, where it's stated that S0ix does not work with 825 […] Done, added the doc number for S0ix checklist. File src/mainboard/prodrive/atlas/Kconfig: https://review.coreboot.org/c/coreboot/+/67553/comment/2eb18a52_e0e957b9 PS3, Line 47: config ENABLE_BUZZER_SUPPORT > Make it a choice between S0ix support and buzzer support? Thanks for reviewing. I disabled s0ix in device tree directly as confirmed with customer it is not part of platform requirements. https://review.coreboot.org/c/coreboot/+/67553/comment/93042f71_68605b13 PS3, Line 48: bool > Shouldn't this have a prompt? I just set Buzzer enabled as default as s0ix is not part of Atlas requirements. https://review.coreboot.org/c/coreboot/+/67553/comment/4f620ed9_72e5d058 PS3, Line 50: default n if !SOC_INTEL_ALDERLAKE_S3 > You need to invert the defaults, so that the conditional one comes first. […] Mentioned above. https://review.coreboot.org/c/coreboot/+/67553/comment/1904729d_5ac614f3 PS3, Line 54: S0ix > There's a `s0ix_enable` field in the devicetree which needs to be configured accordingly. Done, I set it as disabled due to it is requirement for Atlas. -- To view, visit https://review.coreboot.org/c/coreboot/+/67553 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib5e7787a47509ed09818d8515d21a80196fb1ec6 Gerrit-Change-Number: 67553 Gerrit-PatchSet: 12 Gerrit-Owner: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Comment-Date: Wed, 30 Nov 2022 15:19:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Maximilian Brune <maximilian.brune(a)9elements.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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[L] Change in coreboot[master]: nb/intel/sandybridge: Add a chipset devicetree
by Martin L Roth (Code Review) 30 Nov '22

30 Nov '22

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56912 ) ( 6 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: nb/intel/sandybridge: Add a chipset devicetree ...................................................................... nb/intel/sandybridge: Add a chipset devicetree This only moves CPU configuration to a common place. Other PCI devices can be done in follow-ups. Change-Id: I9c5b6f25b779e28b6719cf70455ff0f1a916ad87 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56912 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/apple/macbookair4_2/devicetree.cb M src/mainboard/asrock/b75pro3-m/devicetree.cb M src/mainboard/asrock/h77pro4-m/devicetree.cb M src/mainboard/asus/h61-series/devicetree.cb M src/mainboard/asus/maximus_iv_gene-z/devicetree.cb M src/mainboard/asus/p8x7x-series/devicetree.cb M src/mainboard/biostar/th61-itx/devicetree.cb M src/mainboard/compulab/intense_pc/devicetree.cb M src/mainboard/dell/snb_ivb_workstations/variants/baseboard/devicetree.cb M src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb M src/mainboard/gigabyte/ga-h61m-series/devicetree.cb M src/mainboard/google/butterfly/devicetree.cb M src/mainboard/google/link/devicetree.cb M src/mainboard/google/parrot/devicetree.cb M src/mainboard/google/stout/devicetree.cb M src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb M src/mainboard/hp/snb_ivb_laptops/devicetree.cb M src/mainboard/hp/z220_series/devicetree.cb M src/mainboard/intel/dcp847ske/devicetree.cb M src/mainboard/intel/emeraldlake2/devicetree.cb M src/mainboard/kontron/ktqm77/devicetree.cb M src/mainboard/lenovo/l520/devicetree.cb M src/mainboard/lenovo/s230u/devicetree.cb M src/mainboard/lenovo/t420/devicetree.cb M src/mainboard/lenovo/t420s/devicetree.cb M src/mainboard/lenovo/t430/devicetree.cb M src/mainboard/lenovo/t430s/devicetree.cb M src/mainboard/lenovo/t520/devicetree.cb M src/mainboard/lenovo/t530/devicetree.cb M src/mainboard/lenovo/x131e/devicetree.cb M src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb M src/mainboard/lenovo/x220/devicetree.cb M src/mainboard/lenovo/x230/devicetree.cb M src/mainboard/msi/ms7707/devicetree.cb M src/mainboard/roda/rv11/variants/rv11/devicetree.cb M src/mainboard/roda/rv11/variants/rw11/devicetree.cb M src/mainboard/samsung/lumpy/devicetree.cb M src/mainboard/samsung/stumpy/devicetree.cb M src/mainboard/sapphire/pureplatinumh61/devicetree.cb M src/mainboard/supermicro/x9sae/devicetree.cb M src/mainboard/supermicro/x9scl/devicetree.cb M src/northbridge/intel/sandybridge/Kconfig A src/northbridge/intel/sandybridge/chipset.cb 43 files changed, 41 insertions(+), 367 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/mainboard/apple/macbookair4_2/devicetree.cb b/src/mainboard/apple/macbookair4_2/devicetree.cb index 6ea033e..df2f154 100644 --- a/src/mainboard/apple/macbookair4_2/devicetree.cb +++ b/src/mainboard/apple/macbookair4_2/devicetree.cb @@ -13,15 +13,6 @@ register "gpu_panel_power_down_delay" = "500" register "gpu_panel_power_up_delay" = "2000" register "gpu_pch_backlight" = "0x13121312" - device cpu_cluster 0 on - chip cpu/intel/model_206ax - register "acpi_c1" = "1" - register "acpi_c2" = "3" - register "acpi_c3" = "5" - device lapic 0 on end - device lapic 0xacac off end - end - end device domain 0 on chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH diff --git a/src/mainboard/asrock/b75pro3-m/devicetree.cb b/src/mainboard/asrock/b75pro3-m/devicetree.cb index 0f7d0a8..f45418f 100644 --- a/src/mainboard/asrock/b75pro3-m/devicetree.cb +++ b/src/mainboard/asrock/b75pro3-m/devicetree.cb @@ -13,15 +13,7 @@ register "gpu_panel_power_down_delay" = "0" register "gpu_panel_power_up_delay" = "0" register "gpu_pch_backlight" = "0x00000000" - device cpu_cluster 0 on - chip cpu/intel/model_206ax - register "acpi_c1" = "1" - register "acpi_c2" = "3" - register "acpi_c3" = "5" - device lapic 0 on end - device lapic 0xacac off end - end - end + device domain 0 on device pci 00.0 on subsystemid 0x1849 0x0150 diff --git a/src/mainboard/asrock/h77pro4-m/devicetree.cb b/src/mainboard/asrock/h77pro4-m/devicetree.cb index 86468c1..7d94706 100644 --- a/src/mainboard/asrock/h77pro4-m/devicetree.cb +++ b/src/mainboard/asrock/h77pro4-m/devicetree.cb @@ -1,15 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-or-later chip northbridge/intel/sandybridge - device cpu_cluster 0 on - chip cpu/intel/model_206ax - register "acpi_c1" = "1" - register "acpi_c2" = "3" - register "acpi_c3" = "5" - device lapic 0 on end - device lapic 0xacac off end - end - end device domain 0 on device pci 00.0 on # Host bridge subsystemid 0x1849 0x0100 diff --git a/src/mainboard/asus/h61-series/devicetree.cb b/src/mainboard/asus/h61-series/devicetree.cb index 32f0cd4..abed76a 100644 --- a/src/mainboard/asus/h61-series/devicetree.cb +++ b/src/mainboard/asus/h61-series/devicetree.cb @@ -1,15 +1,6 @@ ## SPDX-License-Identifier: GPL-2.0-or-later chip northbridge/intel/sandybridge - device cpu_cluster 0 on - chip cpu/intel/model_206ax - register "acpi_c1" = "1" - register "acpi_c2" = "3" - register "acpi_c3" = "5" - device lapic 0 on end - device lapic 0xacac off end - end - end device domain 0 on device pci 00.0 on end # Host bridge device pci 01.0 on end # PEG diff --git a/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb b/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb index ca09d2f..41fc4dc 100644 --- a/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb +++ b/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb @@ -1,16 +1,6 @@ ## SPDX-License-Identifier: GPL-2.0-or-later chip northbridge/intel/sandybridge - device cpu_cluster 0 on - chip cpu/intel/model_206ax - register "acpi_c1" = "1" - register "acpi_c2" = "3" - register "acpi_c3" = "5" - device lapic 0 on end - device lapic 0xacac off end - end - end - device domain 0 on subsystemid 0x1043 0x844d inherit diff --git a/src/mainboard/asus/p8x7x-series/devicetree.cb b/src/mainboard/asus/p8x7x-series/devicetree.cb index 9710118..75566d1 100644 --- a/src/mainboard/asus/p8x7x-series/devicetree.cb +++ b/src/mainboard/asus/p8x7x-series/devicetree.cb @@ -1,15 +1,6 @@ ## SPDX-License-Identifier: GPL-2.0-only chip northbridge/intel/sandybridge - device cpu_cluster 0 on - chip cpu/intel/model_206ax - register "acpi_c1" = "1" - register "acpi_c2" = "3" - register "acpi_c3" = "5" - device lapic 0 on end - device lapic 0xacac off end - end - end device domain 0 on device pci 00.0 on end # Host bridge device pci 01.0 on end # PCIEX16_1 diff --git a/src/mainboard/biostar/th61-itx/devicetree.cb b/src/mainboard/biostar/th61-itx/devicetree.cb index 35c3ae34..5999a1d 100644 --- a/src/mainboard/biostar/th61-itx/devicetree.cb +++ b/src/mainboard/biostar/th61-itx/devicetree.cb @@ -1,15 +1,6 @@ ## SPDX-License-Identifier: GPL-2.0-only chip northbridge/intel/sandybridge - device cpu_cluster 0 on - chip cpu/intel/model_206ax - register "acpi_c1" = "1" - register "acpi_c2" = "3" - register "acpi_c3" = "5" - device lapic 0 on end - device lapic 0xacac off end - end - end device domain 0 on subsystemid 0x1565 0x3108 inherit diff --git a/src/mainboard/compulab/intense_pc/devicetree.cb b/src/mainboard/compulab/intense_pc/devicetree.cb index 6979615..1ce2341 100644 --- a/src/mainboard/compulab/intense_pc/devicetree.cb +++ b/src/mainboard/compulab/intense_pc/devicetree.cb @@ -6,15 +6,6 @@ register "gpu_dp_c_hotplug" = "4" register "gpu_dp_d_hotplug" = "4" - device cpu_cluster 0 on - chip cpu/intel/model_206ax # FIXME: check all registers - register "acpi_c1" = "1" - register "acpi_c2" = "3" - register "acpi_c3" = "5" - device lapic 0 on end - device lapic 0xacac off end - end - end device domain 0 on device pci 00.0 on # Host bridge subsystemid 0x8086 0x2010 diff --git a/src/mainboard/dell/snb_ivb_workstations/variants/baseboard/devicetree.cb b/src/mainboard/dell/snb_ivb_workstations/variants/baseboard/devicetree.cb index e614f1e..8f94378 100644 --- a/src/mainboard/dell/snb_ivb_workstations/variants/baseboard/devicetree.cb +++ b/src/mainboard/dell/snb_ivb_workstations/variants/baseboard/devicetree.cb @@ -1,9 +1,6 @@ chip northbridge/intel/sandybridge device cpu_cluster 0 on chip cpu/intel/model_206ax - register "acpi_c1" = "1" - register "acpi_c2" = "3" - register "acpi_c3" = "5" register "tcc_offset" = "5" # TCC of 95C device lapic 0 on end device lapic 0xacac off end diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb index 7ca9a8b..d7263c8 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb +++ b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb @@ -1,16 +1,4 @@ chip northbridge/intel/sandybridge - - device cpu_cluster 0 on - chip cpu/intel/model_206ax - register "acpi_c1" = "1" - register "acpi_c2" = "3" - register "acpi_c3" = "5" - # Magic APIC ID to locate this chip - device lapic 0 on end - device lapic 0xacac off end - end - end - device domain 0 on subsystemid 0x1458 0x5000 inherit device pci 00.0 on # Host bridge diff --git a/src/mainboard/gigabyte/ga-h61m-series/devicetree.cb b/src/mainboard/gigabyte/ga-h61m-series/devicetree.cb index 3f07202..299c134 100644 --- a/src/mainboard/gigabyte/ga-h61m-series/devicetree.cb +++ b/src/mainboard/gigabyte/ga-h61m-series/devicetree.cb @@ -1,15 +1,6 @@ ## SPDX-License-Identifier: GPL-2.0-only chip northbridge/intel/sandybridge - device cpu_cluster 0 on - chip cpu/intel/model_206ax - register "acpi_c1" = "1" - register "acpi_c2" = "3" - register "acpi_c3" = "5" - device lapic 0 on end - device lapic 0xacac off end - end - end device domain 0 on subsystemid 0x1458 0x5000 inherit diff --git a/src/mainboard/google/butterfly/devicetree.cb b/src/mainboard/google/butterfly/devicetree.cb index c79526e..5ff7f9d 100644 --- a/src/mainboard/google/butterfly/devicetree.cb +++ b/src/mainboard/google/butterfly/devicetree.cb @@ -20,18 +20,6 @@ register "max_mem_clock_mhz" = "666" # DDR3-1333 - device cpu_cluster 0 on - chip cpu/intel/model_206ax - # Magic APIC ID to locate this chip - device lapic 0 on end - device lapic 0xacac off end - - register "acpi_c1" = "1" # ACPI(C1) = MWAIT(C1) - register "acpi_c2" = "3" # ACPI(C2) = MWAIT(C3) - register "acpi_c3" = "5" # ACPI(C3) = MWAIT(C7) - end - end - device domain 0 on device pci 00.0 on end # host bridge device pci 01.0 off end # PCIe Bridge for discrete graphics diff --git a/src/mainboard/google/link/devicetree.cb b/src/mainboard/google/link/devicetree.cb index 49c3476..4116188 100644 --- a/src/mainboard/google/link/devicetree.cb +++ b/src/mainboard/google/link/devicetree.cb @@ -19,18 +19,6 @@ register "max_mem_clock_mhz" = "666" - device cpu_cluster 0 on - chip cpu/intel/model_206ax - # Magic APIC ID to locate this chip - device lapic 0 on end - device lapic 0xacac off end - - register "acpi_c1" = "1" # ACPI(C1) = MWAIT(C1) - register "acpi_c2" = "3" # ACPI(C2) = MWAIT(C3) - register "acpi_c3" = "5" # ACPI(C3) = MWAIT(C7) - end - end - device domain 0 on subsystemid 0x1ae0 0xc000 inherit device pci 00.0 on end # host bridge diff --git a/src/mainboard/google/parrot/devicetree.cb b/src/mainboard/google/parrot/devicetree.cb index 6850cf2..7c1cc81 100644 --- a/src/mainboard/google/parrot/devicetree.cb +++ b/src/mainboard/google/parrot/devicetree.cb @@ -19,18 +19,6 @@ register "max_mem_clock_mhz" = "666" - device cpu_cluster 0 on - chip cpu/intel/model_206ax - # Magic APIC ID to locate this chip - device lapic 0 on end - device lapic 0xacac off end - - register "acpi_c1" = "1" # ACPI(C1) = MWAIT(C1) - register "acpi_c2" = "3" # ACPI(C2) = MWAIT(C3) - register "acpi_c3" = "5" # ACPI(C3) = MWAIT(C7) - end - end - device domain 0 on device pci 00.0 on end # host bridge device pci 02.0 on end # vga controller diff --git a/src/mainboard/google/stout/devicetree.cb b/src/mainboard/google/stout/devicetree.cb index b38adaf..77f58c2 100644 --- a/src/mainboard/google/stout/devicetree.cb +++ b/src/mainboard/google/stout/devicetree.cb @@ -26,10 +26,6 @@ device lapic 0xacac off end register "tcc_offset" = "5" # TCC of 95C - - register "acpi_c1" = "1" # ACPI(C1) = MWAIT(C1) - register "acpi_c2" = "3" # ACPI(C2) = MWAIT(C3) - register "acpi_c3" = "5" # ACPI(C3) = MWAIT(C7) end end diff --git a/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb b/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb index 98e48ef..ce100b4 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb +++ b/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb @@ -6,16 +6,6 @@ register "gpu_dp_c_hotplug" = "0" register "gpu_dp_d_hotplug" = "0" - device cpu_cluster 0 on - chip cpu/intel/model_206ax - register "acpi_c1" = "1" - register "acpi_c2" = "3" - register "acpi_c3" = "5" - device lapic 0 on end - device lapic 0xacac off end - end - end - device domain 0 on subsystemid 0x103c 0x1495 inherit diff --git a/src/mainboard/hp/snb_ivb_laptops/devicetree.cb b/src/mainboard/hp/snb_ivb_laptops/devicetree.cb index 2bfbacd..a4d723f 100644 --- a/src/mainboard/hp/snb_ivb_laptops/devicetree.cb +++ b/src/mainboard/hp/snb_ivb_laptops/devicetree.cb @@ -15,15 +15,7 @@ register "gpu_panel_power_down_delay" = "230" register "gpu_panel_power_up_delay" = "300" register "gpu_pch_backlight" = "0x02880288" - device cpu_cluster 0 on - chip cpu/intel/model_206ax - register "acpi_c1" = "1" - register "acpi_c2" = "3" - register "acpi_c3" = "5" - device lapic 0 on end - device lapic 0xacac off end - end - end + device domain 0 on device pci 00.0 on end # Host bridge diff --git a/src/mainboard/hp/z220_series/devicetree.cb b/src/mainboard/hp/z220_series/devicetree.cb index bcacf71..6794b62 100644 --- a/src/mainboard/hp/z220_series/devicetree.cb +++ b/src/mainboard/hp/z220_series/devicetree.cb @@ -6,16 +6,6 @@ register "gpu_dp_c_hotplug" = "0" register "gpu_dp_d_hotplug" = "0" - device cpu_cluster 0 on - chip cpu/intel/model_206ax - register "acpi_c1" = "1" - register "acpi_c2" = "3" - register "acpi_c3" = "5" - device lapic 0 on end - device lapic 0xacac off end - end - end - device domain 0 on subsystemid 0x103c 0x1791 inherit diff --git a/src/mainboard/intel/dcp847ske/devicetree.cb b/src/mainboard/intel/dcp847ske/devicetree.cb index f7821d0..5400af7 100644 --- a/src/mainboard/intel/dcp847ske/devicetree.cb +++ b/src/mainboard/intel/dcp847ske/devicetree.cb @@ -11,17 +11,6 @@ # Enable DVI Hotplug with 6ms pulse register "gpu_dp_b_hotplug" = "0x06" - device cpu_cluster 0 on - chip cpu/intel/model_206ax - # Magic APIC ID to locate this chip - device lapic 0 on end - device lapic 0xacac off end - - register "acpi_c1" = "1" - register "acpi_c2" = "3" - register "acpi_c3" = "5" - end - end device domain 0 on device pci 00.0 on end # Host bridge device pci 01.0 off end # PCIe Bridge for discrete graphics diff --git a/src/mainboard/intel/emeraldlake2/devicetree.cb b/src/mainboard/intel/emeraldlake2/devicetree.cb index 170dbaa..9255848 100644 --- a/src/mainboard/intel/emeraldlake2/devicetree.cb +++ b/src/mainboard/intel/emeraldlake2/devicetree.cb @@ -19,7 +19,6 @@ register "acpi_c1" = "3" # ACPI(C1) = MWAIT(C3) register "acpi_c2" = "4" # ACPI(C2) = MWAIT(C6) - register "acpi_c3" = "5" # ACPI(C3) = MWAIT(C7) end end diff --git a/src/mainboard/kontron/ktqm77/devicetree.cb b/src/mainboard/kontron/ktqm77/devicetree.cb index 31bee5d..1bbbbfc 100644 --- a/src/mainboard/kontron/ktqm77/devicetree.cb +++ b/src/mainboard/kontron/ktqm77/devicetree.cb @@ -8,7 +8,6 @@ device lapic 0 on end device lapic 0xacac off end - register "acpi_c1" = "1" # ACPI(C1) = MWAIT(C1) register "acpi_c2" = "4" # ACPI(C2) = MWAIT(C3) register "acpi_c3" = "0" # ACPI(C3) = MWAIT(C7) end diff --git a/src/mainboard/lenovo/l520/devicetree.cb b/src/mainboard/lenovo/l520/devicetree.cb index 6c2dabe..9e56e79 100644 --- a/src/mainboard/lenovo/l520/devicetree.cb +++ b/src/mainboard/lenovo/l520/devicetree.cb @@ -12,16 +12,6 @@ register "gpu_panel_power_up_delay" = "0" register "gpu_pch_backlight" = "0x00000000" - device cpu_cluster 0 on - chip cpu/intel/model_206ax - register "acpi_c1" = "1" - register "acpi_c2" = "3" - register "acpi_c3" = "5" - device lapic 0 on end - device lapic 0xacac off end - end - end - device domain 0 on subsystemid 0x17aa 0x21dd inherit diff --git a/src/mainboard/lenovo/s230u/devicetree.cb b/src/mainboard/lenovo/s230u/devicetree.cb index f7d65ca..16e1004 100644 --- a/src/mainboard/lenovo/s230u/devicetree.cb +++ b/src/mainboard/lenovo/s230u/devicetree.cb @@ -11,15 +11,7 @@ register "gpu_panel_power_down_delay" = "500" register "gpu_panel_power_up_delay" = "600" register "gpu_pch_backlight" = "0x041e041e" - device cpu_cluster 0 on - chip cpu/intel/model_206ax - register "acpi_c1" = "1" - register "acpi_c2" = "3" - register "acpi_c3" = "5" - device lapic 0 on end - device lapic 0xacac off end - end - end + device domain 0 on subsystemid 0x17aa 0x2205 inherit diff --git a/src/mainboard/lenovo/t420/devicetree.cb b/src/mainboard/lenovo/t420/devicetree.cb index c934f5f..b764a83 100644 --- a/src/mainboard/lenovo/t420/devicetree.cb +++ b/src/mainboard/lenovo/t420/devicetree.cb @@ -15,18 +15,6 @@ register "gpu_cpu_backlight" = "0x1155" register "gpu_pch_backlight" = "0x06100610" - device cpu_cluster 0 on - chip cpu/intel/model_206ax - # Magic APIC ID to locate this chip - device lapic 0 on end - device lapic 0xacac off end - - register "acpi_c1" = "1" # ACPI(C1) = MWAIT(C1) - register "acpi_c2" = "3" # ACPI(C2) = MWAIT(C3) - register "acpi_c3" = "5" # ACPI(C3) = MWAIT(C7) - end - end - device domain 0 on subsystemid 0x17aa 0x21ce inherit diff --git a/src/mainboard/lenovo/t420s/devicetree.cb b/src/mainboard/lenovo/t420s/devicetree.cb index 1d6adaf..92c9085 100644 --- a/src/mainboard/lenovo/t420s/devicetree.cb +++ b/src/mainboard/lenovo/t420s/devicetree.cb @@ -15,18 +15,6 @@ register "gpu_cpu_backlight" = "0x1155" register "gpu_pch_backlight" = "0x06100610" - device cpu_cluster 0 on - chip cpu/intel/model_206ax - # Magic APIC ID to locate this chip - device lapic 0 on end - device lapic 0xacac off end - - register "acpi_c1" = "1" # ACPI(C1) = MWAIT(C1) - register "acpi_c2" = "3" # ACPI(C2) = MWAIT(C3) - register "acpi_c3" = "5" # ACPI(C3) = MWAIT(C7) - end - end - device domain 0 on subsystemid 0x17aa 0x21d2 inherit diff --git a/src/mainboard/lenovo/t430/devicetree.cb b/src/mainboard/lenovo/t430/devicetree.cb index 141faa9..8b15c84 100644 --- a/src/mainboard/lenovo/t430/devicetree.cb +++ b/src/mainboard/lenovo/t430/devicetree.cb @@ -14,16 +14,6 @@ register "gpu_cpu_backlight" = "0x1155" register "gpu_pch_backlight" = "0x11551155" - device cpu_cluster 0 on - chip cpu/intel/model_206ax # FIXME: check all registers - register "acpi_c1" = "1" - register "acpi_c2" = "3" - register "acpi_c3" = "5" - device lapic 0 on end - device lapic 0xacac off end - end - end - device domain 0 on subsystemid 0x17aa 0x21f3 inherit diff --git a/src/mainboard/lenovo/t430s/devicetree.cb b/src/mainboard/lenovo/t430s/devicetree.cb index 739d01d..9148892 100644 --- a/src/mainboard/lenovo/t430s/devicetree.cb +++ b/src/mainboard/lenovo/t430s/devicetree.cb @@ -14,18 +14,6 @@ register "gpu_cpu_backlight" = "0x1155" register "gpu_pch_backlight" = "0x11551155" - device cpu_cluster 0 on - chip cpu/intel/model_206ax - # Magic APIC ID to locate this chip - device lapic 0 on end - device lapic 0xacac off end - - register "acpi_c1" = "1" # ACPI(C1) = MWAIT(C1) - register "acpi_c2" = "3" # ACPI(C2) = MWAIT(C3) - register "acpi_c3" = "5" # ACPI(C3) = MWAIT(C7) - end - end - device domain 0 on subsystemid 0x17aa 0x21fb inherit diff --git a/src/mainboard/lenovo/t520/devicetree.cb b/src/mainboard/lenovo/t520/devicetree.cb index 9c75231..9588af2 100644 --- a/src/mainboard/lenovo/t520/devicetree.cb +++ b/src/mainboard/lenovo/t520/devicetree.cb @@ -15,18 +15,6 @@ register "gpu_cpu_backlight" = "0x1155" register "gpu_pch_backlight" = "0x06100610" - device cpu_cluster 0 on - chip cpu/intel/model_206ax - # Magic APIC ID to locate this chip - device lapic 0 on end - device lapic 0xacac off end - - register "acpi_c1" = "1" # ACPI(C1) = MWAIT(C1) - register "acpi_c2" = "3" # ACPI(C2) = MWAIT(C3) - register "acpi_c3" = "5" # ACPI(C3) = MWAIT(C7) - end - end - device domain 0 on subsystemid 0x17aa 0x21cf inherit diff --git a/src/mainboard/lenovo/t530/devicetree.cb b/src/mainboard/lenovo/t530/devicetree.cb index 5cfa207..a274a67 100644 --- a/src/mainboard/lenovo/t530/devicetree.cb +++ b/src/mainboard/lenovo/t530/devicetree.cb @@ -15,18 +15,6 @@ register "gpu_cpu_backlight" = "0x1155" register "gpu_pch_backlight" = "0x11551155" - device cpu_cluster 0 on - chip cpu/intel/model_206ax - # Magic APIC ID to locate this chip - device lapic 0 on end - device lapic 0xacac off end - - register "acpi_c1" = "1" # ACPI(C1) = MWAIT(C1) - register "acpi_c2" = "3" # ACPI(C2) = MWAIT(C3) - register "acpi_c3" = "5" # ACPI(C3) = MWAIT(C7) - end - end - device domain 0 on subsystemid 0x17aa 0x21f6 inherit diff --git a/src/mainboard/lenovo/x131e/devicetree.cb b/src/mainboard/lenovo/x131e/devicetree.cb index f28212e..a0de163 100644 --- a/src/mainboard/lenovo/x131e/devicetree.cb +++ b/src/mainboard/lenovo/x131e/devicetree.cb @@ -14,18 +14,6 @@ register "gpu_cpu_backlight" = "0x1155" register "gpu_pch_backlight" = "0x11551155" - device cpu_cluster 0 on - chip cpu/intel/model_206ax - # Magic APIC ID to locate this chip - device lapic 0 on end - device lapic 0xacac off end - - register "acpi_c1" = "1" - register "acpi_c2" = "3" - register "acpi_c3" = "5" - end - end - device domain 0 on subsystemid 0x17aa 0x21fe inherit diff --git a/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb b/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb index cbf1141..0c69353 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb +++ b/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb @@ -12,18 +12,6 @@ register "gpu_panel_power_up_delay" = "300" register "gpu_pch_backlight" = "0x11551155" - device cpu_cluster 0 on - chip cpu/intel/model_206ax - # Magic APIC ID to locate this chip - device lapic 0 on end - device lapic 0xacac off end - - register "acpi_c1" = "1" # ACPI(C1) = MWAIT(C1) - register "acpi_c2" = "3" # ACPI(C2) = MWAIT(C3) - register "acpi_c3" = "5" # ACPI(C3) = MWAIT(C7) - end - end - device domain 0 on subsystemid 0x17aa 0x21f9 inherit diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb index 923c88b..46459c5 100644 --- a/src/mainboard/lenovo/x220/devicetree.cb +++ b/src/mainboard/lenovo/x220/devicetree.cb @@ -15,18 +15,6 @@ register "gpu_cpu_backlight" = "0x1155" register "gpu_pch_backlight" = "0x06100610" - device cpu_cluster 0 on - chip cpu/intel/model_206ax - # Magic APIC ID to locate this chip - device lapic 0 on end - device lapic 0xacac off end - - register "acpi_c1" = "1" # ACPI(C1) = MWAIT(C1) - register "acpi_c2" = "3" # ACPI(C2) = MWAIT(C3) - register "acpi_c3" = "5" # ACPI(C3) = MWAIT(C7) - end - end - device domain 0 on subsystemid 0x17aa 0x21db inherit diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb index 30a7916..5c1c124 100644 --- a/src/mainboard/lenovo/x230/devicetree.cb +++ b/src/mainboard/lenovo/x230/devicetree.cb @@ -15,18 +15,6 @@ register "gpu_cpu_backlight" = "0x1155" register "gpu_pch_backlight" = "0x11551155" - device cpu_cluster 0 on - chip cpu/intel/model_206ax - # Magic APIC ID to locate this chip - device lapic 0 on end - device lapic 0xacac off end - - register "acpi_c1" = "1" # ACPI(C1) = MWAIT(C1) - register "acpi_c2" = "3" # ACPI(C2) = MWAIT(C3) - register "acpi_c3" = "5" # ACPI(C3) = MWAIT(C7) - end - end - device domain 0 on subsystemid 0x17aa 0x21fa inherit diff --git a/src/mainboard/msi/ms7707/devicetree.cb b/src/mainboard/msi/ms7707/devicetree.cb index 8e5df58..e0fbc1a 100644 --- a/src/mainboard/msi/ms7707/devicetree.cb +++ b/src/mainboard/msi/ms7707/devicetree.cb @@ -1,13 +1,4 @@ chip northbridge/intel/sandybridge - device cpu_cluster 0 on - chip cpu/intel/model_206ax - register "acpi_c1" = "1" - register "acpi_c2" = "3" - register "acpi_c3" = "5" - device lapic 0 on end - device lapic 0xacac off end - end - end device domain 0 on subsystemid 0x1462 0x7707 inherit diff --git a/src/mainboard/roda/rv11/variants/rv11/devicetree.cb b/src/mainboard/roda/rv11/variants/rv11/devicetree.cb index 6cb77e3..7cb6812 100644 --- a/src/mainboard/roda/rv11/variants/rv11/devicetree.cb +++ b/src/mainboard/roda/rv11/variants/rv11/devicetree.cb @@ -23,7 +23,6 @@ device lapic 0 on end device lapic 0xacac off end - register "acpi_c1" = "1" # ACPI(C1) = MWAIT(C1) register "acpi_c2" = "4" # ACPI(C2) = MWAIT(C6) register "acpi_c3" = "0" end diff --git a/src/mainboard/roda/rv11/variants/rw11/devicetree.cb b/src/mainboard/roda/rv11/variants/rw11/devicetree.cb index 2291f61..96a8ce8 100644 --- a/src/mainboard/roda/rv11/variants/rw11/devicetree.cb +++ b/src/mainboard/roda/rv11/variants/rw11/devicetree.cb @@ -23,7 +23,6 @@ device lapic 0 on end device lapic 0xacac off end - register "acpi_c1" = "1" # ACPI(C1) = MWAIT(C1) register "acpi_c2" = "4" # ACPI(C2) = MWAIT(C6) register "acpi_c3" = "0" end diff --git a/src/mainboard/samsung/lumpy/devicetree.cb b/src/mainboard/samsung/lumpy/devicetree.cb index ff7f362..4049709 100644 --- a/src/mainboard/samsung/lumpy/devicetree.cb +++ b/src/mainboard/samsung/lumpy/devicetree.cb @@ -19,18 +19,6 @@ register "max_mem_clock_mhz" = "666" - device cpu_cluster 0 on - chip cpu/intel/model_206ax - # Magic APIC ID to locate this chip - device lapic 0 on end - device lapic 0xacac off end - - register "acpi_c1" = "1" # ACPI(C1) = MWAIT(C1) - register "acpi_c2" = "3" # ACPI(C2) = MWAIT(C3) - register "acpi_c3" = "5" # ACPI(C3) = MWAIT(C7) - end - end - device domain 0 on subsystemid 0x1ae0 0xc000 inherit device pci 00.0 on end # host bridge diff --git a/src/mainboard/samsung/stumpy/devicetree.cb b/src/mainboard/samsung/stumpy/devicetree.cb index 90ed429..ea164c4 100644 --- a/src/mainboard/samsung/stumpy/devicetree.cb +++ b/src/mainboard/samsung/stumpy/devicetree.cb @@ -19,7 +19,6 @@ register "acpi_c1" = "3" # ACPI(C1) = MWAIT(C3) register "acpi_c2" = "4" # ACPI(C2) = MWAIT(C6) - register "acpi_c3" = "5" # ACPI(C3) = MWAIT(C7) end end diff --git a/src/mainboard/sapphire/pureplatinumh61/devicetree.cb b/src/mainboard/sapphire/pureplatinumh61/devicetree.cb index d5f6fda..b1beae0 100644 --- a/src/mainboard/sapphire/pureplatinumh61/devicetree.cb +++ b/src/mainboard/sapphire/pureplatinumh61/devicetree.cb @@ -1,15 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-or-later chip northbridge/intel/sandybridge - device cpu_cluster 0 on - chip cpu/intel/model_206ax - register "acpi_c1" = "1" - register "acpi_c2" = "3" - register "acpi_c3" = "5" - device lapic 0 on end - device lapic 0xacac off end - end - end device domain 0 on chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "gen1_dec" = "0x000c0291" diff --git a/src/mainboard/supermicro/x9sae/devicetree.cb b/src/mainboard/supermicro/x9sae/devicetree.cb index 05a187e..ed011c1 100644 --- a/src/mainboard/supermicro/x9sae/devicetree.cb +++ b/src/mainboard/supermicro/x9sae/devicetree.cb @@ -6,15 +6,7 @@ register "gpu_dp_c_hotplug" = "4" register "gpu_dp_d_hotplug" = "4" register "gpu_panel_power_cycle_delay" = "4" - device cpu_cluster 0 on - chip cpu/intel/model_206ax - register "acpi_c1" = "1" - register "acpi_c2" = "3" - register "acpi_c3" = "5" - device lapic 0 on end - device lapic 0xacac off end - end - end + device domain 0 on subsystemid 0x15d9 0x0644 inherit diff --git a/src/mainboard/supermicro/x9scl/devicetree.cb b/src/mainboard/supermicro/x9scl/devicetree.cb index 284d8f3..b0f3534 100644 --- a/src/mainboard/supermicro/x9scl/devicetree.cb +++ b/src/mainboard/supermicro/x9scl/devicetree.cb @@ -1,13 +1,4 @@ chip northbridge/intel/sandybridge - device cpu_cluster 0 on - chip cpu/intel/model_206ax # FIXME: check all registers - register "acpi_c1" = "1" - register "acpi_c2" = "3" - register "acpi_c3" = "5" - device lapic 0 on end - device lapic 0xacac off end - end - end device domain 0 on subsystemid 0x15d9 0x0624 inherit device pci 00.0 on end # Host bridge diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index 551714a..bbe8ac4 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -17,6 +17,9 @@ select NO_DDR2 select USE_DDR3 +config CHIPSET_DEVICETREE + default "northbridge/intel/sandybridge/chipset.cb" + config SANDYBRIDGE_VBOOT_IN_ROMSTAGE bool default n diff --git a/src/northbridge/intel/sandybridge/chipset.cb b/src/northbridge/intel/sandybridge/chipset.cb new file mode 100644 index 0000000..ae02a5b --- /dev/null +++ b/src/northbridge/intel/sandybridge/chipset.cb @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: GPL-2.0-only + +chip northbridge/intel/sandybridge + device cpu_cluster 0 on + chip cpu/intel/model_206ax + # Magic APIC ID to locate this chip + device lapic 0 on end + device lapic 0xacac off end + + register "acpi_c1" = "1" # ACPI(C1) = MWAIT(C1) + register "acpi_c2" = "3" # ACPI(C2) = MWAIT(C3) + register "acpi_c3" = "5" # ACPI(C3) = MWAIT(C7) + end + end + + device domain 0 on + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/56912 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c5b6f25b779e28b6719cf70455ff0f1a916ad87 Gerrit-Change-Number: 56912 Gerrit-PatchSet: 8 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/prodrive/atlas: Enable GPP_B14 buzzer support
by Lean Sheng Tan (Code Review) 30 Nov '22

30 Nov '22

Attention is currently required from: Christian Walter, Maximilian Brune, Lean Sheng Tan. Hello build bot (Jenkins), Christian Walter, Maximilian Brune, Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/67553 to look at the new patch set (#12). Change subject: mb/prodrive/atlas: Enable GPP_B14 buzzer support ...................................................................... mb/prodrive/atlas: Enable GPP_B14 buzzer support Per Intel doc 621483, 26.1.1 - NMI_STS_CNT, 8254 timer is required for Speaker Data output (buzzer) at GPP_B14 NF1, as it is using 8254 timer counter 2 output. However when 8254 timer is used, S0ix will not work as 8254 has to be gated instead. For further info on s0ix requirements, refer to Intel doc 610002 (Modern Standby Unified Checklist). This CL also disable s0ix because it is not required by the platform. Signed-off-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Change-Id: Ib5e7787a47509ed09818d8515d21a80196fb1ec6 --- M src/mainboard/prodrive/atlas/Kconfig M src/mainboard/prodrive/atlas/devicetree.cb 2 files changed, 32 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/67553/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/67553 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib5e7787a47509ed09818d8515d21a80196fb1ec6 Gerrit-Change-Number: 67553 Gerrit-PatchSet: 12 Gerrit-Owner: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/intel/meteorlake: Rename method is_eom to is_manufacturing_mode
by Martin L Roth (Code Review) 30 Nov '22

30 Nov '22

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69698 ) Change subject: soc/intel/meteorlake: Rename method is_eom to is_manufacturing_mode ...................................................................... soc/intel/meteorlake: Rename method is_eom to is_manufacturing_mode BUG=none TEST=Build and boot to google/rex. Excerpt from google/rex coreboot log: [DEBUG] ME: Manufacturing Mode : YES Signed-off-by: Kapil Porwal <kapilporwal(a)google.com> Change-Id: I8d2de3365126ba618c987c412c4e9784012f9e0b Reviewed-on: https://review.coreboot.org/c/coreboot/+/69698 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/meteorlake/me.c 1 file changed, 30 insertions(+), 10 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved diff --git a/src/soc/intel/meteorlake/me.c b/src/soc/intel/meteorlake/me.c index f746fe0..4f2bc53 100644 --- a/src/soc/intel/meteorlake/me.c +++ b/src/soc/intel/meteorlake/me.c @@ -76,16 +76,15 @@ } __packed fields; }; - -/* - * Manufacturing mode is disabled if the descriptor is locked, fuses - * are programmed and manufacturing variables are locked. - * The function returns true if manufacturing mode is disabled otherwise false. - */ -static bool is_eom(union me_hfsts1 hfsts1, union me_hfsts6 hfsts6) +static bool is_manufacturing_mode(union me_hfsts1 hfsts1, union me_hfsts6 hfsts6) { - return (hfsts1.fields.mfg_mode == 0) && (hfsts6.fields.manuf_lock == 1) && - (hfsts6.fields.fpf_soc_lock == 1); + /* + * ME manufacturing mode is disabled if the descriptor is locked, fuses + * are programmed and manufacturing variables are locked. + */ + return !((hfsts1.fields.mfg_mode == 0) && + (hfsts6.fields.fpf_soc_lock == 1) && + (hfsts6.fields.manuf_lock == 1)); } static void dump_me_status(void *unused) @@ -96,6 +95,7 @@ union me_hfsts4 hfsts4; union me_hfsts5 hfsts5; union me_hfsts6 hfsts6; + bool manufacturing_mode; if (!is_cse_enabled()) return; @@ -114,8 +114,9 @@ printk(BIOS_DEBUG, "ME: HFSTS5 : 0x%08X\n", hfsts5.data); printk(BIOS_DEBUG, "ME: HFSTS6 : 0x%08X\n", hfsts6.data); + manufacturing_mode = is_manufacturing_mode(hfsts1, hfsts6); printk(BIOS_DEBUG, "ME: Manufacturing Mode : %s\n", - is_eom(hfsts1, hfsts6) ? "NO" : "YES"); + manufacturing_mode ? "YES" : "NO"); /* * The SPI Protection Mode bit reflects SPI descriptor -- To view, visit https://review.coreboot.org/c/coreboot/+/69698 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d2de3365126ba618c987c412c4e9784012f9e0b Gerrit-Change-Number: 69698 Gerrit-PatchSet: 6 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: merged

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