coreboot-gerrit November 2022

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[master]: soc/intel/cmn/block/{pcie/rtd3,usb4}: Use helper functions for _DSD
by Subrata Banik (Code Review) 30 Nov '22

30 Nov '22

Attention is currently required from: Eran Mitrani, Kapil Porwal, Nick Vaccaro. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70065 ) Change subject: soc/intel/cmn/block/{pcie/rtd3,usb4}: Use helper functions for _DSD ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/70065 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib57dea9b16e4590ca2d75ac1512fdaf773ec50f6 Gerrit-Change-Number: 70065 Gerrit-PatchSet: 6 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Wed, 30 Nov 2022 18:51:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: acpi: Helper functions to add certain _DSD properties
by Subrata Banik (Code Review) 30 Nov '22

30 Nov '22

Attention is currently required from: Lance Zhao, Tarun Tuli, Kapil Porwal, Tim Wawrzynczak. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70063 ) Change subject: acpi: Helper functions to add certain _DSD properties ...................................................................... Patch Set 7: (1 comment) File src/acpi/device.c: https://review.coreboot.org/c/coreboot/+/70063/comment/c7cfe8ec_fec920b9 PS7, Line 1203: /* : * Below properties are defined at : * https://docs.microsoft.com/en-us/windows-hardware/drivers/pci/dsd-for-pcie-… : */ : #define ACPI_DSD_EXTERNAL_FACING_PORT_UUID "EFCC06CC-73AC-4BC3-BFF0-76143807C389" : #define ACPI_DSD_EXTERNAL_FACING_PORT_NAME "ExternalFacingPort" : : #define ACPI_DSD_HOTPLUG_IN_D3_UUID "6211E2C0-58A3-4AF3-90E1-927A4E0C55A4" : #define ACPI_DSD_HOTPLUG_IN_D3_NAME "HotPlugSupportInD3" : : /* ID for the DmaProperty _DSD */ : #define ACPI_DSD_DMA_PROPERTY_UUID "70D24161-6DD5-4C9E-8070-705531292865" : #define ACPI_DSD_DMA_PROPERTY_NAME "DmaProperty" : : /* : * Below properties are defined at : * https://docs.microsoft.com/en-us/windows-hardware/design/component-guidelin… : */ : #define ACPI_DSD_STORAGE_D3_UUID "5025030F-842F-4AB4-A561-99A5189762D0" : #define ACPI_DSD_STORAGE_D3_NAME "StorageD3Enable" i would have move all these macros at the startng of the file -- To view, visit https://review.coreboot.org/c/coreboot/+/70063 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5bb432dd4e8f320d2c0d7f378dc2d7b3a770b541 Gerrit-Change-Number: 70063 Gerrit-PatchSet: 7 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Comment-Date: Wed, 30 Nov 2022 18:50:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in coreboot[master]: mb/amd/birman/gpio: Configure birman GPIOs
by Fred Reitberger (Code Review) 30 Nov '22

30 Nov '22

Fred Reitberger has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69411 ) Change subject: mb/amd/birman/gpio: Configure birman GPIOs ...................................................................... mb/amd/birman/gpio: Configure birman GPIOs Configure birman GPIOs per schematic 105-D67000-00B v0.7 Signed-off-by: Fred Reitberger <reitbergerfred(a)gmail.com> Change-Id: I5459efb38431e568e25405c440b5b9cf1354f02f Reviewed-on: https://review.coreboot.org/c/coreboot/+/69411 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/mainboard/amd/birman/early_gpio.c M src/mainboard/amd/birman/gpio.c 2 files changed, 249 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/mainboard/amd/birman/early_gpio.c b/src/mainboard/amd/birman/early_gpio.c index bcdeea7..89f7ef9 100644 --- a/src/mainboard/amd/birman/early_gpio.c +++ b/src/mainboard/amd/birman/early_gpio.c @@ -3,11 +3,69 @@ #include <soc/gpio.h> #include "gpio.h" -/* TODO: Update for birman */ - /* GPIO pins used by coreboot should be initialized in bootblock */ static const struct soc_amd_gpio gpio_set_stage_reset[] = { + /* TPM CS */ + PAD_NF(GPIO_29, SPI_TPM_CS_L, PULL_NONE), + /* ESPI_CS_L */ + PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), + /* ESPI_SOC_CLK */ + PAD_NF(GPIO_77, SPI1_CLK, PULL_NONE), + /* ESPI_DATA0 */ + PAD_NF(GPIO_81, SPI1_DAT0, PULL_NONE), + /* ESPI_DATA1 */ + PAD_NF(GPIO_80, SPI1_DAT1, PULL_NONE), + /* ESPI_DATA2 */ + PAD_NF(GPIO_68, SPI1_DAT2, PULL_NONE), + /* ESPI_DATA3 */ + PAD_NF(GPIO_69, SPI1_DAT3, PULL_NONE), + /* ESPI_ALERT_L */ + PAD_NF(GPIO_22, ESPI_ALERT_D1, PULL_NONE), + /* TPM IRQ */ + PAD_SCI(GPIO_130, PULL_UP, EDGE_LOW), + /* SPI_ROM_REQ */ + PAD_NF(GPIO_67, SPI_ROM_REQ, PULL_NONE), + /* SPI_ROM_GNT */ + PAD_NF(GPIO_76, SPI_ROM_GNT, PULL_NONE), + /* KBRST_L */ + PAD_NF(GPIO_21, KBRST_L, PULL_NONE), + + /* Deassert PCIe Reset lines */ + /* PCIE_RST0_L */ + PAD_NFO(GPIO_26, PCIE_RST0_L, HIGH), + /* PCIE_RST1_L */ + PAD_NFO(GPIO_27, PCIE_RST1_L, HIGH), + + /* Enable UART 2 */ + /* UART2_RXD */ + PAD_NF(GPIO_136, UART2_RXD, PULL_NONE), + /* UART2_TXD */ + PAD_NF(GPIO_138, UART2_TXD, PULL_NONE), + /* Enable UART 0 */ + /* UART0_RXD */ + PAD_NF(GPIO_141, UART0_RXD, PULL_NONE), + /* UART0_TXD */ + PAD_NF(GPIO_143, UART0_TXD, PULL_NONE), + /* FANOUT0 */ + PAD_NF(GPIO_85, FANOUT0, PULL_NONE), + + /* I2C0 SCL */ + PAD_NF(GPIO_145, I2C0_SCL, PULL_NONE), + /* I2C0 SDA */ + PAD_NF(GPIO_146, I2C0_SDA, PULL_NONE), + /* I2C1 SCL */ + PAD_NF(GPIO_147, I2C1_SCL, PULL_NONE), + /* I2C1 SDA */ + PAD_NF(GPIO_148, I2C1_SDA, PULL_NONE), + /* I2C2_SCL */ + PAD_NF(GPIO_113, I2C2_SCL, PULL_NONE), + /* I2C2_SDA */ + PAD_NF(GPIO_114, I2C2_SDA, PULL_NONE), + /* I2C3_SCL */ + PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), + /* I2C3_SDA */ + PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), }; void mainboard_program_early_gpios(void) diff --git a/src/mainboard/amd/birman/gpio.c b/src/mainboard/amd/birman/gpio.c index 583b1d1..50cf9db 100644 --- a/src/mainboard/amd/birman/gpio.c +++ b/src/mainboard/amd/birman/gpio.c @@ -3,15 +3,186 @@ #include <soc/gpio.h> #include "gpio.h" -/* TODO: Update for birman */ - /* * As a rule of thumb, GPIO pins used by coreboot should be initialized at * bootblock while GPIO pins used only by the OS should be initialized at * ramstage. */ static const struct soc_amd_gpio gpio_set_stage_ram[] = { - + /* PWR_BTN_L */ + PAD_NF(GPIO_0, PWR_BTN_L, PULL_NONE), + /* SYS_RESET_L */ + PAD_NF(GPIO_1, SYS_RESET_L, PULL_NONE), + /* WAKE_L */ + PAD_NF_SCI(GPIO_2, WAKE_L, PULL_NONE, EDGE_LOW), + /* PCIE_SD_WAKE_L */ + PAD_SCI(GPIO_3, PULL_NONE, EDGE_LOW), + /* UART_WAKE_L_M2_APU */ + PAD_SCI(GPIO_4, PULL_UP, EDGE_LOW), + /* MPM_EVENT_L, input or OD output */ + PAD_GPI(GPIO_5, PULL_UP), + /* TPNL_INT_L */ + PAD_SCI(GPIO_6, PULL_UP, EDGE_LOW), + /* EC SCI */ + PAD_SCI(GPIO_7, PULL_UP, EDGE_LOW), + /* TPAD_INT_L */ + PAD_SCI(GPIO_8, PULL_UP, EDGE_LOW), + /* SD_CARD_PRSNT_L */ + PAD_GPI(GPIO_9, PULL_UP), /* Unclear if this needs to be SCI */ + /* VDD_MEM_VID0 */ + PAD_GPO(GPIO_10, HIGH), + /* HP_MIC_DET_L */ + PAD_GPI(GPIO_11, PULL_UP), + /* ALIGN_FLAG_MU_L */ + PAD_GPO(GPIO_12, HIGH), + /* GPIO_13 - GPIO_15: Not available */ + /* USB_OC0_L */ + PAD_NF(GPIO_16, USB_OC0_L, PULL_NONE), + /* WAKE_ON_WAN_L */ + PAD_SCI(GPIO_17, PULL_UP, EDGE_LOW), + /* PCIE_WLAN_WAKE_L */ + PAD_SCI(GPIO_18, PULL_UP, EDGE_LOW), + /* I2C3_SCL */ + PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), + /* I2C3_SDA */ + PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), + /* KBRST_L */ + PAD_NF(GPIO_21, KBRST_L, PULL_NONE), + /* ESPI_ALERT_L */ + PAD_NF(GPIO_22, ESPI_ALERT_D1, PULL_NONE), + /* AC_PRES */ + PAD_NF(GPIO_23, AC_PRES, PULL_NONE), + /* PCIE_LOM_WAKE_L */ + PAD_SCI(GPIO_24, PULL_UP, EDGE_LOW), + /* GPIO_25: Not available */ + /* PCIE_RST0_L */ + PAD_NFO(GPIO_26, PCIE_RST0_L, HIGH), + /* PCIE_RST1_L */ + PAD_NFO(GPIO_27, PCIE_RST1_L, HIGH), + /* GPIO_28: Not available */ + /* TPM CS */ + PAD_NF(GPIO_29, SPI_TPM_CS_L, PULL_NONE), + /* ESPI_CS_L */ + PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), + /* INT_CLKREQ_L */ + PAD_SCI(GPIO_31, PULL_UP, EDGE_LOW), + /* LPC_RST_L */ + PAD_NF(GPIO_32, LPC_RST_L, PULL_NONE), + /* GPIO_33 - GPIO_37: Not available */ + /* CLK_REQ5_L */ + PAD_NF(GPIO_38, CLK_REQ5_L, PULL_NONE), + /* CLK_REQ6_L */ + PAD_NF(GPIO_39, CLK_REQ6_L, PULL_NONE), + /* USB2_HDR_P0/1_SMI */ + PAD_SCI(GPIO_40, PULL_UP, EDGE_LOW), + /* GPIO_41: Not available */ + /* VDD_MEM_VID1 */ + PAD_GPO(GPIO_42, HIGH), + /* GPIO_43 - GPIO_66: Not available */ + /* SPI_ROM_REQ */ + PAD_NF(GPIO_67, SPI_ROM_REQ, PULL_NONE), + /* ESPI_DATA2 */ + PAD_NF(GPIO_68, SPI1_DAT2, PULL_NONE), + /* ESPI_DATA3 */ + PAD_NF(GPIO_69, SPI1_DAT3, PULL_NONE), + /* SPI2_CLK */ + PAD_NF(GPIO_70, SPI2_CLK, PULL_NONE), + /* GPIO_71 - GPIO_73: Not available */ + /* APU_NFC_DWL_REQ_1V8 */ + PAD_GPO(GPIO_74, LOW), + /* SPI2_CS1_L */ + PAD_NF(GPIO_75, SPI2_CS1_L, PULL_NONE), + /* SPI_ROM_GNT */ + PAD_NF(GPIO_76, SPI_ROM_GNT, PULL_NONE), + /* ESPI_SOC_CLK */ + PAD_NF(GPIO_77, SPI1_CLK, PULL_NONE), + /* M2_SSD0_RST_L */ + PAD_GPO(GPIO_78, HIGH), + /* M2_SSD1_RST_L */ + PAD_GPO(GPIO_79, HIGH), + /* ESPI_DATA1 */ + PAD_NF(GPIO_80, SPI1_DAT1, PULL_NONE), + /* ESPI_DATA0 */ + PAD_NF(GPIO_81, SPI1_DAT0, PULL_NONE), + /* GPIO_82 - GPIO_83: Not available */ + /* FANIN0 */ + PAD_NF(GPIO_84, FANIN0, PULL_NONE), + /* FANOUT0 */ + PAD_NF(GPIO_85, FANOUT0, PULL_NONE), + /* GPIO_86 - GPIO_88: Not available */ + /* I2S CODEC INT */ + PAD_SCI(GPIO_89, PULL_UP, EDGE_LOW), + /* ALERT_L_M2_SSD0 */ + PAD_SCI(GPIO_90, PULL_UP, EDGE_LOW), + /* NFC IRQ */ + PAD_SCI(GPIO_91, PULL_UP, EDGE_LOW), + /* CLK_REQ0_L */ + PAD_NF(GPIO_92, CLK_REQ0_L, PULL_NONE), + /* GPIO_93 - GPIO_103: Not available */ + /* SPI2_DAT0 */ + PAD_NF(GPIO_104, SPI2_DAT0, PULL_NONE), + /* SPI2_DAT1 */ + PAD_NF(GPIO_105, SPI2_DAT1, PULL_NONE), + /* SPI2_DAT2 */ + PAD_NF(GPIO_106, SPI2_DAT2, PULL_NONE), + /* SPI2_DAT3 */ + PAD_NF(GPIO_107, SPI2_DAT3, PULL_NONE), + /* GPIO_108 - GPIO_112: Not available */ + /* I2C2_SCL */ + PAD_NF(GPIO_113, I2C2_SCL, PULL_NONE), + /* I2C2_SDA */ + PAD_NF(GPIO_114, I2C2_SDA, PULL_NONE), + /* CLK_REQ1_L */ + PAD_NF(GPIO_115, CLK_REQ1_L, PULL_NONE), + /* CLK_REQ2_L */ + PAD_NF(GPIO_116, CLK_REQ2_L, PULL_NONE), + /* GPIO_117 - GPIO_129: Not available */ + /* TPM IRQ */ + PAD_SCI(GPIO_130, PULL_UP, EDGE_LOW), + /* CLK_REQ3_L */ + PAD_NF(GPIO_131, CLK_REQ3_L, PULL_NONE), + /* CLK_REQ4_L */ + PAD_NF(GPIO_132, CLK_REQ4_L, PULL_NONE), + /* GPIO_133 - GPIO_134: Not available */ + /* UART2_CTS_L */ + PAD_NF(GPIO_135, UART2_CTS_L, PULL_NONE), + /* UART2_RXD */ + PAD_NF(GPIO_136, UART2_RXD, PULL_NONE), + /* UART2_RTS_L */ + PAD_NF(GPIO_137, UART2_RTS_L, PULL_NONE), + /* UART2_TXD */ + PAD_NF(GPIO_138, UART2_TXD, PULL_NONE), + /* M2_SSD2_RST_L */ + PAD_GPO(GPIO_139, HIGH), + /* UART0_CTS_L */ + PAD_NF(GPIO_140, UART0_CTS_L, PULL_NONE), + /* UART0_RXD */ + PAD_NF(GPIO_141, UART0_RXD, PULL_NONE), + /* UART0_RTS_L */ + PAD_NF(GPIO_142, UART0_RTS_L, PULL_NONE), + /* UART0_TXD */ + PAD_NF(GPIO_143, UART0_TXD, PULL_NONE), + /* M2_SSD3_RST_L */ + PAD_GPO(GPIO_144, HIGH), + /* I2C0 SCL */ + PAD_NF(GPIO_145, I2C0_SCL, PULL_NONE), + /* I2C0 SDA */ + PAD_NF(GPIO_146, I2C0_SDA, PULL_NONE), + /* I2C1 SCL */ + PAD_NF(GPIO_147, I2C1_SCL, PULL_NONE), + /* I2C1 SDA */ + PAD_NF(GPIO_148, I2C1_SDA, PULL_NONE), + /* GPIO_149 - GPIO_152: Not available */ + /* UART4_CTS_L */ + PAD_NF(GPIO_153, UART4_CTS_L, PULL_NONE), + /* UART4_RTS_L */ + PAD_NF(GPIO_154, UART4_RTS_L, PULL_NONE), + /* UART4_RXD */ + PAD_NF(GPIO_155, UART4_RXD, PULL_NONE), + /* UART4_TXD */ + PAD_NF(GPIO_156, UART4_TXD, PULL_NONE), + /* M2_SSD4_RST_L */ + PAD_GPO(GPIO_157, HIGH), }; void mainboard_program_gpios(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/69411 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5459efb38431e568e25405c440b5b9cf1354f02f Gerrit-Change-Number: 69411 Gerrit-PatchSet: 6 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: acpi: Helper functions to add certain _DSD properties
by Kapil Porwal (Code Review) 30 Nov '22

30 Nov '22

Attention is currently required from: Lance Zhao, Tarun Tuli, Subrata Banik, Tim Wawrzynczak. Kapil Porwal has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70063 ) Change subject: acpi: Helper functions to add certain _DSD properties ...................................................................... Patch Set 7: (1 comment) File src/acpi/device.c: https://review.coreboot.org/c/coreboot/+/70063/comment/0219af53_007ebc67 PS6, Line 1187: /* _DSD with give integer property with UUID */ > nit: "_DSD with giveN integer property and UUID" ? Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/70063 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5bb432dd4e8f320d2c0d7f378dc2d7b3a770b541 Gerrit-Change-Number: 70063 Gerrit-PatchSet: 7 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Comment-Date: Wed, 30 Nov 2022 18:45:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tarun Tuli <taruntuli(a)google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/cmn/block/{pcie/rtd3,usb4}: Use helper functions for _DSD
by Tarun Tuli (Code Review) 30 Nov '22

30 Nov '22

Attention is currently required from: Eran Mitrani, Subrata Banik, Kapil Porwal, Nick Vaccaro. Tarun Tuli has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70065 ) Change subject: soc/intel/cmn/block/{pcie/rtd3,usb4}: Use helper functions for _DSD ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/70065 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib57dea9b16e4590ca2d75ac1512fdaf773ec50f6 Gerrit-Change-Number: 70065 Gerrit-PatchSet: 6 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Wed, 30 Nov 2022 18:37:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: acpi: Helper functions to add certain _DSD properties
by Tarun Tuli (Code Review) 30 Nov '22

30 Nov '22

Attention is currently required from: Lance Zhao, Subrata Banik, Kapil Porwal, Tim Wawrzynczak. Tarun Tuli has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70063 ) Change subject: acpi: Helper functions to add certain _DSD properties ...................................................................... Patch Set 6: (1 comment) File src/acpi/device.c: https://review.coreboot.org/c/coreboot/+/70063/comment/52c64e5c_11737f59 PS6, Line 1187: /* _DSD with give integer property with UUID */ nit: "_DSD with giveN integer property and UUID" ? -- To view, visit https://review.coreboot.org/c/coreboot/+/70063 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5bb432dd4e8f320d2c0d7f378dc2d7b3a770b541 Gerrit-Change-Number: 70063 Gerrit-PatchSet: 6 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Comment-Date: Wed, 30 Nov 2022 18:34:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: acpi: Helper functions to add certain _DSD properties
by Tarun Tuli (Code Review) 30 Nov '22

30 Nov '22

Attention is currently required from: Lance Zhao, Subrata Banik, Kapil Porwal, Tim Wawrzynczak. Tarun Tuli has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70063 ) Change subject: acpi: Helper functions to add certain _DSD properties ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/70063 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5bb432dd4e8f320d2c0d7f378dc2d7b3a770b541 Gerrit-Change-Number: 70063 Gerrit-PatchSet: 6 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Comment-Date: Wed, 30 Nov 2022 18:29:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/amd/mendocino: Enhance DPTC_INPUT to support 13 DPTC thermal para...
by Felix Held (Code Review) 30 Nov '22

30 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68649 ) Change subject: soc/amd/mendocino: Enhance DPTC_INPUT to support 13 DPTC thermal parameters ...................................................................... soc/amd/mendocino: Enhance DPTC_INPUT to support 13 DPTC thermal parameters Expand DPTC_INPUT macro to supoort 13 DPTC thermal table parameters for dynamic table switching support. BRANCH=none BUG=b:232946420 TEST=emerge-skyrim coreboot Signed-off-by: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Change-Id: I6d6a00f0eca0b0941860b9bc75da41d7a10d60e8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68649 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/mainboard/google/skyrim/Kconfig M src/soc/amd/mendocino/root_complex.c 2 files changed, 164 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/mainboard/google/skyrim/Kconfig b/src/mainboard/google/skyrim/Kconfig index 416d8e2..a89cc82 100644 --- a/src/mainboard/google/skyrim/Kconfig +++ b/src/mainboard/google/skyrim/Kconfig @@ -154,4 +154,11 @@ just the small SRAM buffer to a much larger area reserved in main memory. +config FEATURE_DYNAMIC_DPTC + bool + depends on SOC_AMD_COMMON_BLOCK_ACPI_DPTC + help + Selected by mainboards that implement support for ALIB + to enable dynamic DPTC. + endif # BOARD_GOOGLE_BASEBOARD_SKYRIM diff --git a/src/soc/amd/mendocino/root_complex.c b/src/soc/amd/mendocino/root_complex.c index 0d24a25..35fc573 100644 --- a/src/soc/amd/mendocino/root_complex.c +++ b/src/soc/amd/mendocino/root_complex.c @@ -18,15 +18,17 @@ #include <stdint.h> #include "chip.h" -#define DPTC_TOTAL_UPDATE_PARAMS 7 +#define DPTC_TOTAL_UPDATE_PARAMS 13 struct dptc_input { uint16_t size; struct alib_dptc_param params[DPTC_TOTAL_UPDATE_PARAMS]; } __packed; -#define DPTC_INPUTS(_thermctllmit, _sustained, _fast, _slow, \ - _vrmCurrentLimit, _vrmMaxCurrentLimit, _vrmSocCurrentLimit) \ + +#define DPTC_INPUTS(_thermctllmit, _sustained, _spptTimeConst, _fast, _slow, \ + _vrmCurrentLimit, _vrmMaxCurrentLimit, _vrmSocCurrentLimit, \ + _sttMinLimit, _sttM1, _sttM2, _sttCApu, _sttSkinTempLimitApu) \ { \ .size = sizeof(struct dptc_input), \ .params = { \ @@ -39,6 +41,10 @@ .value = _sustained, \ }, \ { \ + .id = ALIB_DPTC_SLOW_PPT_TIME_CONSTANT_ID, \ + .value = _spptTimeConst, \ + }, \ + { \ .id = ALIB_DPTC_FAST_PPT_LIMIT_ID, \ .value = _fast, \ }, \ @@ -58,6 +64,26 @@ .id = ALIB_DPTC_VRM_SOC_CURRENT_LIMIT_ID, \ .value = _vrmSocCurrentLimit, \ }, \ + { \ + .id = ALIB_DPTC_STT_MIN_LIMIT_ID, \ + .value = _sttMinLimit, \ + }, \ + { \ + .id = ALIB_DPTC_STT_M1_ID, \ + .value = _sttM1, \ + }, \ + { \ + .id = ALIB_DPTC_STT_M2_ID, \ + .value = _sttM2, \ + }, \ + { \ + .id = ALIB_DPTC_STT_C_APU_ID, \ + .value = _sttCApu, \ + }, \ + { \ + .id = ALIB_DPTC_STT_SKIN_TEMPERATURE_LIMIT_APU_ID, \ + .value = _sttSkinTempLimitApu, \ + }, \ }, \ } @@ -195,26 +221,131 @@ const struct soc_amd_mendocino_config *config = config_of_soc(); /* Normal mode DPTC values. */ - struct dptc_input default_input = DPTC_INPUTS(config->thermctl_limit_degreeC, + struct dptc_input default_input = DPTC_INPUTS( + config->thermctl_limit_degreeC, config->sustained_power_limit_mW, + config->slow_ppt_time_constant_s, config->fast_ppt_limit_mW, config->slow_ppt_limit_mW, config->vrm_current_limit_mA, config->vrm_maximum_current_limit_mA, - config->vrm_soc_current_limit_mA); + config->vrm_soc_current_limit_mA, + config->stt_min_limit, + config->stt_m1, + config->stt_m2, + config->stt_c_apu, + config->stt_skin_temp_apu); acpigen_write_alib_dptc_default((uint8_t *)&default_input, sizeof(default_input)); /* Low/No Battery */ struct dptc_input no_battery_input = DPTC_INPUTS( config->thermctl_limit_degreeC, config->sustained_power_limit_mW, + config->slow_ppt_time_constant_s, config->fast_ppt_limit_mW, config->slow_ppt_limit_mW, config->vrm_current_limit_throttle_mA, config->vrm_maximum_current_limit_throttle_mA, - config->vrm_soc_current_limit_throttle_mA); + config->vrm_soc_current_limit_throttle_mA, + config->stt_min_limit, + config->stt_m1, + config->stt_m2, + config->stt_c_apu, + config->stt_skin_temp_apu); acpigen_write_alib_dptc_no_battery((uint8_t *)&no_battery_input, sizeof(no_battery_input)); + +#if (CONFIG(FEATURE_DYNAMIC_DPTC)) + /* Profile B */ + struct dptc_input thermal_B_input = DPTC_INPUTS( + config->thermctl_limit_degreeC, + config->sustained_power_limit_mW_B, + config->slow_ppt_time_constant_s_B, + config->fast_ppt_limit_mW_B, + config->slow_ppt_limit_mW_B, + config->vrm_current_limit_throttle_mA, + config->vrm_maximum_current_limit_mA, + config->vrm_soc_current_limit_mA, + config->stt_min_limit_B, + config->stt_m1_B, + config->stt_m2_B, + config->stt_c_apu_B, + config->stt_skin_temp_apu_B); + acpigen_write_alib_dptc_thermal_B((uint8_t *)&thermal_B_input, + sizeof(thermal_B_input)); + + /* Profile C */ + struct dptc_input thermal_C_input = DPTC_INPUTS( + config->thermctl_limit_degreeC, + config->sustained_power_limit_mW_C, + config->slow_ppt_time_constant_s_C, + config->fast_ppt_limit_mW_C, + config->slow_ppt_limit_mW_C, + config->vrm_current_limit_mA, + config->vrm_maximum_current_limit_mA, + config->vrm_soc_current_limit_mA, + config->stt_min_limit_C, + config->stt_m1_C, + config->stt_m2_C, + config->stt_c_apu_C, + config->stt_skin_temp_apu_C); + acpigen_write_alib_dptc_thermal_C((uint8_t *)&thermal_C_input, + sizeof(thermal_C_input)); + + /* Profile D */ + struct dptc_input thermal_D_input = DPTC_INPUTS( + config->thermctl_limit_degreeC, + config->sustained_power_limit_mW_D, + config->slow_ppt_time_constant_s_D, + config->fast_ppt_limit_mW_D, + config->slow_ppt_limit_mW_D, + config->vrm_current_limit_mA, + config->vrm_maximum_current_limit_mA, + config->vrm_soc_current_limit_mA, + config->stt_min_limit_D, + config->stt_m1_D, + config->stt_m2_D, + config->stt_c_apu_D, + config->stt_skin_temp_apu_D); + acpigen_write_alib_dptc_thermal_D((uint8_t *)&thermal_D_input, + sizeof(thermal_D_input)); + + /* Profile E */ + struct dptc_input thermal_E_input = DPTC_INPUTS( + config->thermctl_limit_degreeC, + config->sustained_power_limit_mW_E, + config->slow_ppt_time_constant_s_E, + config->fast_ppt_limit_mW_E, + config->slow_ppt_limit_mW_E, + config->vrm_current_limit_mA, + config->vrm_maximum_current_limit_mA, + config->vrm_soc_current_limit_mA, + config->stt_min_limit_E, + config->stt_m1_E, + config->stt_m2_E, + config->stt_c_apu_E, + config->stt_skin_temp_apu_E); + acpigen_write_alib_dptc_thermal_E((uint8_t *)&thermal_E_input, + sizeof(thermal_E_input)); + + /* Profile F */ + struct dptc_input thermal_F_input = DPTC_INPUTS( + config->thermctl_limit_degreeC, + config->sustained_power_limit_mW_F, + config->slow_ppt_time_constant_s_F, + config->fast_ppt_limit_mW_F, + config->slow_ppt_limit_mW_F, + config->vrm_current_limit_mA, + config->vrm_maximum_current_limit_mA, + config->vrm_soc_current_limit_mA, + config->stt_min_limit_F, + config->stt_m1_F, + config->stt_m2_F, + config->stt_c_apu_F, + config->stt_skin_temp_apu_F); + acpigen_write_alib_dptc_thermal_F((uint8_t *)&thermal_F_input, + sizeof(thermal_F_input)); +#endif } static void root_complex_fill_ssdt(const struct device *device) -- To view, visit https://review.coreboot.org/c/coreboot/+/68649 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6d6a00f0eca0b0941860b9bc75da41d7a10d60e8 Gerrit-Change-Number: 68649 Gerrit-PatchSet: 32 Gerrit-Owner: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nelson Ye <nelson_ye(a)compal.corp-partner.google.com> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel/alderlake: skip external buses for D-states list
by Subrata Banik (Code Review) 30 Nov '22

30 Nov '22

Attention is currently required from: Eran Mitrani. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70163 ) Change subject: soc/intel/alderlake: skip external buses for D-states list ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/70163 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3785b2b2af85d96e2e1296b6cfdefcd72080b5fe Gerrit-Change-Number: 70163 Gerrit-PatchSet: 5 Gerrit-Owner: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Comment-Date: Wed, 30 Nov 2022 17:50:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: Documentation: Add wake source info to device tree documentation
by Tim Van Patten (Code Review) 30 Nov '22

30 Nov '22

Attention is currently required from: Raul Rangel, Dmitry Torokhov, Tim Wawrzynczak, Paul Menzel. Tim Van Patten has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67385 ) Change subject: Documentation: Add wake source info to device tree documentation ...................................................................... Patch Set 8: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/67385 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifcdbd5371408784bf9b81c1ade90263de8c60e0f Gerrit-Change-Number: 67385 Gerrit-PatchSet: 8 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Dmitry Torokhov <dtor(a)chromium.org> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Mark Hasemeyer <markhas(a)google.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Robert Zieba <robertzieba(a)google.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Dmitry Torokhov <dtor(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Wed, 30 Nov 2022 17:41:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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