coreboot-gerrit November 2022

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Change in coreboot[master]: mb/google/volteer: Clean up romstage.c
by Tim Wawrzynczak (Code Review) 20 Dec '22

20 Dec '22

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48512 ) Change subject: mb/google/volteer: Clean up romstage.c ...................................................................... mb/google/volteer: Clean up romstage.c Move the manual calls to fw_config_probe() into the devicetree; the AUDIO probe is trivial, and the TCSS devices (DMA0, iTBT RP0 & RP1) are already guarded with probe statements in the baseboard devicetree, so the code in romstage.c was redundant. Change-Id: I1d067ff3d181b152c784634ff99202bb2b9202f7 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/volteer/romstage.c M src/mainboard/google/volteer/variants/baseboard/devicetree.cb 2 files changed, 7 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/48512/1 diff --git a/src/mainboard/google/volteer/romstage.c b/src/mainboard/google/volteer/romstage.c index 315ec20..67d3489 100644 --- a/src/mainboard/google/volteer/romstage.c +++ b/src/mainboard/google/volteer/romstage.c @@ -22,17 +22,5 @@ }; bool half_populated = gpio_get(GPIO_MEM_CH_SEL); - /* Disable HDA device if no audio board is present. */ - if (fw_config_probe(FW_CONFIG(AUDIO, NONE))) - mem_cfg->PchHdaEnable = 0; - meminit_ddr(mem_cfg, board_cfg, &spd_info, half_populated); - - /* Disable TBT if no USB4 hardware */ - if (!(fw_config_probe(FW_CONFIG(DB_USB, USB4_GEN2)) || - fw_config_probe(FW_CONFIG(DB_USB, USB4_GEN3)))) { - mem_cfg->TcssDma0En = 0; - mem_cfg->TcssItbtPcie0En = 0; - mem_cfg->TcssItbtPcie1En = 0; - } } diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 7964885..c61b003 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -501,6 +501,12 @@ device pnp 0c09.0 on end end end - device ref hda on end + device ref hda on + probe AUDIO MAX98357_ALC5682I_I2S + probe AUDIO MAX98373_ALC5682I_I2S + probe AUDIO MAX98373_ALC5682_SNDW + probe AUDIO MAX98373_ALC5682I_I2S_UP4 + probe AUDIO MAX98360_ALC5682I_I2S + end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/48512 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1d067ff3d181b152c784634ff99202bb2b9202f7 Gerrit-Change-Number: 48512 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

5 15

Change in coreboot[master]: Disable SeaBIOS options unsupported by hardware: scripts to apply the...
by Mike Banon (Code Review) 18 Dec '22

18 Dec '22

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44638 ) Change subject: Disable SeaBIOS options unsupported by hardware: scripts to apply the patches ...................................................................... Disable SeaBIOS options unsupported by hardware: scripts to apply the patches These scripts will help you to securely and conveniently apply CB:44636 and CB:44637 to disable SeaBIOS options unsupported by ASUS AM1I-A and ASUS A88XM-E. Save to ./coreboot/ then run ./get_cfgsb_patches.sh , ./check... and ./apply... https://review.coreboot.org/c/coreboot/+/44636 mb/asus/am1i-a: Disable SeaBIOS options unsupported by hardware https://review.coreboot.org/c/coreboot/+/44637 mb/asus/a88xm-e: Disable SeaBIOS options unsupported by hardware Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I8baaca0d58b863a7084b8672fb9574ebb5e72591 --- A apply_cfgsb_patches.sh A check_cfgsb_patches.sh A get_cfgsb_patches.sh A sha256sums_cfgsb_correct.txt 4 files changed, 43 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/44638/1 diff --git a/apply_cfgsb_patches.sh b/apply_cfgsb_patches.sh new file mode 100755 index 0000000..657211e --- /dev/null +++ b/apply_cfgsb_patches.sh @@ -0,0 +1,12 @@ +#!/bin/sh +### +### https://review.coreboot.org/c/coreboot/+/44636 +### mb/asus/am1i-a: Disable SeaBIOS options unsupported by hardware +### +patch -p1 < "./f4b8121.diff" +### +### https://review.coreboot.org/c/coreboot/+/44637 +### mb/asus/a88xm-e: Disable SeaBIOS options unsupported by hardware +### +patch -p1 < "./4f95dab.diff" +### diff --git a/check_cfgsb_patches.sh b/check_cfgsb_patches.sh new file mode 100755 index 0000000..87f2bac --- /dev/null +++ b/check_cfgsb_patches.sh @@ -0,0 +1,13 @@ +#!/bin/sh +rm -f "./sha256sums_cfgsb_my.txt" +sha256sum "./f4b8121.diff" > "./sha256sums_cfgsb_my.txt" +sha256sum "./4f95dab.diff" >> "./sha256sums_cfgsb_my.txt" +if cmp -s "./sha256sums_cfgsb_my.txt" "./sha256sums_cfgsb_correct.txt" +then + echo "SHA256 checksums are correct, please run ./apply_cfgsb_patches.sh" + exit 0 +else + echo "! MISMATCH ! See ./sha256sums_cfgsb_my.txt and ./sha256sums_cfgsb_correct.txt" + exit 1 +fi +# diff --git a/get_cfgsb_patches.sh b/get_cfgsb_patches.sh new file mode 100755 index 0000000..8070382 --- /dev/null +++ b/get_cfgsb_patches.sh @@ -0,0 +1,16 @@ +#!/bin/sh +### +### https://review.coreboot.org/c/coreboot/+/44636 +### mb/asus/am1i-a: Disable SeaBIOS options unsupported by hardware +### +rm -f "./f4b8121.diff" +wget "https://review.coreboot.org/changes/44636/revisions/1/patch?zip" +unzip "./patch?zip" && rm -f "./patch?zip" # && patch -p1 < "./f4b8121.diff" +### +### https://review.coreboot.org/c/coreboot/+/44637 +### mb/asus/a88xm-e: Disable SeaBIOS options unsupported by hardware +### +rm -f "./4f95dab.diff" +wget "https://review.coreboot.org/changes/44637/revisions/1/patch?zip" +unzip "./patch?zip" && rm -f "./patch?zip" # && patch -p1 < "./4f95dab.diff" +### diff --git a/sha256sums_cfgsb_correct.txt b/sha256sums_cfgsb_correct.txt new file mode 100644 index 0000000..afe90bc --- /dev/null +++ b/sha256sums_cfgsb_correct.txt @@ -0,0 +1,2 @@ +1a3aced0e9d3cce8aaeeebf94c035ed028dc4b262d06cce0addc97df85905dc3 ./f4b8121.diff +270e30aa319e0fa9b661b2f7f0aaa6e04e6c6f2fea0fc354160867c4e92bb7a3 ./4f95dab.diff -- To view, visit https://review.coreboot.org/c/coreboot/+/44638 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8baaca0d58b863a7084b8672fb9574ebb5e72591 Gerrit-Change-Number: 44638 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

2 4

Change in coreboot[master]: AMD good IRQs: scripts for applying the unofficial (not-merged-yet) p...
by Mike Banon (Code Review) 18 Dec '22

18 Dec '22

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48427 ) Change subject: AMD good IRQs: scripts for applying the unofficial (not-merged-yet) patches ...................................................................... AMD good IRQs: scripts for applying the unofficial (not-merged-yet) patches These scripts will help you to securely and conveniently apply seven changes for improving the IRQ routing on these AMD boards: 1) CB:48161, CB:48162, CB:48163, CB:48179 - for AMD Lenovo G505S; 2) CB:48424, CB:48425, CB:48426 - for ASUS A88XM-E; 3) Not ready yet - for ASUS AM1I-A. Save to ./coreboot/ then run ./get_irq_patches.sh , ./check... and ./apply... Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I04869ae24185eef5399c3fd9b8d4965ec4e33a19 --- A apply_irq_patches.sh A check_irq_patches.sh A get_irq_patches.sh A sha256sums_irq_correct.txt 4 files changed, 113 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/48427/1 diff --git a/apply_irq_patches.sh b/apply_irq_patches.sh new file mode 100755 index 0000000..8fc5318 --- /dev/null +++ b/apply_irq_patches.sh @@ -0,0 +1,37 @@ +#!/bin/sh +### +### https://review.coreboot.org/c/coreboot/+/48161 +### lenovo/g505s: properly program the IRQ tables +### +patch -p1 < "./cd096f9.diff" +### +### https://review.coreboot.org/c/coreboot/+/48162 +### lenovo/g505s: update the ACPI routing to match the new IRQ routing +### +patch -p1 < "./42aeed4.diff" +### +### https://review.coreboot.org/c/coreboot/+/48163 +### lenovo/g505s: add the PIRQ routing table +### +patch -p1 < "./c6ab05e.diff" +### +### https://review.coreboot.org/c/coreboot/+/48179 +### lenovo/g505s: enable the webcam [WIP] +### +patch -p1 < "./8517e5a.diff" +### +### https://review.coreboot.org/c/coreboot/+/48424 +### asus/a88xm-e: properly program the IRQ tables +### +patch -p1 < "./cfc8288.diff" +### +### https://review.coreboot.org/c/coreboot/+/48425 +### asus/a88xm-e: update the ACPI routing to match the new IRQ routing +### +patch -p1 < "./489e510.diff" +### +### https://review.coreboot.org/c/coreboot/+/48426 +### asus/a88xm-e: add the PIRQ routing table +### +patch -p1 < "./08638df.diff" +### diff --git a/check_irq_patches.sh b/check_irq_patches.sh new file mode 100755 index 0000000..3a2bb16 --- /dev/null +++ b/check_irq_patches.sh @@ -0,0 +1,18 @@ +#!/bin/sh +rm -f "./sha256sums_irq_my.txt" +sha256sum "./cd096f9.diff" > "./sha256sums_irq_my.txt" +sha256sum "./42aeed4.diff" >> "./sha256sums_irq_my.txt" +sha256sum "./c6ab05e.diff" >> "./sha256sums_irq_my.txt" +sha256sum "./8517e5a.diff" >> "./sha256sums_irq_my.txt" +sha256sum "./cfc8288.diff" >> "./sha256sums_irq_my.txt" +sha256sum "./489e510.diff" >> "./sha256sums_irq_my.txt" +sha256sum "./08638df.diff" >> "./sha256sums_irq_my.txt" +if cmp -s "./sha256sums_irq_my.txt" "./sha256sums_irq_correct.txt" +then + echo "SHA256 checksums are correct, please run ./apply_irq_patches.sh" + exit 0 +else + echo "! MISMATCH ! See ./sha256sums_irq_my.txt and ./sha256sums_irq_correct.txt" + exit 1 +fi +# diff --git a/get_irq_patches.sh b/get_irq_patches.sh new file mode 100755 index 0000000..97da6b5 --- /dev/null +++ b/get_irq_patches.sh @@ -0,0 +1,51 @@ +#!/bin/sh +### +### https://review.coreboot.org/c/coreboot/+/48161 +### lenovo/g505s: properly program the IRQ tables +### +rm -f "./cd096f9.diff" +wget "https://review.coreboot.org/changes/48161/revisions/1/patch?zip" +unzip "./patch?zip" && rm -f "./patch?zip" # && patch -p1 < "./cd096f9.diff" +### +### https://review.coreboot.org/c/coreboot/+/48162 +### lenovo/g505s: update the ACPI routing to match the new IRQ routing +### +rm -f "./42aeed4.diff" +wget "https://review.coreboot.org/changes/48162/revisions/1/patch?zip" +unzip "./patch?zip" && rm -f "./patch?zip" # && patch -p1 < "./42aeed4.diff" +### +### https://review.coreboot.org/c/coreboot/+/48163 +### lenovo/g505s: add the PIRQ routing table +### +rm -f "./c6ab05e.diff" +wget "https://review.coreboot.org/changes/48163/revisions/3/patch?zip" +unzip "./patch?zip" && rm -f "./patch?zip" # && patch -p1 < "./c6ab05e.diff" +### +### https://review.coreboot.org/c/coreboot/+/48179 +### lenovo/g505s: enable the webcam [WIP] +### +rm -f "./8517e5a.diff" +wget "https://review.coreboot.org/changes/48179/revisions/1/patch?zip" +unzip "./patch?zip" && rm -f "./patch?zip" # && patch -p1 < "./8517e5a.diff" +### +### https://review.coreboot.org/c/coreboot/+/48424 +### asus/a88xm-e: properly program the IRQ tables +### +rm -f "./cfc8288.diff" +wget "https://review.coreboot.org/changes/48424/revisions/1/patch?zip" +unzip "./patch?zip" && rm -f "./patch?zip" # && patch -p1 < "./cfc8288.diff" +### +### https://review.coreboot.org/c/coreboot/+/48425 +### asus/a88xm-e: update the ACPI routing to match the new IRQ routing +### +rm -f "./489e510.diff" +wget "https://review.coreboot.org/changes/48425/revisions/1/patch?zip" +unzip "./patch?zip" && rm -f "./patch?zip" # && patch -p1 < "./489e510.diff" +### +### https://review.coreboot.org/c/coreboot/+/48426 +### asus/a88xm-e: add the PIRQ routing table +### +rm -f "./08638df.diff" +wget "https://review.coreboot.org/changes/48426/revisions/1/patch?zip" +unzip "./patch?zip" && rm -f "./patch?zip" # && patch -p1 < "./08638df.diff" +### diff --git a/sha256sums_irq_correct.txt b/sha256sums_irq_correct.txt new file mode 100755 index 0000000..a06b640 --- /dev/null +++ b/sha256sums_irq_correct.txt @@ -0,0 +1,7 @@ +9fd4cca063bb6e6c9063f00f4c972c019d616560883b9bda76177a462817ae8e ./cd096f9.diff +357a1e1e9f250149127fa8f7aac089e481a39f96b313ae1a0310c7e5d22faa72 ./42aeed4.diff +e350591056f1a10b5922cc7180a07e1142f14fe8af41f6c545317a37c12880ed ./c6ab05e.diff +ab0b347af164e5c50c580f036e7ed55757e90158ad3cb04fc2f8154b5392f804 ./8517e5a.diff +358c3a5fcce7085ca49154370c21cd95396fa8fa9d0b30e1de8625fe1db0f36d ./cfc8288.diff +669bd10d74229f3e2200a9e206fad49326928348a6ad3f261f14ebe920b63c56 ./489e510.diff +fab791e93eb63b880d2692eff527979051dadcf504018f58346c6f0c4c6173b6 ./08638df.diff -- To view, visit https://review.coreboot.org/c/coreboot/+/48427 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I04869ae24185eef5399c3fd9b8d4965ec4e33a19 Gerrit-Change-Number: 48427 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

3 14

[M] Change in coreboot[master]: mb/google/herobrine: Only retrieve sku_id from EC once
by Julius Werner (Code Review) 01 Dec '22

01 Dec '22

Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70162 ) Change subject: mb/google/herobrine: Only retrieve sku_id from EC once ...................................................................... Patch Set 4: (1 comment) File src/mainboard/google/herobrine/boardid.c: https://review.coreboot.org/c/coreboot/+/70162/comment/dbef7480_57c1dc78 PS2, Line 28: printk(BIOS_INFO, "BoardID :%d - " > Also, I put in an early exit like in sku_id because I figured that it wouldn't be useful setting up […] The compiler should be smart enough to move that array setup into the if-block to avoid extra cycles in the case where it's already cached. But no harm in making it more explicit. -- To view, visit https://review.coreboot.org/c/coreboot/+/70162 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia787968100baf58a41ccce0cf95ed3ec9ce1758a Gerrit-Change-Number: 70162 Gerrit-PatchSet: 4 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Doug Anderson <dianders(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-CC: Venkat Thogaru <thogaru(a)qualcomm.corp-partner.google.com> Gerrit-CC: mturney mturney <mturney(a)codeaurora.org> Gerrit-Comment-Date: Wed, 30 Nov 2022 23:27:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shelley Chen <shchen(a)google.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: vboot: Force config file inclusion with CBFS integration
by Julius Werner (Code Review) 01 Dec '22

01 Dec '22

Julius Werner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/70157 ) Change subject: vboot: Force config file inclusion with CBFS integration ...................................................................... vboot: Force config file inclusion with CBFS integration CONFIG_VBOOT_CBFS_INTEGRATION images are signed differently than normal images. futility needs to be able to tell this difference, and it parses the `config` file included in CBFS to do this. This change codifies that dependency in Kconfig so that nobody can accidentally break this by turning off config file inclusion. Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: I2b2d245b850bc65abb4e72f20b4e360312c828f7 --- M src/security/vboot/Kconfig 1 file changed, 17 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/70157/1 diff --git a/src/security/vboot/Kconfig b/src/security/vboot/Kconfig index 93e1845..9025979 100644 --- a/src/security/vboot/Kconfig +++ b/src/security/vboot/Kconfig @@ -40,6 +40,7 @@ default n depends on VBOOT_SLOTS_RW_A depends on CBFS_VERIFICATION + select INCLUDE_CONFIG_FILE # futility needs this to auto-detect signing type help Say yes here to enable cryptographic verification of RW slots CBFS metadata. This will replace body hash verification. -- To view, visit https://review.coreboot.org/c/coreboot/+/70157 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b2d245b850bc65abb4e72f20b4e360312c828f7 Gerrit-Change-Number: 70157 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

1 0

[M] Change in coreboot[master]: build: List all Kconfigs in CBFS `config` file, compress it
by Julius Werner (Code Review) 01 Dec '22

01 Dec '22

Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69710 ) Change subject: build: List all Kconfigs in CBFS `config` file, compress it ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: > Technically, the new use case was already possible, just needed additional steps. Well, it's only possible when you have access to the original coreboot source tree that the image was built with. That isn't always the case. My goal was to make it possible to tell the state of any option if you just have the image and nothing else. (In this instance our goal is to make futility able to tell whether certain verification options like CONFIG_VBOOT_CBFS_INTEGRATION are set so it can pick the appropriate strategy when re-signing an image with different keys.) > With the fixed, new solution, if one wants to see which options differ from defaults (a common case when providing user support), one has to run make olddefconfig && make savedefconfig . I fixed this now with the second patch set in CB:69955. It puts the savedefconfig options first in the file, then a comment saying that that part ends there, and then the other (automatic) options below that. That way you can easily get the minimal defconfig back by just cutting off everything below that comment. I hope that's a compromise that makes all our use cases work? -- To view, visit https://review.coreboot.org/c/coreboot/+/69710 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5259ec6f932cdc5780b8843f46dd476da9d19728 Gerrit-Change-Number: 69710 Gerrit-PatchSet: 3 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Vadim Bendebury <vbendeb(a)chromium.org> Gerrit-Comment-Date: Wed, 30 Nov 2022 23:16:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: lib/lzmadecode: Allow for 8 byte reads on 64bit
by Arthur Heymans (Code Review) 01 Dec '22

01 Dec '22

Arthur Heymans has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/70175 ) Change subject: lib/lzmadecode: Allow for 8 byte reads on 64bit ...................................................................... lib/lzmadecode: Allow for 8 byte reads on 64bit This adds an optimization to lzma decode to also read from the boot medium in chunks of 8 bytes if that is the general purpose register length instead of always 4 bytes. It depends on the cache / memory / spi controller whether this is faster, but it's likely to be either the same or faster. TESTED - google/vilboz: cached boot medium 64bit before - 32bit - 64bit after load FSP-M: 35,674 - 35,595 - 34,690 load ramstage: 42,134 - 43,378 - 40,882 load FSP-S: 24,954 - 25,496 - 24,368 - foxconn/g41m: uncached boot medium for testing 64bit before - 32bit - 64bit after load ramstage: 51,164 - 51,872 - 51,894 Change-Id: I890c075307c0aec877618d9902ea352ae42a3bfa Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/lib/lzmadecode.c M src/lib/lzmadecode.h 2 files changed, 37 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/70175/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/70175 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I890c075307c0aec877618d9902ea352ae42a3bfa Gerrit-Change-Number: 70175 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

1 0

[S] Change in coreboot[master]: lib/lzmadecode: Allow for 8 byte reads on 64bit
by Arthur Heymans (Code Review) 01 Dec '22

01 Dec '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/70175 ) Change subject: lib/lzmadecode: Allow for 8 byte reads on 64bit ...................................................................... lib/lzmadecode: Allow for 8 byte reads on 64bit This adds an optimization to lzma decode to also read from the boot medium in chunks of 8 bytes if that is the general purpose register length instead of always 4 bytes. It depends on the cache / memory / spi controller whether this is faster, but it's likely to be either the same or faster. TESTED - google/vilboz: cached boot medium 64bit before - 32bit - 64bit after load FSP-M: 35,674 - 35,595 - 34,690 load ramstage: 42,134 - 43,378 - 40,882 load FSP-S: 24,954 - 25,496 - 24,368 - foxconn/g41m: uncached boot medium for testing 64bit before - 32bit - 64bit after load ramstage: 51,164 - 51,872 - 64,892 Change-Id: I890c075307c0aec877618d9902ea352ae42a3bfa Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/lib/lzmadecode.c M src/lib/lzmadecode.h 2 files changed, 37 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/70175/1 diff --git a/src/lib/lzmadecode.c b/src/lib/lzmadecode.c index cb86829..5c6baa4 100644 --- a/src/lib/lzmadecode.c +++ b/src/lib/lzmadecode.c @@ -35,15 +35,15 @@ #define kBitModelTotal (1 << kNumBitModelTotalBits) #define kNumMoveBits 5 -/* Use 32-bit reads whenever possible to avoid bad flash performance. Fall back - * to byte reads for last 4 bytes since RC_TEST returns an error when BufferLim +/* Use sizeof(SizeT) sized reads whenever possible to avoid bad flash performance. Fall back + * to byte reads for last sizeof(SizeT) bytes since RC_TEST returns an error when BufferLim * is *reached* (not surpassed!), meaning we can't allow that to happen while * there are still bytes to decode from the algorithm's point of view. */ #define RC_READ_BYTE \ - (look_ahead_ptr < 4 ? look_ahead.raw[look_ahead_ptr++] \ - : ((((uintptr_t) Buffer & 3) \ - || ((SizeT) (BufferLim - Buffer) <= 4)) ? (*Buffer++) \ - : ((look_ahead.dw = *(UInt32 *)Buffer), (Buffer += 4), \ + (look_ahead_ptr < sizeof(SizeT) ? look_ahead.raw[look_ahead_ptr++] \ + : ((((uintptr_t) Buffer & (sizeof(SizeT) - 1)) \ + || ((SizeT) (BufferLim - Buffer) <= sizeof(SizeT))) ? (*Buffer++) \ + : ((look_ahead.dw = *(SizeT *)Buffer), (Buffer += sizeof(SizeT)), \ (look_ahead_ptr = 1), look_ahead.raw[0]))) #define RC_INIT2 Code = 0; Range = 0xFFFFFFFF; \ @@ -207,10 +207,10 @@ int len = 0; const Byte *Buffer; const Byte *BufferLim; - int look_ahead_ptr = 4; + int look_ahead_ptr = sizeof(SizeT); union { - Byte raw[4]; - UInt32 dw; + Byte raw[sizeof(SizeT)]; + SizeT dw; } look_ahead; UInt32 Range; UInt32 Code; diff --git a/src/lib/lzmadecode.h b/src/lib/lzmadecode.h index 9ed352a..d897af7 100644 --- a/src/lib/lzmadecode.h +++ b/src/lib/lzmadecode.h @@ -25,7 +25,7 @@ typedef unsigned char Byte; typedef unsigned short UInt16; typedef unsigned int UInt32; -typedef UInt32 SizeT; +typedef unsigned long int SizeT; #define CProb UInt16 -- To view, visit https://review.coreboot.org/c/coreboot/+/70175 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I890c075307c0aec877618d9902ea352ae42a3bfa Gerrit-Change-Number: 70175 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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[L] Change in coreboot[master]: soc/intel/common: provide a list of D-states to enter LPM
by Eran Mitrani (Code Review) 01 Dec '22

01 Dec '22

Attention is currently required from: Tarun Tuli, Subrata Banik. Hello build bot (Jenkins), Tarun Tuli, Subrata Banik, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/70166 to look at the new patch set (#3). Change subject: soc/intel/common: provide a list of D-states to enter LPM ...................................................................... soc/intel/common: provide a list of D-states to enter LPM This was done previously for ADL. moving the code to common so it can be leveraged for other platforms (e.g. MTL) TEST=Built and tested on anahera by verifying SSDT contents Change-Id: I45eded3868a4987cb5eb0676c50378ac52ec3752 Signed-off-by: Eran Mitrani <mitrani(a)google.com> --- M src/include/acpi/acpi.h M src/soc/intel/alderlake/acpi.c M src/soc/intel/common/block/acpi/acpi.c M src/soc/intel/common/block/include/intelblocks/acpi.h 4 files changed, 195 insertions(+), 156 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/70166/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/70166 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I45eded3868a4987cb5eb0676c50378ac52ec3752 Gerrit-Change-Number: 70166 Gerrit-PatchSet: 3 Gerrit-Owner: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[master]: soc/intel/common: provide a list of D-states to enter LPM
by Eran Mitrani (Code Review) 01 Dec '22

01 Dec '22

Eran Mitrani has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70166 ) Change subject: soc/intel/common: provide a list of D-states to enter LPM ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/70166 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I45eded3868a4987cb5eb0676c50378ac52ec3752 Gerrit-Change-Number: 70166 Gerrit-PatchSet: 2 Gerrit-Owner: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 30 Nov 2022 22:23:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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