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Change subject: mb/google/skyrim: Store XHCI PCI BARs
......................................................................
mb/google/skyrim: Store XHCI PCI BARs
This commit implements `smm_mainboard_pci_bar_store_init` to store the
BARs for XHCI devices. These stored BARs are later used by the elog code
to log XHCI wake events.
Example elog contents:
```
244 | 2022-10-11 15:49:24 | S0ix Enter
245 | 2022-10-11 15:49:29 | S0ix Exit
246 | 2022-10-11 15:49:29 | Wake Source | GPE # | 31
247 | 2022-10-11 15:49:29 | Wake Source | PME - XHCI (USB 2.0 port) | 256
248 | 2022-10-11 15:50:08 | S0ix Enter
249 | 2022-10-11 15:50:16 | S0ix Exit
250 | 2022-10-11 15:50:16 | Wake Source | GPE # | 31
251 | 2022-10-11 15:50:16 | Wake Source | PME - XHCI (USB 2.0 port) | 257
```
BUG=b:186792595
TEST=Ran on skyrim proto, verified that wake events show in elog
Change-Id: I529f541a8932267a8825773ddc582beafb27da63
Signed-off-by: Robert Zieba <robertzieba(a)google.com>
---
M src/mainboard/google/skyrim/mainboard.c
1 file changed, 47 insertions(+), 0 deletions(-)
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Change subject: device/xhci: Factor out `struct xhci_usb_info`
......................................................................
device/xhci: Factor out `struct xhci_usb_info`
This commit factors out `struct xhci_usb_info` from intel specific code
as it will be useful on other platforms.
BUG=b:186792595
TEST=Builds for volteer
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---
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Change subject: device/xhci: Factor out common PORTSC code
......................................................................
device/xhci: Factor out common PORTSC code
This commit factors out some code for XHCI port status values.
BUG=b:186792595
TEST=Built coreboot for volteer device
Change-Id: I045405ed224aa8f48f6f628b7d49ec6bafb450d7
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---
M src/include/device/xhci.h
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Change subject: cpu/x86/smm: Add PCI BAR store functionality
......................................................................
cpu/x86/smm: Add PCI BAR store functionality
In certain cases data within protected memmory areas like SMRAM could
be leaked or modified if an attacker remaps PCI BARs to point within
that area. This commit adds support to the existing SMM to allow storing
PCI BARs in SMRAM and then later retrieved.
BUG=b:186792595
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Change-Id: I23fb1e935dd1b89f1cc5c834cc2025f0fe5fda37
---
M src/cpu/x86/Kconfig
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A src/cpu/x86/smm/pci_bar_store.c
M src/cpu/x86/smm/smm_module_handler.c
M src/cpu/x86/smm/smm_module_loader.c
M src/include/cpu/x86/smm.h
6 files changed, 143 insertions(+), 0 deletions(-)
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Change subject: security/tpm: resolve conflicts in TSS implementations
......................................................................
security/tpm: resolve conflicts in TSS implementations
No functional changes. Just code updates to don't have any compiler or
linker errors if TSS 1.2 and TSS 2.0 were both compiled in.
Change-Id: Ia0ea5a917c46ada9fc3274f17240e12bca98db6a
Ticket: https://ticket.coreboot.org/issues/433
Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com>
---
M src/drivers/crb/tis.c
M src/security/tpm/Makefile.inc
M src/security/tpm/tspi/tspi.c
M src/security/tpm/tss.h
M src/security/tpm/tss/tcg-1.2/tss.c
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A src/security/tpm/tss/tss.c
M src/security/tpm/tss/vendor/cr50/cr50.c
M src/security/vboot/secdata_tpm.c
12 files changed, 458 insertions(+), 213 deletions(-)
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Change subject: util/inteltool: Add support for Elkhart lake
......................................................................
util/inteltool: Add support for Elkhart lake
Document: 614109, 601458
Tested on: Protectli vault_ehl (VP2420)
Signed-off-by: Kacper Stojek <kacper.stojek(a)3mdeb.com>
Change-Id: I54948741082ca1072642046f64539a4c15ddb578
---
M util/inteltool/gpio.c
M util/inteltool/gpio_groups.c
A util/inteltool/gpio_names/elkhartlake.h
M util/inteltool/inteltool.c
M util/inteltool/inteltool.h
M util/inteltool/pcr.c
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Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68790 )
Change subject: device/mmio: add clr/setbitsXp macros
......................................................................
Patch Set 4:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/68790/comment/4e56aaf6_98d1e563
PS2, Line 9: pendant
> pendant is also a synonym for `counterpart`
Done
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Change subject: acpigen: export acpigen_write_field_name
......................................................................
Patch Set 4:
(1 comment)
File src/include/acpi/acpigen.h:
https://review.coreboot.org/c/coreboot/+/68787/comment/a89c75bb_482b6502
PS2, Line 523: void acpigen_write_field_name(const char *name, uint32_t size);
> I wrote a suggestion on the patch using this to avoid duplicating most of acpigen_write_field. […]
see https://review.coreboot.org/c/coreboot/+/68791/4..8/src/ec/clevo/it5570e/ss…
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