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Change subject: soc/xeon_sp: Add weak mainboard_ewl_check for EWL check after FSP-M
......................................................................
Patch Set 1: Code-Review+2
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Change subject: checkpatch: add Co-authored-by to signature list
......................................................................
Patch Set 1:
This change is ready for review.
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Change subject: inc/dev: Add some PCIe DPC/AER definitions
......................................................................
Patch Set 2: Code-Review+1
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/69106/comment/78200a9b_9fe02949
PS2, Line 7: inc/dev: Add some PCIe DPC/AER definitions
I would prefer not to short it "include/device/pci_def.h:"
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Change subject: util/inteltool: Add support for Elkhart lake
......................................................................
Patch Set 8:
(10 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/68474/comment/ac4698dd_69042625
PS1, Line 10:
> It is not there. […]
I've done it here in the gerrit editor, so maybe I really did not push this change. Now it is here though.
File util/inteltool/gpio_names/elkhartlake.h:
https://review.coreboot.org/c/coreboot/+/68474/comment/167e7087_1c976490
PS6, Line 447: "VGPIO_0", "n/a",
: "VGPIO_4", "n/a",
: "VGPIO_5", "n/a",
: "VGPIO_6", "n/a",
: "VGPIO_7", "n/a",
: "VGPIO_8", "n/a",
: "VGPIO_9", "n/a",
: "VGPIO_10", "n/a",
: "VGPIO_11", "n/a",
: "VGPIO_12", "n/a",
: "VGPIO_13", "n/a",
: "VGPIO_18", "n/a",
: "VGPIO_19", "n/a",
: "VGPIO_20", "n/a",
: "VGPIO_21", "n/a",
: "VGPIO_22", "n/a",
: "VGPIO_23", "n/a",
: "VGPIO_24", "n/a",
: "VGPIO_25", "n/a",
: "VGPIO_30", "n/a",
: "VGPIO_31", "n/a",
: "VGPIO_32", "n/a",
: "VGPIO_33", "n/a",
: "VGPIO_34", "n/a",
: "VGPIO_35", "n/a",
: "VGPIO_36", "n/a",
: "VGPIO_37", "n/a",
: "VGPIO_39", "n/a",
> I guess VGPIOs have only 1 native function which is VGPIOx, so I would suggest to change it to: […]
Done
https://review.coreboot.org/c/coreboot/+/68474/comment/2302c6d8_bd38cf18
PS6, Line 486: "VGPIO_USB_0", "n/a",
: "VGPIO_USB_1", "n/a",
: "VGPIO_USB_2", "n/a",
: "VGPIO_USB_3", "n/a",
> "VGPIO_USB_0", "VGPIO_USB_0", […]
Done
https://review.coreboot.org/c/coreboot/+/68474/comment/d62eed63_9680c7c7
PS6, Line 501: &elkhartlake_pch_group_t,
: &elkhartlake_pch_group_g,
> Bad indent
Done
https://review.coreboot.org/c/coreboot/+/68474/comment/9f0f3853_7946c524
PS6, Line 528: &elkhartlake_pch_group_gpd,
> Bad indent
Done
https://review.coreboot.org/c/coreboot/+/68474/comment/d465aeae_ad575495
PS6, Line 539: &elkhartlake_pch_group_s,
: &elkhartlake_pch_group_a,
: &elkhartlake_pch_group_vgpio_usb,
> Bad indent
Done
https://review.coreboot.org/c/coreboot/+/68474/comment/13658ff6_1ce37538
PS6, Line 552: &elkhartlake_pch_group_c,
: &elkhartlake_pch_group_f,
: &elkhartlake_pch_group_e,
> Bad indent
Done
https://review.coreboot.org/c/coreboot/+/68474/comment/764b5b11_40f6de4b
PS6, Line 565: &elkhartlake_pch_group_r,
> Bad indent
Done
File util/inteltool/gpio_names/elkhartlake.h:
https://review.coreboot.org/c/coreboot/+/68474/comment/a08f3959_2c4759ad
PS1, Line 150: "GP_DSW07","n/a",
> Let's make it RSVD
Done
File util/inteltool/inteltool.h:
https://review.coreboot.org/c/coreboot/+/68474/comment/ca62531f_36ed672f
PS6, Line 300: #define PCI_DEVICE_ID_INTEL_EHL 0x4b00
> One TAB more? It seems not to be aligned properly with above defines […]
For now I've just added the tab and left it at that.
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Hello Arthur Heymans, build bot (Jenkins), Martin Roth, Karthik Ramasubramanian, Felix Held,
I'd like you to reexamine a change. Please visit
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Change subject: cpu/x86/smm: Add PCI BAR store functionality
......................................................................
cpu/x86/smm: Add PCI BAR store functionality
In certain cases data within protected memmory areas like SMRAM could
be leaked or modified if an attacker remaps PCI BARs to point within
that area. This commit adds support to the existing SMM to allow storing
PCI BARs in SMRAM and then later retrieved.
BUG=b:186792595
Signed-off-by: Robert Zieba <robertzieba(a)google.com>
Change-Id: I23fb1e935dd1b89f1cc5c834cc2025f0fe5fda37
---
M src/cpu/x86/Kconfig
M src/cpu/x86/smm/Makefile.inc
A src/cpu/x86/smm/pci_bar_store.c
M src/cpu/x86/smm/smm_module_handler.c
M src/cpu/x86/smm/smm_module_loader.c
M src/include/cpu/x86/smm.h
6 files changed, 143 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/67931/6
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Change subject: device/xhci: Factor out common PORTSC code
......................................................................
device/xhci: Factor out common PORTSC code
This commit factors out some code for XHCI port status values.
BUG=b:186792595
TEST=Built coreboot for volteer device
Change-Id: I045405ed224aa8f48f6f628b7d49ec6bafb450d7
Signed-off-by: Robert Zieba <robertzieba(a)google.com>
---
M src/include/device/xhci.h
M src/soc/intel/common/block/xhci/elog.c
2 files changed, 57 insertions(+), 39 deletions(-)
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Change subject: device/xhci: Factor out `struct xhci_usb_info`
......................................................................
device/xhci: Factor out `struct xhci_usb_info`
This commit factors out `struct xhci_usb_info` from intel specific code
as it will be useful on other platforms.
BUG=b:186792595
TEST=Builds for volteer
Change-Id: I5b4cc6268f072c6948f11c7498a564d7a5c0a190
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Change subject: mb/google/skyrim: Store XHCI PCI BARs
......................................................................
mb/google/skyrim: Store XHCI PCI BARs
This commit implements `smm_mainboard_pci_bar_store_init` to store the
BARs for XHCI devices. These stored BARs are later used by the elog code
to log XHCI wake events.
Example elog contents:
```
244 | 2022-10-11 15:49:24 | S0ix Enter
245 | 2022-10-11 15:49:29 | S0ix Exit
246 | 2022-10-11 15:49:29 | Wake Source | GPE # | 31
247 | 2022-10-11 15:49:29 | Wake Source | PME - XHCI (USB 2.0 port) | 256
248 | 2022-10-11 15:50:08 | S0ix Enter
249 | 2022-10-11 15:50:16 | S0ix Exit
250 | 2022-10-11 15:50:16 | Wake Source | GPE # | 31
251 | 2022-10-11 15:50:16 | Wake Source | PME - XHCI (USB 2.0 port) | 257
```
BUG=b:186792595
TEST=Ran on skyrim proto, verified that wake events show in elog
Change-Id: I529f541a8932267a8825773ddc582beafb27da63
Signed-off-by: Robert Zieba <robertzieba(a)google.com>
---
M src/mainboard/google/skyrim/mainboard.c
1 file changed, 47 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/68325/5
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Change subject: mb/google/guybrush: Store XHCI BARs
......................................................................
mb/google/guybrush: Store XHCI BARs
This commit implements `smm_mainboard_pci_bar_store_init` to store the
BARs for XHCI devices. These stored BARs are later used by the elog code
to log XHCI wake events.
Example elog contents:
```
250 | 2022-10-11 16:04:49 | S0ix Enter
251 | 2022-10-11 16:04:53 | S0ix Exit
252 | 2022-10-11 16:04:53 | Wake Source | GPE # | 31
253 | 2022-10-11 16:04:53 | Wake Source | PME - XHCI (USB 2.0 port) | 1
254 | 2022-10-11 16:05:24 | S0ix Enter
255 | 2022-10-11 16:05:27 | S0ix Exit
256 | 2022-10-11 16:05:27 | Wake Source | GPE # | 31
257 | 2022-10-11 16:05:27 | Wake Source | PME - XHCI (USB 2.0 port) | 257
```
BRANCH=guybrush
BUG=b:186792595
TEST=Ran on nipperkin, verified that XHCI wake events show up in elog
Change-Id: I1d0911df9e3102791bf7b5723ac38e2ba82a9db6
Signed-off-by: Robert Zieba <robertzieba(a)google.com>
---
M src/mainboard/google/guybrush/mainboard.c
1 file changed, 47 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/68326/5
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