coreboot-gerrit November 2022

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: soc/xeon_sp: Add weak mainboard_ewl_check for EWL check after FSP-M
by 9elements QA (Code Review) 04 Nov '22

04 Nov '22

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69143 ) Change subject: soc/xeon_sp: Add weak mainboard_ewl_check for EWL check after FSP-M ...................................................................... Patch Set 3: Automatic boot test returned (PASS/FAIL/TOTAL): 14 / 2 / 16 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/133762 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/133761 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/133760 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/133759 FAIL: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/133758 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/133757 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/133756 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/133755 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/133754 FAIL: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/133753 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/133752 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/133751 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/133750 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/133749 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/133748 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/133747 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/69143 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6f542e71d20307397c398fd757d9408438f681ed Gerrit-Change-Number: 69143 Gerrit-PatchSet: 3 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Fri, 04 Nov 2022 16:27:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/xeon_sp/cpx: Add get_ewl_hob() utility function
by Tim Crawford (Code Review) 04 Nov '22

04 Nov '22

Attention is currently required from: Marc Jones, Johnny Lin, Angel Pons, Felix Held. Tim Crawford has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69144 ) Change subject: soc/intel/xeon_sp/cpx: Add get_ewl_hob() utility function ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h:8:10: fatal error: hob_enhancedwarningloglib.h: No such file or directory 8 | #include <hob_enhancedwarningloglib.h> | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ compilation terminated. -- To view, visit https://review.coreboot.org/c/coreboot/+/69144 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8f949e9c881099c3723fca056e2c4732ca8b64cf Gerrit-Change-Number: 69144 Gerrit-PatchSet: 3 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 04 Nov 2022 16:19:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: security/vboot: Update build rules using x86 SHA extension
by Raul Rangel (Code Review) 04 Nov '22

04 Nov '22

Attention is currently required from: Julius Werner, Karthik Ramasubramanian. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68953 ) Change subject: security/vboot: Update build rules using x86 SHA extension ...................................................................... Patch Set 3: (1 comment) File src/security/vboot/Makefile.inc: https://review.coreboot.org/c/coreboot/+/68953/comment/69478388_c09e2dea PS3, Line 24: Would it be easier to read an reason about if you pulled the logic outside of the rule? ``` ifeq(..) VBOOT_X86_SHA_EXT_$(1) := ... else ``` Then in the rule just use: ``` X86_SHA_EXT="$(VBOOT_X86_SHA_EXT_$(1))" ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/68953 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4f388e963eb82990cda41d3880e66ad937334908 Gerrit-Change-Number: 68953 Gerrit-PatchSet: 3 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 04 Nov 2022 16:09:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: common/acpi/dptc: Implement DTTS Proposal
by Raul Rangel (Code Review) 04 Nov '22

04 Nov '22

Attention is currently required from: Jason Nien, EricKY Cheng, Matt DeVillier, Martin Roth, Tim Van Patten, Eric Peers, Jason Glenesk, Caveh Jalali, Tim Wawrzynczak, Fred Reitberger, Karthikeyan Ramasubramanian, Boris Mittelberg, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68471 ) Change subject: common/acpi/dptc: Implement DTTS Proposal ...................................................................... Patch Set 30: (1 comment) File src/mainboard/google/skyrim/variants/winterhold/DTTS.asl: PS30: > I think you can move this into "mb/google/skyrim/variants/winterhold/acpi/dtts. […] Hrmm, thinking about this more, the parameters were defined as part of the mdn/chip.h and are used in the mdn/root_complex.c. So I guess this code should be part of the chipset. So move it to src/soc/amd/mendocino/acpi/dtts.asl. Then add the `#include "dtts.asl"` into the `soc.asl`: https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/master/sr… You could maybe modify the PNOT code to look like so: ``` Method (PNOT) { /* Report AC/DC state to ALIB using WAL1() */ \WAL1 () If (CondRefOf (\_SB.DTTS)) { \_SB.DTTS() } Else If (CondRefOf (\_SB.DPTC)) { \_SB.DPTC() } } ``` Or if you didn't want to copy/paste the DTPC low battery code/tablet code, we could make `DPTC` return 0 when nothing is changed, and 1 when it does change something, so we could have: ``` Method (PNOT) { /* Report AC/DC state to ALIB using WAL1() */ \WAL1 () If (CondRefOf (\_SB.DPTC)) { If (!\_SB.DPTC() && CondRefOf (\_SB.DTTS)) { \_SB.DTTS() } } } ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/68471 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I866e5e497e2936984e713029b5f0b6d54cbc9622 Gerrit-Change-Number: 68471 Gerrit-PatchSet: 30 Gerrit-Owner: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: LeilaCY Lin <leilacy_lin(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Eric Peers <epeers(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 04 Nov 2022 15:54:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/amd/mendocino: Enhance DPTC_INPUT to support 13 DPTC thermal para...
by Raul Rangel (Code Review) 04 Nov '22

04 Nov '22

Attention is currently required from: Jason Glenesk, EricKY Cheng, Matt DeVillier, Tim Van Patten, Fred Reitberger, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68649 ) Change subject: soc/amd/mendocino: Enhance DPTC_INPUT to support 13 DPTC thermal parameters ...................................................................... Patch Set 20: (1 comment) File src/soc/amd/mendocino/root_complex.c: https://review.coreboot.org/c/coreboot/+/68649/comment/f3877970_91076827 PS20, Line 269: /* Normal mode DPTC values. */ : struct dptc_input default_input = DPTC_INPUTS( : config->thermctl_limit_degreeC, : config->sustained_power_limit_mW, : config->slow_ppt_time_constant_s, : config->fast_ppt_limit_mW, : config->slow_ppt_limit_mW, : config->vrm_current_limit_mA, : config->vrm_maximum_current_limit_mA, : config->vrm_soc_current_limit_mA, : config->stt_min_limit, : config->stt_m1, : config->stt_m2, : config->stt_c_apu, : config->stt_skin_temp_apu); : acpigen_write_alib_dptc_default((uint8_t *)&default_input, sizeof(default_input)); : : /* Low/No Battery */ : struct dptc_input no_battery_input = DPTC_INPUTS( : config->thermctl_limit_degreeC, : config->sustained_power_limit_mW, : config->slow_ppt_time_constant_s, : config->fast_ppt_limit_mW, : config->slow_ppt_limit_mW, : config->vrm_current_limit_throttle_mA, : config->vrm_maximum_current_limit_throttle_mA, : config->vrm_soc_current_limit_throttle_mA, : config->stt_min_limit, : config->stt_m1, : config->stt_m2, : config->stt_c_apu, : config->stt_skin_temp_apu); : acpigen_write_alib_dptc_no_battery((uint8_t *)&no_battery_input, : sizeof(no_battery_input)); Delete these and use the ones defined below instead. -- To view, visit https://review.coreboot.org/c/coreboot/+/68649 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6d6a00f0eca0b0941860b9bc75da41d7a10d60e8 Gerrit-Change-Number: 68649 Gerrit-PatchSet: 20 Gerrit-Owner: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 04 Nov 2022 15:44:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: ec/google/chromec: Expand EC share memory for DTTS
by Raul Rangel (Code Review) 04 Nov '22

04 Nov '22

Attention is currently required from: Jason Nien, EricKY Cheng, Caveh Jalali, Isaac Lee, Paul Menzel, Jon Murphy, Tim Wawrzynczak, Martin Roth, Eric Peers, Moises Garcia, Karthikeyan Ramasubramanian, Boris Mittelberg. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68077 ) Change subject: ec/google/chromec: Expand EC share memory for DTTS ...................................................................... Patch Set 24: Code-Review+2 (1 comment) Patchset: PS24: If you place this at the beginning of the stack we could merge it -- To view, visit https://review.coreboot.org/c/coreboot/+/68077 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I37b3a0d8f6546361c8d5501e98e3e1b0d814fce3 Gerrit-Change-Number: 68077 Gerrit-PatchSet: 24 Gerrit-Owner: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Isaac Lee <isaaclee(a)google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Moises Garcia <moisesgarcia(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Isaac Lee <isaaclee(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Eric Peers <epeers(a)google.com> Gerrit-Attention: Moises Garcia <moisesgarcia(a)google.com> Gerrit-Attention: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Fri, 04 Nov 2022 15:42:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/mediatek/mt8188: Disable input-gating for big-core SRAM
by 9elements QA (Code Review) 04 Nov '22

04 Nov '22

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69089 ) Change subject: soc/mediatek/mt8188: Disable input-gating for big-core SRAM ...................................................................... Patch Set 13: Automatic boot test returned (PASS/FAIL/TOTAL): 15 / 1 / 16 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/133745 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/133744 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/133743 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/133742 FAIL: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/133741 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/133740 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/133739 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/133738 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/133737 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/133736 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/133735 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/133734 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/133733 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/133732 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/133731 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/133730 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/69089 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd68fe9362587955cdb8598c4cc5c2d0eefe53ca Gerrit-Change-Number: 69089 Gerrit-PatchSet: 13 Gerrit-Owner: Liju-Clr Chen <liju-clr.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Fri, 04 Nov 2022 15:41:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: common/acpi/dptc: Implement DTTS Proposal
by Raul Rangel (Code Review) 04 Nov '22

04 Nov '22

Attention is currently required from: Jason Nien, EricKY Cheng, Matt DeVillier, Martin Roth, Tim Van Patten, Eric Peers, Jason Glenesk, Caveh Jalali, Tim Wawrzynczak, Fred Reitberger, Karthikeyan Ramasubramanian, Boris Mittelberg, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68471 ) Change subject: common/acpi/dptc: Implement DTTS Proposal ...................................................................... Patch Set 30: (4 comments) File src/mainboard/google/skyrim/dsdt.asl: https://review.coreboot.org/c/coreboot/+/68471/comment/024dc056_6986acbb PS30, Line 18: variants/winterhold/DTTS.asl Add the following include line here: https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/master/sr… ``` CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/acpi ``` Then just do `#include <dtts.asl>` File src/mainboard/google/skyrim/variants/winterhold/DTTS.asl: PS30: I think you can move this into "mb/google/skyrim/variants/winterhold/acpi/dtts.asl" https://review.coreboot.org/c/coreboot/+/68471/comment/a4db1f67_8b0ac658 PS30, Line 45: LGreaterEqual Just use `>=` https://review.coreboot.org/c/coreboot/+/68471/comment/f0c7fe19_94d00887 PS30, Line 46: ) nit: don't think you need the extra `()` -- To view, visit https://review.coreboot.org/c/coreboot/+/68471 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I866e5e497e2936984e713029b5f0b6d54cbc9622 Gerrit-Change-Number: 68471 Gerrit-PatchSet: 30 Gerrit-Owner: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: LeilaCY Lin <leilacy_lin(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Eric Peers <epeers(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 04 Nov 2022 15:38:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/prodrive/atlas: Add IBECC Kconfig option
by Felix Held (Code Review) 04 Nov '22

04 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68783 ) Change subject: mb/prodrive/atlas: Add IBECC Kconfig option ...................................................................... mb/prodrive/atlas: Add IBECC Kconfig option Add an option on Atlas to enable IBECC (In Band Error Correction Code), which is currently needed for endurance testing. Test: start atlas mainboard with Linux. See in dmesg that IBECC (EDAC igen6) driver is loaded. Inject a fake error via debugfs and see in dmesg that Linux handles it. Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Change-Id: I71ee2401136e2dc70b3164db6c99af03a3e1f346 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68783 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> --- M src/mainboard/prodrive/atlas/Kconfig M src/mainboard/prodrive/atlas/devicetree.cb 2 files changed, 30 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Lean Sheng Tan: Looks good to me, approved diff --git a/src/mainboard/prodrive/atlas/Kconfig b/src/mainboard/prodrive/atlas/Kconfig index f986a2d..814c1e0 100644 --- a/src/mainboard/prodrive/atlas/Kconfig +++ b/src/mainboard/prodrive/atlas/Kconfig @@ -19,6 +19,13 @@ bool "Enable SaGv" default y +config ATLAS_ENABLE_IBECC + bool "Enable IBECC" + help + Enables In Band Error Correction Code. It's only needed for endurance testing + and therefore not always required. + default n + config MAINBOARD_FAMILY string default "PRODRIVE_ATLAS_SERIES" diff --git a/src/mainboard/prodrive/atlas/devicetree.cb b/src/mainboard/prodrive/atlas/devicetree.cb index 6e795a7..0d91bb6 100644 --- a/src/mainboard/prodrive/atlas/devicetree.cb +++ b/src/mainboard/prodrive/atlas/devicetree.cb @@ -47,6 +47,9 @@ register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC1)" + register "ibecc.enable" = "CONFIG(ATLAS_ENABLE_IBECC)" + register "ibecc.mode" = "CONFIG(ATLAS_ENABLE_IBECC) ? IBECC_MODE_ALL : IBECC_MODE_NONE" + register "sata_salp_support" = "1" register "sata_ports_enable" = "{ -- To view, visit https://review.coreboot.org/c/coreboot/+/68783 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I71ee2401136e2dc70b3164db6c99af03a3e1f346 Gerrit-Change-Number: 68783 Gerrit-PatchSet: 4 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: soc/intel/alderlake: Add IBECC
by Felix Held (Code Review) 04 Nov '22

04 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68756 ) Change subject: soc/intel/alderlake: Add IBECC ...................................................................... soc/intel/alderlake: Add IBECC Add In Band Error Correction Code to Alderlake SOC's. It's currently needed and tested for the Prodrive Atlas mainboard. After enabling it in the UPD, FSP-M takes care of enabling IBECC. Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Change-Id: I9cc2ed6defa1223aa422b9b0d8145f8f8b3dd12e Reviewed-on: https://review.coreboot.org/c/coreboot/+/68756 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/romstage/fsp_params.c 2 files changed, 58 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index 46721b0..a732fe6 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -20,6 +20,25 @@ #include <soc/vr_config.h> #include <stdint.h> +/* Define config parameters for In-Band ECC (IBECC). */ +#define MAX_IBECC_REGIONS 8 + +/* In-Band ECC Operation Mode */ +enum ibecc_mode { + IBECC_MODE_PER_REGION, + IBECC_MODE_NONE, + IBECC_MODE_ALL +}; + +struct ibecc_config { + bool enable; + enum ibecc_mode mode; + bool range_enable[MAX_IBECC_REGIONS]; + uint16_t range_base[MAX_IBECC_REGIONS]; + uint16_t range_mask[MAX_IBECC_REGIONS]; + /* add ECC error injection if needed by a mainboard */ +}; + /* Types of different SKUs */ enum soc_intel_alderlake_power_limits { ADL_P_142_242_282_15W_CORE, @@ -273,6 +292,9 @@ /* TCC activation offset */ uint32_t tcc_offset; + /* In-Band ECC (IBECC) configuration */ + struct ibecc_config ibecc; + /* System Agent dynamic frequency support. Only effects ULX/ULT CPUs. * When enabled memory will be training at two different frequencies. * 0:Disabled, 1:FixedPoint0, 2:FixedPoint1, 3:FixedPoint2, diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c index c0bdb0d..b603a42 100644 --- a/src/soc/intel/alderlake/romstage/fsp_params.c +++ b/src/soc/intel/alderlake/romstage/fsp_params.c @@ -342,6 +342,24 @@ m_cfg->CpuCrashLogEnable = m_cfg->CpuCrashLogDevice; } +static void fill_fspm_ibecc_params(FSP_M_CONFIG *m_cfg, + const struct soc_intel_alderlake_config *config) +{ + /* In-Band ECC configuration */ + if (config->ibecc.enable) { + m_cfg->Ibecc = config->ibecc.enable; + m_cfg->IbeccOperationMode = config->ibecc.mode; + if (m_cfg->IbeccOperationMode == IBECC_MODE_PER_REGION) { + FSP_ARRAY_LOAD(m_cfg->IbeccProtectedRangeEnable, + config->ibecc.range_enable); + FSP_ARRAY_LOAD(m_cfg->IbeccProtectedRangeBase, + config->ibecc.range_base); + FSP_ARRAY_LOAD(m_cfg->IbeccProtectedRangeMask, + config->ibecc.range_mask); + } + } +} + static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const struct soc_intel_alderlake_config *config) { @@ -362,6 +380,7 @@ fill_fspm_usb4_params, fill_fspm_vtd_params, fill_fspm_trace_params, + fill_fspm_ibecc_params, }; for (size_t i = 0; i < ARRAY_SIZE(fill_fspm_params); i++) -- To view, visit https://review.coreboot.org/c/coreboot/+/68756 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9cc2ed6defa1223aa422b9b0d8145f8f8b3dd12e Gerrit-Change-Number: 68756 Gerrit-PatchSet: 10 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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