coreboot-gerrit November 2022

coreboot-gerrit@coreboot.org

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7286 discussions

[M] Change in coreboot[master]: soc/qualcomm/sc7280: Add API to differentialize PRO and NON_PRO SKUs
by Venkat Thogaru (Code Review) 07 Nov '22

07 Nov '22

Attention is currently required from: Shelley Chen, Taniya Das, Paul Menzel, Julius Werner, Sudheer Amrabadi. Venkat Thogaru has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68384 ) Change subject: soc/qualcomm/sc7280: Add API to differentialize PRO and NON_PRO SKUs ...................................................................... Patch Set 12: (1 comment) File src/soc/qualcomm/sc7280/socinfo.c: https://review.coreboot.org/c/coreboot/+/68384/comment/0f17bf24_a8e8e465 PS4, Line 12: static struct chipinfo chipinfolut[] = { > Qualcomm, do you have an update on this? Sure. For readability, we have commented 'chip_id' information in latest patch-set-12 -- To view, visit https://review.coreboot.org/c/coreboot/+/68384 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9f23696384a6c1a89000292eafebd8a16c273ca Gerrit-Change-Number: 68384 Gerrit-PatchSet: 12 Gerrit-Owner: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Taniya Das <quic_tdas(a)quicinc.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Taniya Das <tdas(a)qualcomm.corp-partner.google.com> Gerrit-CC: Venkat Thogaru <thogaru(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Taniya Das <quic_tdas(a)quicinc.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Taniya Das <tdas(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-Comment-Date: Mon, 07 Nov 2022 08:34:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shelley Chen <shchen(a)google.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Taniya Das <tdas(a)qualcomm.corp-partner.google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/aldrlake: Update ME HFSTS register definition
by Sridhar Siricilla (Code Review) 07 Nov '22

07 Nov '22

Attention is currently required from: Tarun Tuli, Rizwan Qureshi. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69286 ) Change subject: soc/intel/aldrlake: Update ME HFSTS register definition ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69286 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9aeee7a3b41ad59c03391207930a253ffff19ae5 Gerrit-Change-Number: 69286 Gerrit-PatchSet: 1 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Comment-Date: Mon, 07 Nov 2022 08:20:17 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: include/spd.h: Add module type information
by Elyes Haouas (Code Review) 07 Nov '22

07 Nov '22

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69271 ) Change subject: include/spd.h: Add module type information ...................................................................... include/spd.h: Add module type information Change-Id: I7af61404d11f7e0ff5f30c42958c4dd9318538fa Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/include/spd.h 1 file changed, 13 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/69271/1 diff --git a/src/include/spd.h b/src/include/spd.h index ca78d9c..7a6e5ab 100644 --- a/src/include/spd.h +++ b/src/include/spd.h @@ -201,7 +201,7 @@ #define SPD_ECC_8BIT (1<<3) #define SPD_ECC_8BIT_LP5_DDR5 (1<<4) -/* Byte 3: Module type information */ +/* Byte 20 [5:0]: DDR2 Module type information */ enum ddr2_module_type { DDR2_SPD_RDIMM = 0x01, DDR2_SPD_UDIMM = 0x02, @@ -213,6 +213,7 @@ DDR2_SPD_MINI_UDIMM = 0x20, }; +/* Byte 3 [3:0]: DDR3 Module type information */ enum ddr3_module_type { DDR3_SPD_RDIMM = 0x01, DDR3_SPD_UDIMM = 0x02, @@ -229,6 +230,7 @@ DDR3_SPD_32B_SO_RDIMM = 0x0d, }; +/* Byte 3 [3:0]: DDR4 Module type information */ enum ddr4_module_type { DDR4_SPD_RDIMM = 0x01, DDR4_SPD_UDIMM = 0x02, -- To view, visit https://review.coreboot.org/c/coreboot/+/69271 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7af61404d11f7e0ff5f30c42958c4dd9318538fa Gerrit-Change-Number: 69271 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: soc/qualcomm/sc7280: Add API to differentialize PRO and NON_PRO SKUs
by Venkat Thogaru (Code Review) 07 Nov '22

07 Nov '22

Attention is currently required from: Taniya Das, Venkat Thogaru, Paul Menzel, Julius Werner, Sudheer Amrabadi. Venkat Thogaru has uploaded a new patch set (#12) to the change originally created by Sudheer Amrabadi. ( https://review.coreboot.org/c/coreboot/+/68384 ) Change subject: soc/qualcomm/sc7280: Add API to differentialize PRO and NON_PRO SKUs ...................................................................... soc/qualcomm/sc7280: Add API to differentialize PRO and NON_PRO SKUs The API socinfo_pro_part() returns 1 for Pro and 0 for NON_PRO SKUs. To reduce the binary footprint for chipinfo structure, change its members range from uint32_t to uint16_t. Add helper functions for reading and matching jtagid. BUG=b:248187555 TEST=Validate boards are detected correctly on PRO and NON_PRO SKUs Signed-off-by: Taniya Das <quic_tdas(a)quicinc.com> Change-Id: Id9f23696384a6c1a89000292eafebd8a16c273ca --- M src/soc/qualcomm/sc7280/include/soc/socinfo.h M src/soc/qualcomm/sc7280/socinfo.c 2 files changed, 86 insertions(+), 57 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/68384/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/68384 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9f23696384a6c1a89000292eafebd8a16c273ca Gerrit-Change-Number: 68384 Gerrit-PatchSet: 12 Gerrit-Owner: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Taniya Das <quic_tdas(a)quicinc.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Taniya Das <tdas(a)qualcomm.corp-partner.google.com> Gerrit-CC: Venkat Thogaru <thogaru(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Taniya Das <quic_tdas(a)quicinc.com> Gerrit-Attention: Venkat Thogaru <thogaru(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Taniya Das <tdas(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/intel/aldrlake: Update ME HFSTS register definition
by Subrata Banik (Code Review) 07 Nov '22

07 Nov '22

Attention is currently required from: Tarun Tuli, Rizwan Qureshi. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69286 ) Change subject: soc/intel/aldrlake: Update ME HFSTS register definition ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Can you please consider porting the CL for MTL? -- To view, visit https://review.coreboot.org/c/coreboot/+/69286 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9aeee7a3b41ad59c03391207930a253ffff19ae5 Gerrit-Change-Number: 69286 Gerrit-PatchSet: 1 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-CC: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Comment-Date: Mon, 07 Nov 2022 08:09:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/aldrlake: Update ME HFSTS register definition
by Subrata Banik (Code Review) 07 Nov '22

07 Nov '22

Attention is currently required from: Tarun Tuli, Rizwan Qureshi. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69286 ) Change subject: soc/intel/aldrlake: Update ME HFSTS register definition ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Patchset: PS1: Looks like those bit-field changes are not that impactful to the me.c file (i'm no one is actually consuming those bit-fields directly. -- To view, visit https://review.coreboot.org/c/coreboot/+/69286 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9aeee7a3b41ad59c03391207930a253ffff19ae5 Gerrit-Change-Number: 69286 Gerrit-PatchSet: 1 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-CC: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Comment-Date: Mon, 07 Nov 2022 08:08:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: security/vboot: Fix different size operands in bitwise operation
by Yu-Ping Wu (Code Review) 07 Nov '22

07 Nov '22

Attention is currently required from: V Sowmya, Shahina Shaik, Haribalaraman Ramasubramanian, Paul Menzel, Sridhar Siricilla, Julius Werner, Balaji Manigandan. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69221 ) Change subject: security/vboot: Fix different size operands in bitwise operation ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: Please see Julius' comment in https://chromium-review.googlesource.com/c/chromiumos/platform/vboot_refere…: > Let's not put these casts here. They are unnecessary for now, because we haven't allocated bit 32 or higher yet, so they'll always be 0 anyway, and once we do we'll have to stop using an enum anyway because enums can't be larger than 32-bit (I think?). So at that point we'll have to represent them as macros or something and then we should just define them ULL to begin with. > > We definitely don't want to be in a situation where you have to put this cast here or otherwise something is gonna silently break (because sooner or later someone would make that mistake), so we wouldn't build a system that requires that. Then there's no point in having the casts here either. (If you want to be extra proactive, feel free to already rewrite the field definitions now.) -- To view, visit https://review.coreboot.org/c/coreboot/+/69221 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifecd5de843bd0229c0cab758d4a641889b4bffd6 Gerrit-Change-Number: 69221 Gerrit-PatchSet: 2 Gerrit-Owner: Shahina Shaik <shahina.shaik(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Shahina Shaik <shahina.shaik(a)intel.corp-partner.google.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Shahina Shaik <shahina.shaik(a)intel.com> Gerrit-Attention: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Shahina Shaik <shahina.shaik(a)intel.corp-partner.google.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Comment-Date: Mon, 07 Nov 2022 08:08:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel: Use `PWRMBASE` over static `Index 0` for PMC
by Werner Zeh (Code Review) 07 Nov '22

07 Nov '22

Attention is currently required from: Tarun Tuli, Subrata Banik, Kapil Porwal, Arthur Heymans, Lean Sheng Tan. Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69227 ) Change subject: soc/intel: Use `PWRMBASE` over static `Index 0` for PMC ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69227 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iee2523876a8045e70effd5824afc327d1113038b Gerrit-Change-Number: 69227 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Mon, 07 Nov 2022 08:06:50 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/aldrlake: Update ME HFSTS register definition
by Rizwan Qureshi (Code Review) 07 Nov '22

07 Nov '22

Rizwan Qureshi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69286 ) Change subject: soc/intel/aldrlake: Update ME HFSTS register definition ...................................................................... soc/intel/aldrlake: Update ME HFSTS register definition Update AlderLake CSME HFSTS registers definitions as per https://cdrdv2.intel.com/v1/dl/getContent/627331 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Change-Id: I9aeee7a3b41ad59c03391207930a253ffff19ae5 --- M src/soc/intel/alderlake/include/soc/me.h M src/soc/intel/alderlake/me.c 2 files changed, 21 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/69286/1 diff --git a/src/soc/intel/alderlake/include/soc/me.h b/src/soc/intel/alderlake/include/soc/me.h index 8eea095..e094af6 100644 --- a/src/soc/intel/alderlake/include/soc/me.h +++ b/src/soc/intel/alderlake/include/soc/me.h @@ -35,11 +35,9 @@ struct { u32 reserved_0: 4; u32 fw_sku: 3; - u32 reserved_7: 2; - u32 reserved_9: 2; - u32 resered_11: 3; - u32 resered_14: 16; - u32 reserved_30: 2; + u32 reserved_7_10: 4; + u32 rpmc_status: 3; + u32 resered_14_31: 18; } __packed fields; }; #endif /* _ALDERLAKE_ME_H_ */ diff --git a/src/soc/intel/alderlake/me.c b/src/soc/intel/alderlake/me.c index 31b09da..a965807 100644 --- a/src/soc/intel/alderlake/me.c +++ b/src/soc/intel/alderlake/me.c @@ -23,7 +23,8 @@ uint32_t me_power_gate : 1; uint32_t ipu_needed : 1; uint32_t forced_safe_boot : 1; - uint32_t rsvd1 : 2; + uint32_t rsvd1 : 1; + uint32_t cse_to_be_disabled : 1; uint32_t listener_change : 1; uint32_t status_data : 8; uint32_t current_pmevent : 4; @@ -58,10 +59,7 @@ uint32_t acm_done_sts : 1; uint32_t timeout_count : 7; uint32_t scrtm_indicator : 1; - uint32_t inc_boot_guard_acm : 4; - uint32_t inc_key_manifest : 4; - uint32_t inc_boot_policy : 4; - uint32_t rsvd0 : 2; + uint32_t rsvd0 : 14; uint32_t start_enforcement : 1; } __packed fields; }; @@ -78,9 +76,8 @@ uint32_t error_enforce_policy : 2; uint32_t measured_boot : 1; uint32_t verified_boot : 1; - uint32_t boot_guard_acmsvn : 4; - uint32_t kmsvn : 4; - uint32_t bpmsvn : 4; + uint32_t rsvd1 : 11; + uint32_t manuf_lock : 1; uint32_t key_manifest_id : 4; uint32_t boot_policy_status : 1; uint32_t error : 1; -- To view, visit https://review.coreboot.org/c/coreboot/+/69286 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9aeee7a3b41ad59c03391207930a253ffff19ae5 Gerrit-Change-Number: 69286 Gerrit-PatchSet: 1 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: cbfstool: Fix possible memory leak
by Yu-Ping Wu (Code Review) 07 Nov '22

07 Nov '22

Attention is currently required from: V Sowmya, Shahina Shaik, Haribalaraman Ramasubramanian, Sridhar Siricilla, Balaji Manigandan. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69220 ) Change subject: cbfstool: Fix possible memory leak ...................................................................... Patch Set 5: (2 comments) File util/cbfstool/cbfstool.c: https://review.coreboot.org/c/coreboot/+/69220/comment/0196b9be_6b410bda PS4, Line 773: header_offset > Fixed the indent as suggested. Nothing seems to be changed? File util/cbfstool/common.c: https://review.coreboot.org/c/coreboot/+/69220/comment/281f1aa0_c6673df9 PS4, Line 40: } > In line no:30, strdup is using malloc internally to allocate memory for the buffer->name, which has […] I meant to return -1 *after* line #40, and return 0 in line #42. -- To view, visit https://review.coreboot.org/c/coreboot/+/69220 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I01c4643d1e671d9bd9971ac6db8031634fffd61e Gerrit-Change-Number: 69220 Gerrit-PatchSet: 5 Gerrit-Owner: Shahina Shaik <shahina.shaik(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Shahina Shaik <shahina.shaik(a)intel.corp-partner.google.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Shahina Shaik <shahina.shaik(a)intel.com> Gerrit-Attention: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Shahina Shaik <shahina.shaik(a)intel.corp-partner.google.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Comment-Date: Mon, 07 Nov 2022 07:57:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shahina Shaik <shahina.shaik(a)intel.corp-partner.google.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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coreboot-gerrit November 2022