coreboot-gerrit November 2022

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[M] Change in coreboot[master]: mb/google/{eve,glados}: Use <spd_bin.h>
by Elyes Haouas (Code Review) 07 Nov '22

07 Nov '22

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69273 ) Change subject: mb/google/{eve,glados}: Use <spd_bin.h> ...................................................................... mb/google/{eve,glados}: Use <spd_bin.h> Change-Id: I3978d100ad1b763d7318d261cd7825ce2ac4ba97 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/mainboard/google/eve/romstage.c M src/mainboard/google/eve/spd/spd.c M src/mainboard/google/eve/spd/spd.h M src/mainboard/google/glados/romstage.c M src/mainboard/google/glados/spd/spd.c M src/mainboard/google/glados/spd/spd.h 6 files changed, 35 insertions(+), 42 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/69273/1 diff --git a/src/mainboard/google/eve/romstage.c b/src/mainboard/google/eve/romstage.c index f3c0f11..43021f1 100644 --- a/src/mainboard/google/eve/romstage.c +++ b/src/mainboard/google/eve/romstage.c @@ -34,7 +34,7 @@ mem_cfg->MemorySpdPtr00 = mainboard_get_spd_data(); mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00; - mem_cfg->MemorySpdDataLen = SPD_LEN; + mem_cfg->MemorySpdDataLen = SPD_PAGE_LEN; /* Limit K4EBE304EB-EGCF memory to 1600MHz for stability */ if (board_id() < 6 && mainboard_get_spd_index() == 5) { diff --git a/src/mainboard/google/eve/spd/spd.c b/src/mainboard/google/eve/spd/spd.c index e9405f0..0d0c7b6 100644 --- a/src/mainboard/google/eve/spd/spd.c +++ b/src/mainboard/google/eve/spd/spd.c @@ -19,15 +19,15 @@ const int spd_ranks[8] = { 1, 2, 3, 4, -1, -1, -1, -1 }; const int spd_devw[8] = { 4, 8, 16, 32, -1, -1, -1, -1 }; const int spd_busw[8] = { 8, 16, 32, 64, -1, -1, -1, -1 }; - char spd_name[SPD_PART_LEN+1] = { 0 }; + char spd_name[DDR3_SPD_PART_LEN+1] = { 0 }; int banks = spd_banks[(spd[SPD_DENSITY_BANKS] >> 4) & 7]; int capmb = spd_capmb[spd[SPD_DENSITY_BANKS] & 7] * 256; int rows = spd_rows[(spd[SPD_ADDRESSING] >> 3) & 7]; int cols = spd_cols[spd[SPD_ADDRESSING] & 7]; - int ranks = spd_ranks[(spd[SPD_ORGANIZATION] >> 3) & 7]; - int devw = spd_devw[spd[SPD_ORGANIZATION] & 7]; - int busw = spd_busw[spd[SPD_BUS_DEV_WIDTH] & 7]; + int ranks = spd_ranks[(spd[DDR3_ORGANIZATION] >> 3) & 7]; + int devw = spd_devw[spd[DDR3_ORGANIZATION] & 7]; + int busw = spd_busw[spd[DDR3_BUS_DEV_WIDTH] & 7]; /* Module type */ printk(BIOS_INFO, "SPD: module type is "); @@ -35,7 +35,7 @@ case SPD_DRAM_DDR3: printk(BIOS_INFO, "DDR3\n"); break; - case SPD_DRAM_LPDDR3: + case SPD_DRAM_LPDDR3_INTEL: printk(BIOS_INFO, "LPDDR3\n"); break; default: @@ -44,8 +44,8 @@ } /* Module Part Number */ - memcpy(spd_name, &spd[SPD_PART_OFF], SPD_PART_LEN); - spd_name[SPD_PART_LEN] = 0; + memcpy(spd_name, &spd[DDR3_SPD_PART_OFF], DDR3_SPD_PART_LEN); + spd_name[DDR3_SPD_PART_LEN] = 0; printk(BIOS_INFO, "SPD: module part is %s\n", spd_name); printk(BIOS_INFO, @@ -87,16 +87,16 @@ die("SPD data not found."); /* make sure we have at least one SPD in the file. */ - if (spd_file_len < SPD_LEN) + if (spd_file_len < SPD_PAGE_LEN) die("Missing SPD data."); /* Make sure we did not overrun the buffer */ - if (spd_file_len < ((spd_index + 1) * SPD_LEN)) { + if (spd_file_len < ((spd_index + 1) * SPD_PAGE_LEN)) { printk(BIOS_ERR, "SPD index override to 1 - old hardware?\n"); spd_index = 1; } - spd_index *= SPD_LEN; + spd_index *= SPD_PAGE_LEN; mainboard_print_spd_info((uint8_t *)(spd_file + spd_index)); return (uintptr_t)(spd_file + spd_index); diff --git a/src/mainboard/google/eve/spd/spd.h b/src/mainboard/google/eve/spd/spd.h index 7b53fd4..b46ea4d 100644 --- a/src/mainboard/google/eve/spd/spd.h +++ b/src/mainboard/google/eve/spd/spd.h @@ -3,17 +3,9 @@ #ifndef MAINBOARD_SPD_H #define MAINBOARD_SPD_H -#define SPD_LEN 256 +#include <spd_bin.h> +#include <stdint.h> -#define SPD_DRAM_TYPE 2 -#define SPD_DRAM_DDR3 0x0b -#define SPD_DRAM_LPDDR3 0xf1 -#define SPD_DENSITY_BANKS 4 -#define SPD_ADDRESSING 5 -#define SPD_ORGANIZATION 7 -#define SPD_BUS_DEV_WIDTH 8 -#define SPD_PART_OFF 128 -#define SPD_PART_LEN 18 #define SPD_MANU_OFF 148 int mainboard_get_spd_index(void); diff --git a/src/mainboard/google/glados/romstage.c b/src/mainboard/google/glados/romstage.c index 9a968b1..1c4641e 100644 --- a/src/mainboard/google/glados/romstage.c +++ b/src/mainboard/google/glados/romstage.c @@ -30,7 +30,7 @@ }; const int spd_idx = gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); - mem_cfg->MemorySpdDataLen = SPD_LEN; + mem_cfg->MemorySpdDataLen = SPD_PAGE_LEN; mem_cfg->DqPinsInterleaved = FALSE; spd_memory_init_params(mupd, spd_idx); diff --git a/src/mainboard/google/glados/spd/spd.c b/src/mainboard/google/glados/spd/spd.c index 9bfb202..5deae62 100644 --- a/src/mainboard/google/glados/spd/spd.c +++ b/src/mainboard/google/glados/spd/spd.c @@ -20,15 +20,15 @@ const int spd_ranks[8] = { 1, 2, 3, 4, -1, -1, -1, -1 }; const int spd_devw[8] = { 4, 8, 16, 32, -1, -1, -1, -1 }; const int spd_busw[8] = { 8, 16, 32, 64, -1, -1, -1, -1 }; - char spd_name[SPD_PART_LEN+1] = { 0 }; + char spd_name[DDR3_SPD_PART_LEN+1] = { 0 }; int banks = spd_banks[(spd[SPD_DENSITY_BANKS] >> 4) & 7]; int capmb = spd_capmb[spd[SPD_DENSITY_BANKS] & 7] * 256; int rows = spd_rows[(spd[SPD_ADDRESSING] >> 3) & 7]; int cols = spd_cols[spd[SPD_ADDRESSING] & 7]; - int ranks = spd_ranks[(spd[SPD_ORGANIZATION] >> 3) & 7]; - int devw = spd_devw[spd[SPD_ORGANIZATION] & 7]; - int busw = spd_busw[spd[SPD_BUS_DEV_WIDTH] & 7]; + int ranks = spd_ranks[(spd[DDR3_ORGANIZATION] >> 3) & 7]; + int devw = spd_devw[spd[DDR3_ORGANIZATION] & 7]; + int busw = spd_busw[spd[DDR3_BUS_DEV_WIDTH] & 7]; /* Module type */ printk(BIOS_INFO, "SPD: module type is "); @@ -36,7 +36,7 @@ case SPD_DRAM_DDR3: printk(BIOS_INFO, "DDR3\n"); break; - case SPD_DRAM_LPDDR3: + case SPD_DRAM_LPDDR3_INTEL: printk(BIOS_INFO, "LPDDR3\n"); break; default: @@ -45,8 +45,8 @@ } /* Module Part Number */ - memcpy(spd_name, &spd[SPD_PART_OFF], SPD_PART_LEN); - spd_name[SPD_PART_LEN] = 0; + memcpy(spd_name, &spd[DDR3_SPD_PART_OFF], DDR3_SPD_PART_LEN); + spd_name[DDR3_SPD_PART_LEN] = 0; printk(BIOS_INFO, "SPD: module part is %s\n", spd_name); printk(BIOS_INFO, @@ -84,16 +84,16 @@ die("SPD data not found."); /* make sure we have at least one SPD in the file. */ - if (spd_file_len < SPD_LEN) + if (spd_file_len < SPD_PAGE_LEN) die("Missing SPD data."); /* Make sure we did not overrun the buffer */ - if (spd_file_len < ((spd_index + 1) * SPD_LEN)) { + if (spd_file_len < ((spd_index + 1) * SPD_PAGE_LEN)) { printk(BIOS_ERR, "SPD index override to 1 - old hardware?\n"); spd_index = 1; } - const size_t spd_offset = spd_index * SPD_LEN; + const size_t spd_offset = spd_index * SPD_PAGE_LEN; /* Make sure a valid SPD was found */ if (spd_file[spd_offset] == 0) die("Invalid SPD data."); diff --git a/src/mainboard/google/glados/spd/spd.h b/src/mainboard/google/glados/spd/spd.h index 764958b..02e9c7c 100644 --- a/src/mainboard/google/glados/spd/spd.h +++ b/src/mainboard/google/glados/spd/spd.h @@ -3,17 +3,8 @@ #ifndef MAINBOARD_SPD_H #define MAINBOARD_SPD_H -#define SPD_LEN 256 +#include <spd_bin.h> -#define SPD_DRAM_TYPE 2 -#define SPD_DRAM_DDR3 0x0b -#define SPD_DRAM_LPDDR3 0xf1 -#define SPD_DENSITY_BANKS 4 -#define SPD_ADDRESSING 5 -#define SPD_ORGANIZATION 7 -#define SPD_BUS_DEV_WIDTH 8 -#define SPD_PART_OFF 128 -#define SPD_PART_LEN 18 #define SPD_MANU_OFF 148 #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/69273 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3978d100ad1b763d7318d261cd7825ce2ac4ba97 Gerrit-Change-Number: 69273 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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[XL] Change in coreboot[master]: vc/intel/fsp/mtl: Update header files from 2364_00 to 2404_00
by Subrata Banik (Code Review) 07 Nov '22

07 Nov '22

Attention is currently required from: Tarun Tuli, Jamie Ryu, Subrata Banik, Ravishankar Sarawadi, Kapil Porwal, Sridhar Siricilla. Subrata Banik has uploaded a new patch set (#4) to the change originally created by Name of user not set #1004626. ( https://review.coreboot.org/c/coreboot/+/69182 ) Change subject: vc/intel/fsp/mtl: Update header files from 2364_00 to 2404_00 ...................................................................... vc/intel/fsp/mtl: Update header files from 2364_00 to 2404_00 Update header files for FSP for Meteor Lake platform to version 2404_00, previous version being 2364_00. FSPM: 1. Address offset changes 2. Rename `PlatformDebugConsent` to `PlatformDebugOption` FSPS: 1. Address offset changes Additionally, incorporate the UPD name change for MTL romstage. BUG=b:255481471 TEST=Able to build and boot Google, Rex to ChromeOS. Signed-off-by: vjadeja-intel <vikrant.l.jadeja(a)intel.com> Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I63ef4ecb6569141542a3b9bf4ee8cbcd2946582e --- M src/soc/intel/meteorlake/romstage/fsp_params.c M src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h M src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspsUpd.h 3 files changed, 1,110 insertions(+), 202 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/69182/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/69182 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I63ef4ecb6569141542a3b9bf4ee8cbcd2946582e Gerrit-Change-Number: 69182 Gerrit-PatchSet: 4 Gerrit-Owner: Name of user not set #1004626 Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-CC: Raj Astekar <raj.astekar(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: include/cper.h: Add CPER Memory Error Section definitions
by Shuming Chu (Shuming) (Code Review) 07 Nov '22

07 Nov '22

Attention is currently required from: Jonathan Zhang, Johnny Lin, Angel Pons, Tim Chu. Shuming Chu (Shuming) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69198 ) Change subject: include/cper.h: Add CPER Memory Error Section definitions ...................................................................... Patch Set 3: (1 comment) File src/include/cper.h: https://review.coreboot.org/c/coreboot/+/69198/comment/5de733ae_2191e9e6 PS2, Line 508: /* UEFI Spec, Appendix N.2.5 Memory Error Types */ > Let's add the spec version, table number, such as "IA32/X64 Processor Error Section (Table 255)"; al […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/69198 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0a165350a16a4cbe4033a3e7c43fa23a5b27c44b Gerrit-Change-Number: 69198 Gerrit-PatchSet: 3 Gerrit-Owner: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 07 Nov 2022 10:02:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/meteorlake: Remove PM Energy Report WA
by Sridhar Siricilla (Code Review) 07 Nov '22

07 Nov '22

Attention is currently required from: Tarun Tuli, Subrata Banik, Ravishankar Sarawadi, Kapil Porwal. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69042 ) Change subject: soc/intel/meteorlake: Remove PM Energy Report WA ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69042 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If5f1f9c6ab31652977d436a49a3531edffbd60c5 Gerrit-Change-Number: 69042 Gerrit-PatchSet: 4 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Mon, 07 Nov 2022 10:01:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: include/cper.h: Add CPER Memory Error Section definitions
by Shuming Chu (Shuming) (Code Review) 07 Nov '22

07 Nov '22

Attention is currently required from: Johnny Lin, Angel Pons, Shuming Chu (Shuming), Tim Chu. Hello build bot (Jenkins), Jonathan Zhang, Johnny Lin, Angel Pons, Tim Chu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69198 to look at the new patch set (#3). Change subject: include/cper.h: Add CPER Memory Error Section definitions ...................................................................... include/cper.h: Add CPER Memory Error Section definitions Add Memory Error Section definitions from UEFI Specification rev 2.10 appendix N.2.5. The structure defined here may be used for machine check handling. Signed-off-by: Tim Chu <Tim.Chu(a)quantatw.com> Change-Id: I0a165350a16a4cbe4033a3e7c43fa23a5b27c44b --- M src/include/cper.h 1 file changed, 48 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/69198/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/69198 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0a165350a16a4cbe4033a3e7c43fa23a5b27c44b Gerrit-Change-Number: 69198 Gerrit-PatchSet: 3 Gerrit-Owner: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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[XL] Change in coreboot[master]: vc/intel/fsp/mtl: Update header files from 2364_00 to 2404_00
by Subrata Banik (Code Review) 07 Nov '22

07 Nov '22

Attention is currently required from: Tarun Tuli, Jamie Ryu, Subrata Banik, Ravishankar Sarawadi, Kapil Porwal, Sridhar Siricilla. Subrata Banik has uploaded a new patch set (#3) to the change originally created by Name of user not set #1004626. ( https://review.coreboot.org/c/coreboot/+/69182 ) Change subject: vc/intel/fsp/mtl: Update header files from 2364_00 to 2404_00 ...................................................................... vc/intel/fsp/mtl: Update header files from 2364_00 to 2404_00 Update header files for FSP for Meteor Lake platform to version 2404_00, previous version being 2364_00. FSPM: 1. Address offset changes 2. Rename `PlatformDebugConsent` to `PlatformDebugOption` FSPS: 1. Address offset changes Additionally, incorporate the UPD name change for MTL romstage. BUG=b:TBD TEST=emerge-rex intel-mtlfsp Signed-off-by: vjadeja-intel <vikrant.l.jadeja(a)intel.com> Change-Id: I63ef4ecb6569141542a3b9bf4ee8cbcd2946582e --- M src/soc/intel/meteorlake/romstage/fsp_params.c M src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h M src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspsUpd.h 3 files changed, 1,109 insertions(+), 202 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/69182/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/69182 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I63ef4ecb6569141542a3b9bf4ee8cbcd2946582e Gerrit-Change-Number: 69182 Gerrit-PatchSet: 3 Gerrit-Owner: Name of user not set #1004626 Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-CC: Raj Astekar <raj.astekar(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: newpatchset

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[XL] Change in coreboot[master]: vc/intel/fsp/mtl: Update header files from 2364_00 to 2404_00
by Subrata Banik (Code Review) 07 Nov '22

07 Nov '22

Attention is currently required from: Tarun Tuli, Jamie Ryu, Subrata Banik, Ravishankar Sarawadi, Kapil Porwal, Sridhar Siricilla. Subrata Banik has uploaded a new patch set (#2) to the change originally created by Name of user not set #1004626. ( https://review.coreboot.org/c/coreboot/+/69182 ) Change subject: vc/intel/fsp/mtl: Update header files from 2364_00 to 2404_00 ...................................................................... vc/intel/fsp/mtl: Update header files from 2364_00 to 2404_00 Update header files for FSP for Meteor Lake platform to version 2404_00, previous version being 2364_00. FSPM: 1. Address offset changes 2. Rename `PlatformDebugConsent` to `PlatformDebugOption` FSPS: 1. Address offset changes BUG=b:TBD TEST=emerge-rex intel-mtlfsp Signed-off-by: vjadeja-intel <vikrant.l.jadeja(a)intel.com> Change-Id: I63ef4ecb6569141542a3b9bf4ee8cbcd2946582e --- M src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h M src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspsUpd.h 2 files changed, 1,106 insertions(+), 201 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/69182/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69182 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I63ef4ecb6569141542a3b9bf4ee8cbcd2946582e Gerrit-Change-Number: 69182 Gerrit-PatchSet: 2 Gerrit-Owner: Name of user not set #1004626 Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-CC: Raj Astekar <raj.astekar(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: mb/google/brya: Create marasov variant
by Subrata Banik (Code Review) 07 Nov '22

07 Nov '22

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69052 ) Change subject: mb/google/brya: Create marasov variant ...................................................................... mb/google/brya: Create marasov variant Create the marasov variant of the brya0 reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:254365935 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_MARASOV Signed-off-by: Frank Chu <Frank_Chu(a)pegatron.corp-partner.google.com> Change-Id: Ibe2dc442480f6a73877b40625e228cdb2038aa4d Reviewed-on: https://review.coreboot.org/c/coreboot/+/69052 Reviewed-by: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Reviewed-by: Kyle Lin <kylelinck(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/Kconfig.name A src/mainboard/google/brya/variants/marasov/include/variant/ec.h A src/mainboard/google/brya/variants/marasov/include/variant/gpio.h A src/mainboard/google/brya/variants/marasov/memory/Makefile.inc A src/mainboard/google/brya/variants/marasov/memory/dram_id.generated.txt A src/mainboard/google/brya/variants/marasov/memory/mem_parts_used.txt A src/mainboard/google/brya/variants/marasov/overridetree.cb 8 files changed, 71 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Frank Chu: Looks good to me, but someone else must approve Subrata Banik: Looks good to me, approved Eric Lai: Looks good to me, approved Kyle Lin: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index f54e96b..68c2780 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -218,6 +218,7 @@ default "Lisbon" if BOARD_GOOGLE_LISBON default "Zydron" if BOARD_GOOGLE_ZYDRON default "Gladios" if BOARD_GOOGLE_GLADIOS + default "Marasov" if BOARD_GOOGLE_MARASOV config VARIANT_DIR default "brya0" if BOARD_GOOGLE_BRYA0 @@ -258,6 +259,7 @@ default "lisbon" if BOARD_GOOGLE_LISBON default "zydron" if BOARD_GOOGLE_ZYDRON default "gladios" if BOARD_GOOGLE_GLADIOS + default "marasov" if BOARD_GOOGLE_MARASOV config VBOOT select VBOOT_EARLY_EC_SYNC if !BOARD_GOOGLE_BASEBOARD_NISSA diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index 647ae30..fc91205 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -288,3 +288,7 @@ bool "-> Gladios" select BOARD_GOOGLE_BASEBOARD_BRASK select SOC_INTEL_RAPTORLAKE + +config BOARD_GOOGLE_MARASOV + bool "-> Marasov" + select BOARD_GOOGLE_BASEBOARD_BRYA diff --git a/src/mainboard/google/brya/variants/marasov/include/variant/ec.h b/src/mainboard/google/brya/variants/marasov/include/variant/ec.h new file mode 100644 index 0000000..7a2a6ff --- /dev/null +++ b/src/mainboard/google/brya/variants/marasov/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/brya/variants/marasov/include/variant/gpio.h b/src/mainboard/google/brya/variants/marasov/include/variant/gpio.h new file mode 100644 index 0000000..c4fe342 --- /dev/null +++ b/src/mainboard/google/brya/variants/marasov/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include <baseboard/gpio.h> + +#endif diff --git a/src/mainboard/google/brya/variants/marasov/memory/Makefile.inc b/src/mainboard/google/brya/variants/marasov/memory/Makefile.inc new file mode 100644 index 0000000..eace2e4 --- /dev/null +++ b/src/mainboard/google/brya/variants/marasov/memory/Makefile.inc @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. + +SPD_SOURCES = placeholder diff --git a/src/mainboard/google/brya/variants/marasov/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/marasov/memory/dram_id.generated.txt new file mode 100644 index 0000000..fa24790 --- /dev/null +++ b/src/mainboard/google/brya/variants/marasov/memory/dram_id.generated.txt @@ -0,0 +1 @@ +DRAM Part Name ID to assign diff --git a/src/mainboard/google/brya/variants/marasov/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/marasov/memory/mem_parts_used.txt new file mode 100644 index 0000000..9621137 --- /dev/null +++ b/src/mainboard/google/brya/variants/marasov/memory/mem_parts_used.txt @@ -0,0 +1,11 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Generated IDs are dependent on the order of parts in this file, +# so new parts must always be added at the end of the file! +# +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# part_id_gen tool from util/spd_tools. +# See util/spd_tools/README.md for more details and instructions. + +# Part Name diff --git a/src/mainboard/google/brya/variants/marasov/overridetree.cb b/src/mainboard/google/brya/variants/marasov/overridetree.cb new file mode 100644 index 0000000..4f2c04a --- /dev/null +++ b/src/mainboard/google/brya/variants/marasov/overridetree.cb @@ -0,0 +1,6 @@ +chip soc/intel/alderlake + + device domain 0 on + end + +end -- To view, visit https://review.coreboot.org/c/coreboot/+/69052 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe2dc442480f6a73877b40625e228cdb2038aa4d Gerrit-Change-Number: 69052 Gerrit-PatchSet: 9 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Kyle Lin <kylelinck(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: src/include/smbios: Add definition for smbios type 4 and type 9
by Shuming Chu (Shuming) (Code Review) 07 Nov '22

07 Nov '22

Attention is currently required from: Paul Menzel, Angel Pons, Tim Chu. Shuming Chu (Shuming) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68902 ) Change subject: src/include/smbios: Add definition for smbios type 4 and type 9 ...................................................................... Patch Set 3: (2 comments) File src/include/smbios.h: https://review.coreboot.org/c/coreboot/+/68902/comment/cfa287e0_e7131fa0 PS1, Line 487: #define SMBIOS_PROCESSOR_FAMILY_XEON 0xb3 > Where is this define used? Does it really belong in here? These defines are used for smbios type 4 processor family field. https://review.coreboot.org/c/coreboot/+/68902/comment/89637a94_e2d62845 PS1, Line 488: #define PROCESSOR_64BIT_CAPABLE BIT(2) : #define PROCESSOR_MULTI_CORE BIT(3) : #define PROCESSOR_POWER_PERFORMANCE_CONTROL BIT(7) > Hmmm, let's not use `BIT()` for consistency with existing macros Done -- To view, visit https://review.coreboot.org/c/coreboot/+/68902 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I559995b0204f8e5bdeef2c0f8b394f9011d72240 Gerrit-Change-Number: 68902 Gerrit-PatchSet: 3 Gerrit-Owner: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 07 Nov 2022 09:48:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: nb/intel/sandybridge: Hook up CPU bus and PCI domain ops to devicetree
by build bot (Jenkins) (Code Review) 07 Nov '22

07 Nov '22

Attention is currently required from: Angel Pons, Alexander Couzens, Evgeny Zinoviev. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69291 ) Change subject: nb/intel/sandybridge: Hook up CPU bus and PCI domain ops to devicetree ...................................................................... Patch Set 1: (1 comment) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-162637): https://review.coreboot.org/c/coreboot/+/69291/comment/073a543b_25799587 PS1, Line 15: sed -i 's/domain 0 on/domain 0 on\n\t\tops sandybridge_pci_domain_ops/' \ Possible unwrapped commit description (prefer a maximum 72 chars per line) -- To view, visit https://review.coreboot.org/c/coreboot/+/69291 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I718d9dbc184c8bca38f452efea3202901018cb04 Gerrit-Change-Number: 69291 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Comment-Date: Mon, 07 Nov 2022 09:47:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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