Attention is currently required from: Venkat Thogaru, Julius Werner, Sudheer Amrabadi.
Venkat Thogaru has uploaded a new patch set (#22) to the change originally created by Sudheer Amrabadi. ( https://review.coreboot.org/c/coreboot/+/67673 )
Change subject: soc/qualcomm/sc7280: Move AOP load and reset handle to Romstage
......................................................................
soc/qualcomm/sc7280: Move AOP load and reset handle to Romstage
As AOP takes 500 msec delay to get up, moving aop load and reset to
romstage improves the performance.
BUG=b:218406702
TEST=reboot from AP console (on CRD3)
prior to fix (from cbmem dump):
1000:depthcharge start 1,139,809 (152,679)
after fix (from cbmem dump):
1000:depthcharge start 1,041,109 (46,353)
Signed-off-by: Sudheer Kumar Amrabadi <samrabad(a)codeaurora.org>
Change-Id: Iabc8ee8f6e7b14d237b0aeaae42da8077f9dafc4
---
M src/mainboard/google/herobrine/romstage.c
M src/soc/qualcomm/sc7280/Makefile.inc
M src/soc/qualcomm/sc7280/memlayout.ld
M src/soc/qualcomm/sc7280/soc.c
4 files changed, 26 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/67673/22
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Change subject: soc/qualcomm/sc7280: Update Skuid to support pro/non-pro
......................................................................
soc/qualcomm/sc7280: Update Skuid to support pro/non-pro
Tranferring a bit to DC through Skuid to update the regulator
node in order to support pro and non-pro
BUG=b:248187555
TEST=Validate boards are detected correctly on PRO and NON_PRO SKUs
Signed-off-by: Sudheer Kumar Amrabadi <quic_samrabad(a)quicinc.com>
Change-Id: Iec392c03c2e2c79d20b1fcb79236ca9e048bfd07
---
M src/mainboard/google/herobrine/boardid.c
1 file changed, 20 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/68385/15
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Venkat Thogaru has uploaded a new patch set (#14) to the change originally created by Sudheer Amrabadi. ( https://review.coreboot.org/c/coreboot/+/68384 )
Change subject: soc/qualcomm/sc7280: Add API to differentialize PRO and NON_PRO SKUs
......................................................................
soc/qualcomm/sc7280: Add API to differentialize PRO and NON_PRO SKUs
The API socinfo_pro_part() returns 1 for Pro and 0 for NON_PRO SKUs. To
reduce the binary footprint for chipinfo structure, change its members
range from uint32_t to uint16_t. Add helper functions for reading and
matching jtagid.
BUG=b:248187555
TEST=Validate boards are detected correctly on PRO and NON_PRO SKUs
Signed-off-by: Taniya Das <quic_tdas(a)quicinc.com>
Change-Id: Id9f23696384a6c1a89000292eafebd8a16c273ca
---
M src/soc/qualcomm/sc7280/include/soc/socinfo.h
M src/soc/qualcomm/sc7280/socinfo.c
2 files changed, 86 insertions(+), 57 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/68384/14
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Change subject: mb/google/herobrine: Update comment of modem status info
......................................................................
mb/google/herobrine: Update comment of modem status info
Updated comment as per guidelines.
BUG=b:232302324
TEST=none
Signed-off-by: Venkat Thogaru <quic_thogaru(a)quicinc.com>
Change-Id: I6a925477a926e7e9d54e42d662768536318ec8e0
---
M src/mainboard/google/herobrine/boardid.c
1 file changed, 17 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/69296/2
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Change subject: soc/qualcomm/sc7280: Update Skuid to support pro/non-pro
......................................................................
Patch Set 14:
(1 comment)
File src/mainboard/google/herobrine/boardid.c:
https://review.coreboot.org/c/coreboot/+/68385/comment/15cceb35_e7868b71
PS10, Line 47: /* Update modem status in 9th bit of sku id */
> Moved the changes to separate commit. […]
Done
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Change subject: soc/qualcomm/sc7280: Update Skuid to support pro/non-pro
......................................................................
Patch Set 14:
(1 comment)
File src/mainboard/google/herobrine/boardid.c:
https://review.coreboot.org/c/coreboot/+/68385/comment/e9de06db_eda8791b
PS10, Line 47: /* Update modem status in 9th bit of sku id */
> Please factor this out into a separate commit.
Moved the changes to separate commit.
https://review.coreboot.org/c/coreboot/+/69296
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Change subject: mb/google/herobrine: Update comment of modem status info
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-162651):
https://review.coreboot.org/c/coreboot/+/69296/comment/50361f29_e35a9350
PS1, Line 8:
'guidlines' may be misspelled - perhaps 'guidelines'?
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Venkat Thogaru has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69296 )
Change subject: mb/google/herobrine: Update comment of modem status info
......................................................................
mb/google/herobrine: Update comment of modem status info
Updated comment as per guidlines.
BUG=b:232302324
TEST=none
Signed-off-by: Venkat Thogaru <quic_thogaru(a)quicinc.com>
Change-Id: I6a925477a926e7e9d54e42d662768536318ec8e0
---
M src/mainboard/google/herobrine/boardid.c
1 file changed, 17 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/69296/1
diff --git a/src/mainboard/google/herobrine/boardid.c b/src/mainboard/google/herobrine/boardid.c
index 7bac5df..fc058e2 100644
--- a/src/mainboard/google/herobrine/boardid.c
+++ b/src/mainboard/google/herobrine/boardid.c
@@ -43,7 +43,8 @@
uint32_t sku_id(void)
{
static uint32_t id = UNDEFINED_STRAPPING_ID;
- /*Update modem status in 9th bit of sku id*/
+
+ /* Update modem status in 9th bit of sku id */
uint32_t mask = 1 << 9;
id = google_chromeec_get_board_sku();
id = ((id & ~mask) | (socinfo_modem_supported() << 9));
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Attention is currently required from: Venkat Thogaru, Julius Werner, Sudheer Amrabadi.
Venkat Thogaru has uploaded a new patch set (#21) to the change originally created by Sudheer Amrabadi. ( https://review.coreboot.org/c/coreboot/+/67673 )
Change subject: soc/qualcomm/sc7280: Move AOP load and reset handle to Romstage
......................................................................
soc/qualcomm/sc7280: Move AOP load and reset handle to Romstage
As AOP takes 500 msec delay to get up, moving aop load and reset to
romstage improves the performance.
BUG=b:218406702
TEST=reboot from AP console (on CRD3)
prior to fix (from cbmem dump):
1000:depthcharge start 1,139,809 (152,679)
after fix (from cbmem dump):
1000:depthcharge start 1,041,109 (46,353)
Signed-off-by: Sudheer Kumar Amrabadi <samrabad(a)codeaurora.org>
Change-Id: Iabc8ee8f6e7b14d237b0aeaae42da8077f9dafc4
---
M src/mainboard/google/herobrine/romstage.c
M src/soc/qualcomm/sc7280/Makefile.inc
M src/soc/qualcomm/sc7280/memlayout.ld
M src/soc/qualcomm/sc7280/soc.c
4 files changed, 26 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/67673/21
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EricKY Cheng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68649 )
Change subject: soc/amd/mendocino: Enhance DPTC_INPUT to support 13 DPTC thermal parameters
......................................................................
Patch Set 21:
(1 comment)
File src/soc/amd/mendocino/root_complex.c:
https://review.coreboot.org/c/coreboot/+/68649/comment/102f63ea_1e484067
PS20, Line 269: /* Normal mode DPTC values. */
: struct dptc_input default_input = DPTC_INPUTS(
: config->thermctl_limit_degreeC,
: config->sustained_power_limit_mW,
: config->slow_ppt_time_constant_s,
: config->fast_ppt_limit_mW,
: config->slow_ppt_limit_mW,
: config->vrm_current_limit_mA,
: config->vrm_maximum_current_limit_mA,
: config->vrm_soc_current_limit_mA,
: config->stt_min_limit,
: config->stt_m1,
: config->stt_m2,
: config->stt_c_apu,
: config->stt_skin_temp_apu);
: acpigen_write_alib_dptc_default((uint8_t *)&default_input, sizeof(default_input));
:
: /* Low/No Battery */
: struct dptc_input no_battery_input = DPTC_INPUTS(
: config->thermctl_limit_degreeC,
: config->sustained_power_limit_mW,
: config->slow_ppt_time_constant_s,
: config->fast_ppt_limit_mW,
: config->slow_ppt_limit_mW,
: config->vrm_current_limit_throttle_mA,
: config->vrm_maximum_current_limit_throttle_mA,
: config->vrm_soc_current_limit_throttle_mA,
: config->stt_min_limit,
: config->stt_m1,
: config->stt_m2,
: config->stt_c_apu,
: config->stt_skin_temp_apu);
: acpigen_write_alib_dptc_no_battery((uint8_t *)&no_battery_input,
: sizeof(no_battery_input));
> Delete these and use the ones defined below instead.
default_input on line 270 is different form default_input on line 395.
no_battery_input on line 287 s different form default_input on line 405.
Follow thermal team's proposal, default_input is used as table A on line 270 defined with DTTS requested parameters.
If delete the default_input on line 270 and used the default_input on line 395, will
conflict with thermal team's proposal.
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