coreboot-gerrit November 2022

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: mb/google/brya/var/lisbon: Disable thunderbolt ports
by Felix Held (Code Review) 08 Nov '22

08 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68916 ) Change subject: mb/google/brya/var/lisbon: Disable thunderbolt ports ...................................................................... mb/google/brya/var/lisbon: Disable thunderbolt ports Lisbon doesn't support thunderbolt. BUG=b:246657849 TEST=FW_NAME=lisbon emerge-brask coreboot Signed-off-by: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Change-Id: Iac44315d000c3c0c572efb00e877d039e0308455 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68916 Reviewed-by: Nick Vaccaro <nvaccaro(a)google.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/variants/lisbon/overridetree.cb 1 file changed, 26 insertions(+), 7 deletions(-) Approvals: build bot (Jenkins): Verified Nick Vaccaro: Looks good to me, approved Angel Pons: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/lisbon/overridetree.cb b/src/mainboard/google/brya/variants/lisbon/overridetree.cb index 23c3461..fc285639 100644 --- a/src/mainboard/google/brya/variants/lisbon/overridetree.cb +++ b/src/mainboard/google/brya/variants/lisbon/overridetree.cb @@ -150,13 +150,12 @@ .flags = PCIE_RP_LTR | PCIE_RP_AER, }" end - device ref tcss_dma0 on - chip drivers/intel/usb4/retimer - register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)" - use tcss_usb3_port1 as dfp[0].typec_port - device generic 0 on end - end - end + device ref tbt_pcie_rp0 off end + device ref tbt_pcie_rp1 off end + device ref tbt_pcie_rp2 off end + + device ref tcss_dma0 off end + device ref tcss_dma1 off end device ref cnvi_wifi on chip drivers/wifi/generic register "wake" = "GPE0_PME_B0" -- To view, visit https://review.coreboot.org/c/coreboot/+/68916 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iac44315d000c3c0c572efb00e877d039e0308455 Gerrit-Change-Number: 68916 Gerrit-PatchSet: 3 Gerrit-Owner: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Ricky Chang <rickytlchang(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: mb/intel/mtlrvp: Enable ACPI and add ACPI table
by Eric Lai (Code Review) 08 Nov '22

08 Nov '22

Eric Lai has submitted this change. ( https://review.coreboot.org/c/coreboot/+/66100 ) Change subject: mb/intel/mtlrvp: Enable ACPI and add ACPI table ...................................................................... mb/intel/mtlrvp: Enable ACPI and add ACPI table This enables ACPI configuration and add ACPI table. BUG=b:224325352 TEST=util/abuild/abuild -p none -t intel/mtlrvp -a -c max Signed-off-by: Jamie Ryu <jamie.m.ryu(a)intel.com> Change-Id: I8264197fd0acdd7e19b9a36fb22822447b013202 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66100 Reviewed-by: Nick Vaccaro <nvaccaro(a)google.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Usha P <usha.p(a)intel.com> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> --- M src/mainboard/intel/mtlrvp/Kconfig A src/mainboard/intel/mtlrvp/Makefile.inc M src/mainboard/intel/mtlrvp/dsdt.asl A src/mainboard/intel/mtlrvp/include/baseboard/gpio.h 4 files changed, 51 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Nick Vaccaro: Looks good to me, approved Angel Pons: Looks good to me, approved Usha P: Looks good to me, approved Subrata Banik: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/mainboard/intel/mtlrvp/Kconfig b/src/mainboard/intel/mtlrvp/Kconfig index 3c29d3a..e73d26a 100644 --- a/src/mainboard/intel/mtlrvp/Kconfig +++ b/src/mainboard/intel/mtlrvp/Kconfig @@ -1,6 +1,7 @@ config BOARD_INTEL_MTLRVP_COMMON def_bool n select BOARD_ROMSIZE_KB_32768 + select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select SOC_INTEL_METEORLAKE diff --git a/src/mainboard/intel/mtlrvp/Makefile.inc b/src/mainboard/intel/mtlrvp/Makefile.inc new file mode 100644 index 0000000..830a6d3 --- /dev/null +++ b/src/mainboard/intel/mtlrvp/Makefile.inc @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include + +subdirs-y += variants/$(VARIANT_DIR) diff --git a/src/mainboard/intel/mtlrvp/dsdt.asl b/src/mainboard/intel/mtlrvp/dsdt.asl index 82d11c6..f5728a6 100644 --- a/src/mainboard/intel/mtlrvp/dsdt.asl +++ b/src/mainboard/intel/mtlrvp/dsdt.asl @@ -11,4 +11,18 @@ 0x20110725 ) { + #include <acpi/dsdt_top.asl> + #include <cpu/intel/common/acpi/cpu.asl> + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + #include <soc/intel/common/block/acpi/acpi/platform.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <soc/intel/common/block/acpi/acpi/northbridge.asl> + #include <soc/intel/meteorlake/acpi/southbridge.asl> + } + } + + #include <southbridge/intel/common/acpi/sleepstates.asl> } diff --git a/src/mainboard/intel/mtlrvp/include/baseboard/gpio.h b/src/mainboard/intel/mtlrvp/include/baseboard/gpio.h new file mode 100644 index 0000000..a708db1 --- /dev/null +++ b/src/mainboard/intel/mtlrvp/include/baseboard/gpio.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __BASEBOARD_GPIO_H__ +#define __BASEBOARD_GPIO_H__ + +#include <soc/gpe.h> +#include <soc/gpio.h> + +#endif /* __BASEBOARD_GPIO_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/66100 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8264197fd0acdd7e19b9a36fb22822447b013202 Gerrit-Change-Number: 66100 Gerrit-PatchSet: 8 Gerrit-Owner: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/intel/mtlrvp: Enable ACPI and add ACPI table
by Eric Lai (Code Review) 08 Nov '22

08 Nov '22

Attention is currently required from: Tarun Tuli, Jamie Ryu, Wonkyu Kim, Ravishankar Sarawadi, Tim Wawrzynczak, Kapil Porwal, Raj Astekar. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/66100 ) Change subject: mb/intel/mtlrvp: Enable ACPI and add ACPI table ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/66100 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8264197fd0acdd7e19b9a36fb22822447b013202 Gerrit-Change-Number: 66100 Gerrit-PatchSet: 7 Gerrit-Owner: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Comment-Date: Tue, 08 Nov 2022 00:25:46 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/nissa/var/craask: Add wifi sar table
by Eric Lai (Code Review) 08 Nov '22

08 Nov '22

Attention is currently required from: Tarun Tuli, Kangheui Won, Tim Wawrzynczak, Tyler Wang, Nick Vaccaro. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68660 ) Change subject: mb/google/nissa/var/craask: Add wifi sar table ...................................................................... Patch Set 9: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68660 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5c92f0ab53ece12a97068f09241e5298909116aa Gerrit-Change-Number: 68660 Gerrit-PatchSet: 9 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Cathy Chen <cathy_chen(a)quanta.corp-partner.google.com> Gerrit-CC: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-CC: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Tue, 08 Nov 2022 00:20:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/qemu/x86: Remove option for LEGACY_SMP_INIT
by 9elements QA (Code Review) 08 Nov '22

08 Nov '22

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69128 ) Change subject: mb/qemu/x86: Remove option for LEGACY_SMP_INIT ...................................................................... Patch Set 8: Automatic boot test returned (PASS/FAIL/TOTAL): 15 / 1 / 16 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/134311 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/134310 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/134309 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/134308 FAIL: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/134307 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/134306 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/134305 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/134304 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/134303 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/134302 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/134301 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/134300 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/134299 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/134298 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/134297 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/134296 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/69128 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I17327c31f8ade51716578e45c2d90a327efcd4ad Gerrit-Change-Number: 69128 Gerrit-PatchSet: 8 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Tue, 08 Nov 2022 00:14:54 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/aldrlake: Update ME HFSTS register definition
by Eric Lai (Code Review) 08 Nov '22

08 Nov '22

Attention is currently required from: Tarun Tuli, Rizwan Qureshi. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69286 ) Change subject: soc/intel/aldrlake: Update ME HFSTS register definition ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/69286 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9aeee7a3b41ad59c03391207930a253ffff19ae5 Gerrit-Change-Number: 69286 Gerrit-PatchSet: 1 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Comment-Date: Tue, 08 Nov 2022 00:14:17 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/alderlake: Check MANUF_LOCK when logging manufacturing mode
by Reka Norman (Code Review) 08 Nov '22

08 Nov '22

Reka Norman has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69324 ) Change subject: soc/intel/alderlake: Check MANUF_LOCK when logging manufacturing mode ...................................................................... soc/intel/alderlake: Check MANUF_LOCK when logging manufacturing mode As per Intel doc #627331 Section 3.6.1 "Intel CSME Production Machine Determination", from ADL onwards there are three criteria which determine whether a device is in production mode: 1. Fuses are programmed 2. SPI descriptor is locked 3. Manufacturing variables are locked When logging whether the device is in manufacturing mode, 1 and 2 are already checked. Add a check for 3 as well. BUG=b:255462682 TEST=On a nivviks which has not gone through EOM: [DEBUG] ME: Manufacturing Mode : YES On an anahera which has gone through EOM: [DEBUG] ME: Manufacturing Mode : NO Change-Id: Iac605baa291ab5cc5f28464006f4828c12c748fe Signed-off-by: Reka Norman <rekanorman(a)chromium.org> --- M src/soc/intel/alderlake/me.c 1 file changed, 30 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/69324/1 diff --git a/src/soc/intel/alderlake/me.c b/src/soc/intel/alderlake/me.c index a965807..1a30e0d 100644 --- a/src/soc/intel/alderlake/me.c +++ b/src/soc/intel/alderlake/me.c @@ -134,12 +134,13 @@ printk(BIOS_DEBUG, "ME: HFSTS6 : 0x%08X\n", hfsts6.data); /* - * Lock Descriptor, and Fuses must be programmed on a - * production system to indicate ME Manufacturing mode is disabled. + * ME manufacturing mode is disabled if the descriptor is locked, fuses + * are programmed and manufacturing variables are locked. */ printk(BIOS_DEBUG, "ME: Manufacturing Mode : %s\n", ((hfsts1.fields.mfg_mode == 0) && - (hfsts6.fields.fpf_soc_lock == 1)) ? "NO" : "YES"); + (hfsts6.fields.fpf_soc_lock == 1) && + (hfsts6.fields.manuf_lock == 1)) ? "NO" : "YES"); /* * The SPI Protection Mode bit reflects SPI descriptor * locked(0) or unlocked(1). -- To view, visit https://review.coreboot.org/c/coreboot/+/69324 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iac605baa291ab5cc5f28464006f4828c12c748fe Gerrit-Change-Number: 69324 Gerrit-PatchSet: 1 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: common/acpi/dptc: Implement DTTS Proposal
by Tim Van Patten (Code Review) 08 Nov '22

08 Nov '22

Attention is currently required from: Jason Nien, EricKY Cheng, Matt DeVillier, Martin Roth, Eric Peers, LeilaCY Lin, Jason Glenesk, Caveh Jalali, Tim Wawrzynczak, Fred Reitberger, Karthikeyan Ramasubramanian, Boris Mittelberg, Felix Held. Tim Van Patten has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68471 ) Change subject: common/acpi/dptc: Implement DTTS Proposal ...................................................................... Patch Set 31: (1 comment) File src/soc/amd/common/acpi/dptc.asl: https://review.coreboot.org/c/coreboot/+/68471/comment/a1923c62_198bfa55 PS21, Line 56: 118 > Because there is an offset(200) of temperature value stored in mapped memory. […] Please add a comment indicating this offset is how the temperature values here are determined. -- To view, visit https://review.coreboot.org/c/coreboot/+/68471 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I866e5e497e2936984e713029b5f0b6d54cbc9622 Gerrit-Change-Number: 68471 Gerrit-PatchSet: 31 Gerrit-Owner: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: LeilaCY Lin <leilacy_lin(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Eric Peers <epeers(a)google.com> Gerrit-Attention: LeilaCY Lin <leilacy_lin(a)compal.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 07 Nov 2022 23:56:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Comment-In-Reply-To: Tim Van Patten <timvp(a)google.com> Comment-In-Reply-To: LeilaCY Lin <leilacy_lin(a)compal.corp-partner.google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/alderlake: Hook up DisableDynamicTccoldHandshake to dev tree
by Eric Lai (Code Review) 08 Nov '22

08 Nov '22

Attention is currently required from: Bora Guvendik, Zhixing Ma, Anil Kumar K, Subrata Banik, Selma Bensaid, Tim Wawrzynczak. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68635 ) Change subject: soc/intel/alderlake: Hook up DisableDynamicTccoldHandshake to dev tree ...................................................................... Patch Set 5: -Code-Review -- To view, visit https://review.coreboot.org/c/coreboot/+/68635 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica13b98204acebef7f0b9a4411b4ac19f53cad6e Gerrit-Change-Number: 68635 Gerrit-PatchSet: 5 Gerrit-Owner: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Comment-Date: Mon, 07 Nov 2022 23:55:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/alderlake: Hook up DisableDynamicTccoldHandshake to dev tree
by Nick Vaccaro (Code Review) 08 Nov '22

08 Nov '22

Attention is currently required from: Bora Guvendik, Zhixing Ma, Anil Kumar K, Subrata Banik, Selma Bensaid, Tim Wawrzynczak. Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68635 ) Change subject: soc/intel/alderlake: Hook up DisableDynamicTccoldHandshake to dev tree ...................................................................... Patch Set 5: Code-Review-2 (1 comment) Patchset: PS5: DisableDynamicTccoldHandshake field is not in the RPL FSP headers. -- To view, visit https://review.coreboot.org/c/coreboot/+/68635 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica13b98204acebef7f0b9a4411b4ac19f53cad6e Gerrit-Change-Number: 68635 Gerrit-PatchSet: 5 Gerrit-Owner: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Comment-Date: Mon, 07 Nov 2022 23:49:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit November 2022