coreboot-gerrit November 2022

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[S] Change in coreboot[master]: mb/google/var/marasov: Generate SPD ID for supported memory parts
by Frank Chu (Code Review) 08 Nov '22

08 Nov '22

Attention is currently required from: Tarun Tuli, Kyle Lin. Frank Chu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69311 ) Change subject: mb/google/var/marasov: Generate SPD ID for supported memory parts ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/69311 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifa0637b47d0017cdb9e26ed32328f4405c0df3f7 Gerrit-Change-Number: 69311 Gerrit-PatchSet: 1 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Kyle Lin <kylelinck(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kyle Lin <kylelinck(a)google.com> Gerrit-Comment-Date: Tue, 08 Nov 2022 03:08:54 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/var/marasov: Generate SPD ID for supported memory parts
by Frank Chu (Code Review) 08 Nov '22

08 Nov '22

Frank Chu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69311 ) Change subject: mb/google/var/marasov: Generate SPD ID for supported memory parts ...................................................................... mb/google/var/marasov: Generate SPD ID for supported memory parts Add supported memory parts in mem_parts_used list, and generate SPD ID for these parts. DRAM Part Name ID to assign MT62F512M32D2DR-031 WT:B 0 (0000) H9JCNNNBK3MLYR-N6E 1 (0001) MT62F1G32D4DR-031 WT:B 4 (0100) K3LKBKB0BM-MGCP 5 (0101) BUG=b:254365935 BRANCH=None TEST=run part_id_gen to generate SPD id Signed-off-by: Frank Chu <Frank_Chu(a)pegatron.corp-partner.google.com> Change-Id: Ifa0637b47d0017cdb9e26ed32328f4405c0df3f7 --- M src/mainboard/google/brya/variants/marasov/memory/Makefile.inc M src/mainboard/google/brya/variants/marasov/memory/dram_id.generated.txt M src/mainboard/google/brya/variants/marasov/memory/mem_parts_used.txt 3 files changed, 43 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/69311/1 diff --git a/src/mainboard/google/brya/variants/marasov/memory/Makefile.inc b/src/mainboard/google/brya/variants/marasov/memory/Makefile.inc index eace2e4..55b9450 100644 --- a/src/mainboard/google/brya/variants/marasov/memory/Makefile.inc +++ b/src/mainboard/google/brya/variants/marasov/memory/Makefile.inc @@ -1,5 +1,10 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is an auto-generated file. Do not edit!! -# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. +# Generated by: +# ./util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/marasov/memory/ src/mainboard/google/brya/variants/marasov/memory/mem_parts_used.txt -SPD_SOURCES = placeholder +SPD_SOURCES = +SPD_SOURCES += spd/lp5/set-0/spd-1.hex # ID = 0(0b0000) Parts = MT62F512M32D2DR-031 WT:B +SPD_SOURCES += spd/lp5/set-0/spd-1.hex # ID = 1(0b0001) Parts = H9JCNNNBK3MLYR-N6E +SPD_SOURCES += spd/lp5/set-0/spd-2.hex # ID = 4(0b0100) Parts = MT62F1G32D4DR-031 WT:B +SPD_SOURCES += spd/lp5/set-0/spd-3.hex # ID = 5(0b0101) Parts = K3LKBKB0BM-MGCP diff --git a/src/mainboard/google/brya/variants/marasov/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/marasov/memory/dram_id.generated.txt index fa24790..fc776ad 100644 --- a/src/mainboard/google/brya/variants/marasov/memory/dram_id.generated.txt +++ b/src/mainboard/google/brya/variants/marasov/memory/dram_id.generated.txt @@ -1 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# ./util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/marasov/memory/ src/mainboard/google/brya/variants/marasov/memory/mem_parts_used.txt + DRAM Part Name ID to assign +MT62F512M32D2DR-031 WT:B 0 (0000) +H9JCNNNBK3MLYR-N6E 1 (0001) +MT62F1G32D4DR-031 WT:B 4 (0100) +K3LKBKB0BM-MGCP 5 (0101) diff --git a/src/mainboard/google/brya/variants/marasov/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/marasov/memory/mem_parts_used.txt index 9621137..dc26979 100644 --- a/src/mainboard/google/brya/variants/marasov/memory/mem_parts_used.txt +++ b/src/mainboard/google/brya/variants/marasov/memory/mem_parts_used.txt @@ -9,3 +9,7 @@ # See util/spd_tools/README.md for more details and instructions. # Part Name +MT62F512M32D2DR-031 WT:B +H9JCNNNBK3MLYR-N6E +MT62F1G32D4DR-031 WT:B +K3LKBKB0BM-MGCP -- To view, visit https://review.coreboot.org/c/coreboot/+/69311 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifa0637b47d0017cdb9e26ed32328f4405c0df3f7 Gerrit-Change-Number: 69311 Gerrit-PatchSet: 1 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-MessageType: newchange

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[XL] Change in coreboot[master]: cpu/x86: Drop LEGACY_SMP_INIT
by 9elements QA (Code Review) 08 Nov '22

08 Nov '22

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69121 ) Change subject: cpu/x86: Drop LEGACY_SMP_INIT ...................................................................... Patch Set 16: Automatic boot test returned (PASS/FAIL/TOTAL): 15 / 1 / 16 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/134391 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/134390 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/134389 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/134388 FAIL: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/134387 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/134386 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/134385 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/134384 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/134383 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/134382 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/134381 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/134380 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/134379 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/134378 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/134377 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/134376 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/69121 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e90f457f3979781d06323ef1350d5fb05a6be43 Gerrit-Change-Number: 69121 Gerrit-PatchSet: 16 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Tue, 08 Nov 2022 02:27:06 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mem_chip_info: Update to new format
by Julius Werner (Code Review) 08 Nov '22

08 Nov '22

Attention is currently required from: Hung-Te Lin. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68871 ) Change subject: mem_chip_info: Update to new format ...................................................................... Patch Set 4: (5 comments) Patchset: PS4: > BTW, is it possible to have speed (frequency) in future? Uff... I mean it would but I was really hoping I could finalize this now... We were planning to only use this for part identification, so frequency isn't really needed for that. I guess it seems like a reasonable enough thing to add just as a precaution, if we still have time for that. I'm not really sure what the appropriate layer would be to model frequency here... I guess at the channel level? Can different channels theoretically run different frequencies? Or should it just be a toplevel value? (And for the data type I guess a `uint32_t frequency_mhz` -- or an enum? Is there going to be confusion between 1866 and 1867 depending on how people round? What should systems like Kevin put in where the frequency is technically 928MHz for SI reasons but the "common" frequency slot in that vicinity is 933?) Also, of course, this would just be boot frequency and most devices have some form of dynamic frequency scaling these days (which also implies that the kernel must obviously know the possible frequency values through other means already anyway). Is that still a valuable thing to report here, then? I'm not even sure if it's guaranteed that this frequency is always the highest possible one. File src/commonlib/bsd/include/commonlib/bsd/mem_chip_info.h: https://review.coreboot.org/c/coreboot/+/68871/comment/d4b1a722_c171513c PS3, Line 72: struct_version > > since it always takes them forever to make a new update […] Well, changing this structure is also cumbersome for us independent of Qualcomm. The payload interface is supposed to be stable, so if we ever want to make changes here again (at least after we really start using it) we would have to have structs describing both layouts and code in depthcharge parsing both layouts etc... I hope we can avoid all that. File src/soc/mediatek/common/memory.c: https://review.coreboot.org/c/coreboot/+/68871/comment/1fc739cd_57e227f2 PS3, Line 129: ddr->mrr_info.mr8_density[r] > @yuping: right. […] Ack https://review.coreboot.org/c/coreboot/+/68871/comment/ca63d6fc_40c919f3 PS3, Line 150: size = sizeof(*mc) + : sizeof(struct mem_chip_entry) * CHANNEL_MAX * curr_ddr_info->mrr_info.rank_nums; > Is it possible to refactor mem_chip_info_size() to take a 'entries' parameter so both MTK and QC can […] Done https://review.coreboot.org/c/coreboot/+/68871/comment/3464a158_60e30c67 PS3, Line 155: fill_dram_info > can we do memset(mc, 0, size) first so there's no need to do reserve[0] = 0, reserve[1] = 0 in the f […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/68871 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If34e6857439b6f6ab225344e5b4dd0ff11d8d42a Gerrit-Change-Number: 68871 Gerrit-PatchSet: 4 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-CC: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-CC: Yidi Lin <yidilin(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Comment-Date: Tue, 08 Nov 2022 02:15:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Hung-Te Lin <hungte(a)chromium.org> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mem_chip_info: Update to new format
by Julius Werner (Code Review) 08 Nov '22

08 Nov '22

Attention is currently required from: Julius Werner, Angel Pons. Hello Hung-Te Lin, Shelley Chen, Angel Pons, Xixi Chen, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68871 to look at the new patch set (#5). Change subject: mem_chip_info: Update to new format ...................................................................... mem_chip_info: Update to new format The original version of the mem_chip_info structure does not record rank information and does not allow precise modeling of certain DDR configurations, so it falls short on its purpose to compile all available memory information. This patch updates the format to a new layout that remedies these issues. Since the structure was introduced so recently that no firmware using it has been finalized and shipped yet, we should be able to get away with this without accounting for backwards compatibility. BRANCH=corsola Cq-Depend: chromium:3980175 Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: If34e6857439b6f6ab225344e5b4dd0ff11d8d42a --- M src/commonlib/bsd/include/commonlib/bsd/mem_chip_info.h M src/soc/mediatek/common/memory.c M src/soc/qualcomm/common/qclib.c 3 files changed, 123 insertions(+), 31 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/68871/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/68871 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If34e6857439b6f6ab225344e5b4dd0ff11d8d42a Gerrit-Change-Number: 68871 Gerrit-PatchSet: 5 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-CC: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-CC: Yidi Lin <yidilin(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: src/drivers/ipmi: retry ipmi_get_device_id in ipmi_kcs_init
by Johnny Lin (Code Review) 08 Nov '22

08 Nov '22

Attention is currently required from: TangYiwei. Hello TangYiwei, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/69310 to review the following change. Change subject: src/drivers/ipmi: retry ipmi_get_device_id in ipmi_kcs_init ...................................................................... src/drivers/ipmi: retry ipmi_get_device_id in ipmi_kcs_init Without this retry there's a chance that ipmi_get_device_id failed then ipmi device won't be enabled. Change-Id: I2b972c905fb0f8223570212432a4a10bd715f3f7 Signed-off-by: Yiwei Tang <tangyiwei.2022(a)bytedance.com> Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> --- M src/drivers/ipmi/ipmi_kcs_ops.c 1 file changed, 43 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/69310/1 diff --git a/src/drivers/ipmi/ipmi_kcs_ops.c b/src/drivers/ipmi/ipmi_kcs_ops.c index 28ced49..8fc8fa0 100644 --- a/src/drivers/ipmi/ipmi_kcs_ops.c +++ b/src/drivers/ipmi/ipmi_kcs_ops.c @@ -63,6 +63,7 @@ uint32_t man_id = 0, prod_id = 0; struct drivers_ipmi_config *conf = dev->chip_info; const struct gpio_operations *gpio_ops; + int retries = 10; if (!conf) { printk(BIOS_WARNING, "IPMI: chip_info is missing! Skip init.\n"); @@ -116,31 +117,37 @@ /* Don't write tables if communication failed */ dev->enabled = 0; - if (!ipmi_get_device_id(dev, &rsp)) { - /* Queried the IPMI revision from BMC */ - ipmi_revision_minor = IPMI_IPMI_VERSION_MINOR(rsp.ipmi_version); - ipmi_revision_major = IPMI_IPMI_VERSION_MAJOR(rsp.ipmi_version); - - bmc_revision_major = rsp.fw_rev1; - bmc_revision_minor = rsp.fw_rev2; - - memcpy(&man_id, rsp.manufacturer_id, - sizeof(rsp.manufacturer_id)); - - memcpy(&prod_id, rsp.product_id, sizeof(rsp.product_id)); - - printk(BIOS_INFO, "IPMI: Found man_id 0x%06x, prod_id 0x%04x\n", - man_id, prod_id); - - printk(BIOS_INFO, "IPMI: Version %01x.%01x\n", - ipmi_revision_major, ipmi_revision_minor); - } else { - /* Don't write tables if communication failed */ - dev->enabled = 0; + while (ipmi_get_device_id(dev, &rsp)) { + retries--; + printk(BIOS_DEBUG, "IPMI: BMC does not respond to get device id, %d retries left\n", + retries); + if (retries == 0) { + dev->enabled = 0; + break; + } + mdelay(1000); } - if (!dev->enabled) + if (!dev->enabled) { + printk(BIOS_ERR, "IPMI: BMC does not respond to get device id even after retries.\n"); return; + } + + /* Queried the IPMI revision from BMC */ + ipmi_revision_minor = IPMI_IPMI_VERSION_MINOR(rsp.ipmi_version); + ipmi_revision_major = IPMI_IPMI_VERSION_MAJOR(rsp.ipmi_version); + + bmc_revision_major = rsp.fw_rev1; + bmc_revision_minor = rsp.fw_rev2; + + memcpy(&man_id, rsp.manufacturer_id, sizeof(rsp.manufacturer_id)); + + memcpy(&prod_id, rsp.product_id, sizeof(rsp.product_id)); + + printk(BIOS_INFO, "IPMI: Found man_id 0x%06x, prod_id 0x%04x\n", man_id, prod_id); + + printk(BIOS_INFO, "IPMI: Version %01x.%01x\n", ipmi_revision_major, + ipmi_revision_minor); if (CONFIG(DRIVERS_IPMI_SUPERMICRO_OEM)) supermicro_ipmi_oem(dev->path.pnp.port); -- To view, visit https://review.coreboot.org/c/coreboot/+/69310 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b972c905fb0f8223570212432a4a10bd715f3f7 Gerrit-Change-Number: 69310 Gerrit-PatchSet: 1 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: TangYiwei Gerrit-Attention: TangYiwei Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: acpi: Add initial support for CEDT
by Jonathan Zhang (Code Review) 08 Nov '22

08 Nov '22

Attention is currently required from: Arthur Heymans, Jonathan Zhang, Tim Wawrzynczak, Paul Menzel. Hello Lance Zhao, Arthur Heymans, Marc Jones, Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/64263 to look at the new patch set (#7). Change subject: acpi: Add initial support for CEDT ...................................................................... acpi: Add initial support for CEDT Add initial CEDT (CXL Early Discovery Table) support based on CXL spec 2.0 section 9.14.1. Add functions to create CEDT table (revision 1) and create CEDT CXL Host Bridge Structure (CHBS) and CXL Fixed Memory Windows Structure (CFMWS). TESTED=Create CEDT table on Intel Archer City CRB, dumped the CEDT table and examined the content. Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com> Change-Id: I4fbce78efc86ad9f2468c37b4827a6dadbdc6802 --- M src/acpi/acpi.c M src/include/acpi/acpi.h 2 files changed, 160 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/64263/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/64263 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4fbce78efc86ad9f2468c37b4827a6dadbdc6802 Gerrit-Change-Number: 64263 Gerrit-PatchSet: 7 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: mb/google/brya/marasov: Add memory config for marasov
by Frank Chu (Code Review) 08 Nov '22

08 Nov '22

Attention is currently required from: Tarun Tuli, Kyle Lin. Hello build bot (Jenkins), Tarun Tuli, Kyle Lin, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69149 to look at the new patch set (#7). Change subject: mb/google/brya/marasov: Add memory config for marasov ...................................................................... mb/google/brya/marasov: Add memory config for marasov Configure the rcomp, dqs and dq tables based on the schematic. BUG=b:254365935 BRANCH=None TEST=Built successfully Signed-off-by: Frank Chu <Frank_Chu(a)pegatron.corp-partner.google.com> Change-Id: I8c9541006828deae83e2ae4a860f40d7433662d4 --- A src/mainboard/google/brya/variants/marasov/Makefile.inc A src/mainboard/google/brya/variants/marasov/memory.c 2 files changed, 131 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/69149/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/69149 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8c9541006828deae83e2ae4a860f40d7433662d4 Gerrit-Change-Number: 69149 Gerrit-PatchSet: 7 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Kyle Lin <kylelinck(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kyle Lin <kylelinck(a)google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mb/google/var/marasov: Generate SPD ID for supported memory parts
by Frank Chu (Code Review) 08 Nov '22

08 Nov '22

Attention is currently required from: Tarun Tuli, Kyle Lin, Tim Wawrzynczak. Hello build bot (Jenkins), Tarun Tuli, Kyle Lin, Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68627 to look at the new patch set (#4). Change subject: mb/google/var/marasov: Generate SPD ID for supported memory parts ...................................................................... mb/google/var/marasov: Generate SPD ID for supported memory parts Add supported memory parts in mem_parts_used list, and generate SPD ID for these parts. DRAM Part Name ID to assign MT62F512M32D2DR-031 WT:B 0 (0000) H9JCNNNBK3MLYR-N6E 1 (0001) MT62F1G32D4DR-031 WT:B 4 (0100) K3LKBKB0BM-MGCP 5 (0101) BUG=b:254365935 BRANCH=None TEST=run part_id_gen to generate SPD id Signed-off-by: FrankChu <frank_chu(a)pegatron.corp-partner.google.com> Change-Id: I53a4c551e7a2dda9770531e977caf36c108c8647 --- M src/mainboard/google/brya/variants/marasov/memory/Makefile.inc M src/mainboard/google/brya/variants/marasov/memory/dram_id.generated.txt M src/mainboard/google/brya/variants/marasov/memory/mem_parts_used.txt 3 files changed, 43 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/68627/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/68627 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I53a4c551e7a2dda9770531e977caf36c108c8647 Gerrit-Change-Number: 68627 Gerrit-PatchSet: 4 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Kyle Lin <kylelinck(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kyle Lin <kylelinck(a)google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: [test]mb/google/brya/marasov: Add memory config for marasov
by Frank Chu (Code Review) 08 Nov '22

08 Nov '22

Attention is currently required from: Tarun Tuli. Frank Chu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69149 ) Change subject: [test]mb/google/brya/marasov: Add memory config for marasov ...................................................................... Patch Set 6: Code-Review+1 This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/69149 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8c9541006828deae83e2ae4a860f40d7433662d4 Gerrit-Change-Number: 69149 Gerrit-PatchSet: 6 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Comment-Date: Tue, 08 Nov 2022 01:36:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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