Attention is currently required from: Bill XIE, Paul Menzel.
Hello build bot (Jenkins), Paul Menzel, Tim Wawrzynczak, Angel Pons, Arthur Heymans, Lean Sheng Tan,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/69215
to look at the new patch set (#5).
Change subject: cpu/x86/mp_init.c: Handle dummy nodes in cpu bus
......................................................................
cpu/x86/mp_init.c: Handle dummy nodes in cpu bus
commit 48c825ebd1beadb8ac4fd3ae687a36ff4705ab7a assumes that
(g_)cpu_bus->children->sibling represents the first AP cpu, but this
is not true when device tree (like mb/asus/p8x7x-series/devicetree.cb)
contains static dummy lapic nodes. In such case, Linux kernel can find
one cpu unable to wake up, and an additional working cpu without
corresponding ACPI firmware node:
smpboot: Allowing 5 CPUs, 0 hotplug CPUs
smpboot: CPU0: Intel(R) Xeon(R) CPU E3-1225 V2 @ 3.20GHz (family:
0x6, model: 0x3a, stepping: 0x9)
smpboot: do_boot_cpu failed(-1) to wakeup CPU#2
This could be resolved by skipping disabled cpu nodes.
Signed-off-by: Bill XIE <persmule(a)hardenedlinux.org>
Change-Id: I1075bc52091e619ef79cbeab0a0f6b57cff1d708
---
M src/cpu/x86/mp_init.c
1 file changed, 31 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/69215/5
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Kangheui Won has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69312 )
Change subject: mb/google/nissa/var/xivu: Add Hynix new memory support
......................................................................
Patch Set 1: Code-Review+2
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Change subject: soc/intel/common: Remove the option to send EOP early
......................................................................
Patch Set 3:
(2 comments)
Patchset:
PS3:
> @subrata Any feedback on this? Or could we merge PS:1 as to avoid problems in master?
I agree with just PS1 and we can work together with Intel to get the recommendations around sending EOP early. If seems not required, we can always drop that later.
File src/soc/intel/alderlake/chip.c:
https://review.coreboot.org/c/coreboot/+/67760/comment/db65a314_284fa0f9
PS1, Line 207: 0)
can we use the macro instead `0` to define the ME state?
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Change subject: soc/intel/common: add units to soc_power_limits_config elements
......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/starlabs/lite/devtree.c:
https://review.coreboot.org/c/coreboot/+/69206/comment/7f7005e7_f0bd927f
PS1, Line 43: cfg->tcc_offset = 5;
> nit: Alignment
Hi Sean,
Do you need my help to correct the alignment?
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Change subject: mb/google/brya/gaelin: Configure devicetree settings
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Patch Set 2: Code-Review+1
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Change subject: soc/intel/common: add units to soc_power_limits_config elements
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