coreboot-gerrit November 2022

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[S] Change in coreboot[master]: soc/intel/alderlake: Check MANUF_LOCK when logging manufacturing mode
by Sridhar Siricilla (Code Review) 08 Nov '22

08 Nov '22

Attention is currently required from: Tarun Tuli, Michał Żygowski, Kangheui Won, Reka Norman, Rizwan Qureshi. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69324 ) Change subject: soc/intel/alderlake: Check MANUF_LOCK when logging manufacturing mode ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/alderlake/me.c: https://review.coreboot.org/c/coreboot/+/69324/comment/c7c0265e_8381777f PS1, Line 141: hfsts1.fields.mfg_mode > This bit only reflects the regions' writability in flash descriptor. […] Originally, the bit is named as spi_protection since it indicates writability to flash descriptor. But, recently it got updated incorrectly. This has to be reverted to avoid the confusion. >So basically fpf_soc_lock and manuf_lock should be the only bits to be checked, shouldn't they? As part of staged EOM. these 3 conditions together reflect the EOM state. Hence, firmware has to check these 3 conditions. -- To view, visit https://review.coreboot.org/c/coreboot/+/69324 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iac605baa291ab5cc5f28464006f4828c12c748fe Gerrit-Change-Number: 69324 Gerrit-PatchSet: 1 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Comment-Date: Tue, 08 Nov 2022 13:41:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: arch/x86: Use 'enum cb_err'
by Elyes Haouas (Code Review) 08 Nov '22

08 Nov '22

Attention is currently required from: Angel Pons. Hello build bot (Jenkins), Paul Menzel, Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68369 to look at the new patch set (#2). Change subject: arch/x86: Use 'enum cb_err' ...................................................................... arch/x86: Use 'enum cb_err' Change-Id: I38e4b8c6adfaaa45377b2fbe0644285d21841cd1 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/arch/x86/pirq_routing.c M src/arch/x86/postcar_loader.c M src/arch/x86/rdrand.c M src/include/random.h 4 files changed, 30 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/68369/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68369 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I38e4b8c6adfaaa45377b2fbe0644285d21841cd1 Gerrit-Change-Number: 68369 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: soc/intel/ehl: Add EHL MDIO operation
by Mario Scheithauer (Code Review) 08 Nov '22

08 Nov '22

Attention is currently required from: Angel Pons, Lean Sheng Tan, Werner Zeh. Mario Scheithauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69383 ) Change subject: soc/intel/ehl: Add EHL MDIO operation ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Hi Angel, it was some time ago, when I had already tried to implement a PHY driver. https://review.coreboot.org/c/coreboot/+/64024 At that time, you had talked about a way via ops_mdio. I have now tried to implement something this way. What do you think of this, could this be a valid way? Thank you already for looking over. -- To view, visit https://review.coreboot.org/c/coreboot/+/69383 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5d1b9dd2f2ba8c18291fff314c13f0c3851784aa Gerrit-Change-Number: 69383 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Tue, 08 Nov 2022 13:33:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: drivers/phy/m88e1512: Provide functionality to customize LED status
by build bot (Jenkins) (Code Review) 08 Nov '22

08 Nov '22

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69386 ) Change subject: drivers/phy/m88e1512: Provide functionality to customize LED status ...................................................................... Patch Set 1: (1 comment) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-162967): https://review.coreboot.org/c/coreboot/+/69386/comment/4d7b8c8a_f2f3f277 PS1, Line 14: https://www.marvell.com/content/dam/marvell/en/public-collateral/phys-trans… Possible unwrapped commit description (prefer a maximum 72 chars per line) -- To view, visit https://review.coreboot.org/c/coreboot/+/69386 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia71c43f4286f9201f03cb759252ebb405ab81904 Gerrit-Change-Number: 69386 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 08 Nov 2022 13:31:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: emulation/qemu-i440fx/fw_cfg.c: Use 'enum cb_err'
by Elyes Haouas (Code Review) 08 Nov '22

08 Nov '22

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69327 ) Change subject: emulation/qemu-i440fx/fw_cfg.c: Use 'enum cb_err' ...................................................................... emulation/qemu-i440fx/fw_cfg.c: Use 'enum cb_err' Also sort includes. Change-Id: I3ddab932eaff647270681171725cefd73e3939d8 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/mainboard/emulation/qemu-i440fx/fw_cfg.c 1 file changed, 28 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/69327/1 diff --git a/src/mainboard/emulation/qemu-i440fx/fw_cfg.c b/src/mainboard/emulation/qemu-i440fx/fw_cfg.c index 5c23988..f1be734 100644 --- a/src/mainboard/emulation/qemu-i440fx/fw_cfg.c +++ b/src/mainboard/emulation/qemu-i440fx/fw_cfg.c @@ -1,13 +1,15 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpi.h> +#include <arch/io.h> +#include <commonlib/bsd/helpers.h> +#include <commonlib/endian.h> +#include <console/console.h> #include <endian.h> +#include <smbios.h> #include <stdlib.h> #include <string.h> -#include <smbios.h> -#include <console/console.h> -#include <arch/io.h> -#include <acpi/acpi.h> -#include <commonlib/endian.h> +#include <types.h> #include "fw_cfg.h" #include "fw_cfg_if.h" @@ -61,7 +63,7 @@ fw_cfg_read(dst, dstlen); } -static int fw_cfg_find_file(FWCfgFile *file, const char *name) +static enum cb_err fw_cfg_find_file(FWCfgFile *file, const char *name) { uint32_t count = 0; @@ -75,11 +77,11 @@ file->size = be32_to_cpu(file->size); file->select = be16_to_cpu(file->select); printk(BIOS_INFO, "QEMU: firmware config: Found '%s'\n", name); - return 0; + return CB_SUCCESS; } } printk(BIOS_INFO, "QEMU: firmware config: Couldn't find '%s'\n", name); - return -1; + return CB_ERR; } int fw_cfg_check_file(FWCfgFile *file, const char *name) @@ -89,26 +91,26 @@ return fw_cfg_find_file(file, name); } -static int fw_cfg_e820_select(uint32_t *size) +static enum cb_err fw_cfg_e820_select(uint32_t *size) { FWCfgFile file; if (!fw_cfg_present() || fw_cfg_find_file(&file, "etc/e820")) - return -1; + return CB_ERR; fw_cfg_select(file.select); *size = file.size; - return 0; + return CB_SUCCESS; } -static int fw_cfg_e820_read(FwCfgE820Entry *entry, uint32_t *size, +static enum cb_err fw_cfg_e820_read(FwCfgE820Entry *entry, uint32_t *size, uint32_t *pos) { if (*pos + sizeof(*entry) > *size) - return -1; + return CB_ERR; fw_cfg_read(entry, sizeof(*entry)); *pos += sizeof(*entry); - return 0; + return CB_SUCCESS; } /* returns tolud on success or 0 on failure */ -- To view, visit https://review.coreboot.org/c/coreboot/+/69327 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3ddab932eaff647270681171725cefd73e3939d8 Gerrit-Change-Number: 69327 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: mb/siemens/mc_ehl2: Enable Marvell PHY 88E1512 driver
by Mario Scheithauer (Code Review) 08 Nov '22

08 Nov '22

Attention is currently required from: Werner Zeh. Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69387 ) Change subject: mb/siemens/mc_ehl2: Enable Marvell PHY 88E1512 driver ...................................................................... mb/siemens/mc_ehl2: Enable Marvell PHY 88E1512 driver This mainboard has three Marvel PHYs connected to the internal SOC GbE controllers. The default LED status after HW reset of this PHYs shows a different mode than what is needed. This patch sets the following LED status: LED[0] - 7 = On - 1000 Mbps Link, Off - Else LED[1] - 1 = On - Link, Blink - Activity, Off - No Link TEST=Try different register values to verify LED feature. Change-Id: I51d817bc720bf787279777f503efdc17dbb1274d Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/siemens/mc_ehl/variants/mc_ehl2/Kconfig M src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb 2 files changed, 51 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/69387/1 diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/Kconfig b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/Kconfig index 00875fb..a3aba3a 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/Kconfig +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/Kconfig @@ -6,6 +6,7 @@ select DRIVER_INTEL_I210 select SOC_INTEL_COMMON_BLOCK_LPC_COMB_ENABLE select EHL_TSN_DRIVER + select DRIVERS_PHY_M88E1512 config FMDFILE default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/mc_ehl.fmd" diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb index 4109ec9..492122a 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb @@ -161,12 +161,39 @@ device pci 1c.6 on end # RP7 (pcie3 multi VC) device pci 1d.0 off end # Intel PSE IPC (local host to PSE) - device pci 1d.1 on end # Intel PSE Time-Sensitive Networking GbE 0 - device pci 1d.2 on end # Intel PSE Time-Sensitive Networking GbE 1 + device pci 1d.1 on # Intel PSE Time-Sensitive Networking GbE 0 + # Enable external Marvell PHY 88E1512 + chip drivers/phy/m88e1512 + register "led_customize" = "1" + # LED[0]: On - 1000 Mbps Link, Off - Else + # LED[1]: On - Link, Blink - Activity, Off - No Link + register "led_ctrl" = "0x17" + device pnp 0.0 on end # PHY address + end + end + device pci 1d.2 on # Intel PSE Time-Sensitive Networking GbE 1 + # Enable external Marvell PHY 88E1512 + chip drivers/phy/m88e1512 + register "led_customize" = "1" + # LED[0]: On - 1000 Mbps Link, Off - Else + # LED[1]: On - Link, Blink - Activity, Off - No Link + register "led_ctrl" = "0x17" + device pnp 0.1 on end # PHY address + end + end device pci 1e.0 on end # UART0 device pci 1e.1 on end # UART1 - device pci 1e.4 on end # PCH Time-Sensitive Networking GbE + device pci 1e.4 on # PCH Time-Sensitive Networking GbE + # Enable external Marvell PHY 88E1512 + chip drivers/phy/m88e1512 + register "led_customize" = "1" + # LED[0]: On - 1000 Mbps Link, Off - Else + # LED[1]: On - Link, Blink - Activity, Off - No Link + register "led_ctrl" = "0x17" + device pnp 1.1 on end # PHY address + end + end device pci 1f.0 on # eSPI Interface chip drivers/pc80/tpm -- To view, visit https://review.coreboot.org/c/coreboot/+/69387 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I51d817bc720bf787279777f503efdc17dbb1274d Gerrit-Change-Number: 69387 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: drivers/phy/m88e1512: Provide functionality to customize LED status
by Mario Scheithauer (Code Review) 08 Nov '22

08 Nov '22

Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69386 ) Change subject: drivers/phy/m88e1512: Provide functionality to customize LED status ...................................................................... drivers/phy/m88e1512: Provide functionality to customize LED status For Marvel PHY it could be necessary to customize the shown LED status at the connector. The LED status can be changed via PHY Function Control Register on page 3. Link to the Marvell PHY 88E1512 datasheet: https://www.marvell.com/content/dam/marvell/en/public-collateral/phys-trans… Change-Id: Ia71c43f4286f9201f03cb759252ebb405ab81904 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- A src/drivers/phy/m88e1512/chip.h M src/drivers/phy/m88e1512/m88e1512.c A src/drivers/phy/m88e1512/m88e1512.h 3 files changed, 70 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/69386/1 diff --git a/src/drivers/phy/m88e1512/chip.h b/src/drivers/phy/m88e1512/chip.h new file mode 100644 index 0000000..e22a087 --- /dev/null +++ b/src/drivers/phy/m88e1512/chip.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include "m88e1512.h" + +struct drivers_phy_m88e1512_config { + unsigned char led_customize; /* Enable LED customization */ + unsigned char led_ctrl; /* LED[1:0] Control */ +}; diff --git a/src/drivers/phy/m88e1512/m88e1512.c b/src/drivers/phy/m88e1512/m88e1512.c index 7da0651..81c77e6 100644 --- a/src/drivers/phy/m88e1512/m88e1512.c +++ b/src/drivers/phy/m88e1512/m88e1512.c @@ -1,9 +1,41 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <console/console.h> #include <device/device.h> +#include <device/mdio.h> +#include <device/pci.h> +#include <soc/mdio.h> +#include "chip.h" +#include "m88e1512.h" static void m88e1512_init(struct device *dev) { + const struct mdio_operations *mdio_ops; + struct drivers_phy_m88e1512_config *config = dev->chip_info; + uint16_t page_reg; + + mdio_ops = dev_get_mdio_ops(dev->bus->dev); + + /* Customize LEDs if led_ctrl is set. */ + if (mdio_ops && config->led_customize) { + printk(BIOS_DEBUG, "%s: Set a customized LED mode on 0x%x...\n", + dev->chip_ops->name, dev->bus->dev->device); + + /* Select page 3 to access LED function control register. */ + mdio_ops->write(dev->bus->dev, dev->path.pnp.device, + PHY_MDIO_PAGE_ANY_ADR_REG, PHY_MDIO_PAGE_3_SEL); + + /* Modify PHY LED mode. */ + page_reg = mdio_ops->read(dev->bus->dev, dev->path.pnp.device, + PHY_MDIO_LED_FUNC_CTRL_REG); + clrsetbits16(&page_reg, PHY_MDIO_LED_FUNC_CTRL_MASK, config->led_ctrl); + mdio_ops->write(dev->bus->dev, dev->path.pnp.device, + PHY_MDIO_LED_FUNC_CTRL_REG, page_reg); + + /* Select page back to 0. */ + mdio_ops->write(dev->bus->dev, dev->path.pnp.device, + PHY_MDIO_PAGE_ANY_ADR_REG, PHY_MDIO_PAGE_0_SEL); + } } static struct device_operations m88e1512_ops = { diff --git a/src/drivers/phy/m88e1512/m88e1512.h b/src/drivers/phy/m88e1512/m88e1512.h new file mode 100644 index 0000000..90ada1a --- /dev/null +++ b/src/drivers/phy/m88e1512/m88e1512.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _PHY_M88E1512_H_ +#define _PHY_M88E1512_H_ + +/* Register layout */ +#define PHY_MDIO_PAGE_ANY_ADR_REG 0x16 +#define PHY_MDIO_PAGE_0_SEL 0 +#define PHY_MDIO_PAGE_3_SEL 3 +#define PHY_MDIO_LED_FUNC_CTRL_REG 0x10 +#define PHY_MDIO_LED_FUNC_CTRL_MASK 0x00FF + +#endif /* _PHY_M88E1512_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/69386 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia71c43f4286f9201f03cb759252ebb405ab81904 Gerrit-Change-Number: 69386 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/intel/elkhartlake: Enable 'scan_bus' on TSN GbE
by Mario Scheithauer (Code Review) 08 Nov '22

08 Nov '22

Attention is currently required from: Lean Sheng Tan, Werner Zeh. Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69385 ) Change subject: soc/intel/elkhartlake: Enable 'scan_bus' on TSN GbE ...................................................................... soc/intel/elkhartlake: Enable 'scan_bus' on TSN GbE For extern PHY access it is necessary to enable the 'scan_bus' functionality. Change-Id: I88050df2059ec7e0b27a132bca626eaef3d5dfb0 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/soc/intel/elkhartlake/tsn_gbe.c 1 file changed, 14 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/69385/1 diff --git a/src/soc/intel/elkhartlake/tsn_gbe.c b/src/soc/intel/elkhartlake/tsn_gbe.c index 28ed0a4..d143418 100644 --- a/src/soc/intel/elkhartlake/tsn_gbe.c +++ b/src/soc/intel/elkhartlake/tsn_gbe.c @@ -88,6 +88,7 @@ .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, + .scan_bus = scan_generic_bus, .enable = gbe_tsn_enable, .init = gbe_tsn_init, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/69385 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I88050df2059ec7e0b27a132bca626eaef3d5dfb0 Gerrit-Change-Number: 69385 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: drivers/phy/m88e1512: Add new driver for Marvell PHY 88E1512
by Mario Scheithauer (Code Review) 08 Nov '22

08 Nov '22

Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69384 ) Change subject: drivers/phy/m88e1512: Add new driver for Marvell PHY 88E1512 ...................................................................... drivers/phy/m88e1512: Add new driver for Marvell PHY 88E1512 This driver enables the usage of an external Marvell PHY 88E1512 which should be connected to a SOC internal MAC controller. In a first step it is only the framework of the driver. Functionality will follow with a second patch. Change-Id: I24011860caa7bb206770f9779eb34b689293db10 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- A src/drivers/phy/m88e1512/Kconfig A src/drivers/phy/m88e1512/Makefile.inc A src/drivers/phy/m88e1512/m88e1512.c 3 files changed, 44 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/69384/1 diff --git a/src/drivers/phy/m88e1512/Kconfig b/src/drivers/phy/m88e1512/Kconfig new file mode 100644 index 0000000..8e9a2d9 --- /dev/null +++ b/src/drivers/phy/m88e1512/Kconfig @@ -0,0 +1,5 @@ +config DRIVERS_PHY_M88E1512 + bool + default n + help + Enable support for external Marvell PHY chip 88E1512. diff --git a/src/drivers/phy/m88e1512/Makefile.inc b/src/drivers/phy/m88e1512/Makefile.inc new file mode 100644 index 0000000..0d38051 --- /dev/null +++ b/src/drivers/phy/m88e1512/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_DRIVERS_PHY_M88E1512) += m88e1512.c diff --git a/src/drivers/phy/m88e1512/m88e1512.c b/src/drivers/phy/m88e1512/m88e1512.c new file mode 100644 index 0000000..7da0651 --- /dev/null +++ b/src/drivers/phy/m88e1512/m88e1512.c @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> + +static void m88e1512_init(struct device *dev) +{ +} + +static struct device_operations m88e1512_ops = { + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, + .init = m88e1512_init, +}; + +static void m88e1512_enable(struct device *dev) +{ + dev->ops = &m88e1512_ops; +} + +struct chip_operations drivers_phy_m88e1512_ops = { + CHIP_NAME("88E1512") + .enable_dev = m88e1512_enable +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/69384 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24011860caa7bb206770f9779eb34b689293db10 Gerrit-Change-Number: 69384 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: soc/intel/ehl: Add EHL MDIO operation
by Mario Scheithauer (Code Review) 08 Nov '22

08 Nov '22

Attention is currently required from: Lean Sheng Tan, Werner Zeh. Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69383 ) Change subject: soc/intel/ehl: Add EHL MDIO operation ...................................................................... soc/intel/ehl: Add EHL MDIO operation Previously, MDIO read/write access was only necessary for internal GbE TSN controller. For external MDIO access, it is necessary to provide a more general solution. This MDIO operation provides a read and write function which can be also used on mainboard level. Change-Id: I5d1b9dd2f2ba8c18291fff314c13f0c3851784aa Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/soc/intel/elkhartlake/Makefile.inc A src/soc/intel/elkhartlake/include/soc/mdio.h M src/soc/intel/elkhartlake/include/soc/tsn_gbe.h A src/soc/intel/elkhartlake/mdio.c M src/soc/intel/elkhartlake/tsn_gbe.c 5 files changed, 157 insertions(+), 83 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/69383/1 diff --git a/src/soc/intel/elkhartlake/Makefile.inc b/src/soc/intel/elkhartlake/Makefile.inc index 1ed11b4..6c8207f 100644 --- a/src/soc/intel/elkhartlake/Makefile.inc +++ b/src/soc/intel/elkhartlake/Makefile.inc @@ -32,6 +32,7 @@ ramstage-y += fsp_params.c ramstage-y += gpio.c ramstage-y += lockdown.c +ramstage-y += mdio.c ramstage-y += p2sb.c ramstage-y += pmc.c ramstage-y += reset.c diff --git a/src/soc/intel/elkhartlake/include/soc/mdio.h b/src/soc/intel/elkhartlake/include/soc/mdio.h new file mode 100644 index 0000000..c61a342 --- /dev/null +++ b/src/soc/intel/elkhartlake/include/soc/mdio.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_ELKHARTLAKE_MDIO_H_ +#define _SOC_ELKHARTLAKE_MDIO_H_ + +#define GMII_TIMEOUT_MS 20 + +#define MAC_MDIO_ADR 0x200 /* MAC MDIO Address register */ +#define MAC_MDIO_ADR_MASK 0x03FF7F0E +#define MAC_PHYAD(pa) (pa << 21) /* Physical Layer Address */ +#define MAC_REGAD(rda) (rda << 16) /* Register/Device Address */ +#define MAC_CLK_TRAIL_4 (4 << 12) /* 4 Trailing Clocks */ +#define MAC_CSR_CLK_DIV_102 (1 << 10) /* 0100: CSR=150-250 MHz; CSR/102 */ +#define MAC_OP_CMD_WRITE (1 << 2) /* GMII Operation Command Write */ +#define MAC_OP_CMD_READ (3 << 2) /* GMII Operation Command Read */ +#define MAC_GMII_BUSY (1 << 0) /* GMII Busy bit */ + +#define MAC_MDIO_DATA 0x204 /* MAC MDIO Data register */ + +/* + * Set mdio ops of the device to mdio dev ops. + */ +void mdio_dev_enable(struct device *dev); + +#endif /* _SOC_ELKHARTLAKE_MDIO_H_ */ diff --git a/src/soc/intel/elkhartlake/include/soc/tsn_gbe.h b/src/soc/intel/elkhartlake/include/soc/tsn_gbe.h index cd9f12e..ba037ed 100644 --- a/src/soc/intel/elkhartlake/include/soc/tsn_gbe.h +++ b/src/soc/intel/elkhartlake/include/soc/tsn_gbe.h @@ -8,18 +8,6 @@ #define TSN_MAC_ADD0_HIGH 0x300 /* MAC Address0 High register */ #define TSN_MAC_ADD0_LOW 0x304 /* MAC Address0 Low register */ -#define TSN_GMII_TIMEOUT_MS 20 - -#define TSN_MAC_MDIO_ADR 0x200 /* MAC MDIO Address register */ -#define TSN_MAC_MDIO_ADR_MASK 0x03FF7F0E -#define TSN_MAC_PHYAD(pa) (pa << 21) /* Physical Layer Address */ -#define TSN_MAC_REGAD(rda) (rda << 16) /* Register/Device Address */ -#define TSN_MAC_CLK_TRAIL_4 (4 << 12) /* 4 Trailing Clocks */ -#define TSN_MAC_CSR_CLK_DIV_102 (1 << 10) /* 0100: CSR=150-250 MHz; CSR/102 */ -#define TSN_MAC_OP_CMD_WRITE (1 << 2) /* GMII Operation Command Write */ -#define TSN_MAC_OP_CMD_READ (3 << 2) /* GMII Operation Command Read */ -#define TSN_MAC_GMII_BUSY (1 << 0) /* GMII Busy bit */ - /* MDIO - Adhoc PHY Sublayer Register */ #define TSN_MAC_MDIO_ADHOC_ADR 0x15 /* Global Configuration Register */ @@ -27,14 +15,8 @@ /* PHY to MAC Interrupt Polarity bit */ #define TSN_MAC_PHY2MAC_INTR_POL (1 << 6) -#define TSN_MAC_MDIO_DATA 0x204 /* MAC MDIO Data register */ - /* We need one function we can call to get a MAC address to use. */ /* This function can be coded somewhere else but must exist. */ enum cb_err mainboard_get_mac_address(struct device *dev, uint8_t mac[MAC_ADDR_LEN]); -enum cb_err phy_gmii_ready(void *base); -uint16_t tsn_mdio_read(void *base, uint8_t phy_adr, uint8_t reg_adr); -void tsn_mdio_write(void *base, uint8_t phy_adr, uint8_t reg_adr, uint16_t data); - #endif /* _SOC_ELKHARTLAKE_TSN_GBE_H_ */ diff --git a/src/soc/intel/elkhartlake/mdio.c b/src/soc/intel/elkhartlake/mdio.c new file mode 100644 index 0000000..7a7adbc --- /dev/null +++ b/src/soc/intel/elkhartlake/mdio.c @@ -0,0 +1,98 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#define __SIMPLE_DEVICE__ + +#include <console/console.h> +#include <device/mdio.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <soc/mdio.h> +#include <timer.h> + +static enum cb_err phy_gmii_ready(void *base) +{ + struct stopwatch sw; + + stopwatch_init_msecs_expire(&sw, GMII_TIMEOUT_MS); + do { + if (!(read32((base + MAC_MDIO_ADR)) & MAC_GMII_BUSY)) + return CB_SUCCESS; + + } while (!stopwatch_expired(&sw)); + + printk(BIOS_ERR, "%s Timeout after %lld msec\n", __func__, + stopwatch_duration_msecs(&sw)); + return CB_ERR; +} + +static uint16_t mdio_read(struct device *dev, uint8_t phy_adr, uint8_t reg_adr) +{ + uint16_t data = 0; + enum cb_err status; + /* Get the base address of the I/O registers in memory space */ + struct resource *gbe_tsn_res = find_resource(dev, PCI_BASE_ADDRESS_0); + void *io_mem_base = (void *)(uintptr_t)gbe_tsn_res->base; + + if (!io_mem_base) + return data; + + clrsetbits32(io_mem_base + MAC_MDIO_ADR, MAC_MDIO_ADR_MASK, + MAC_PHYAD(phy_adr) | MAC_REGAD(reg_adr) + | MAC_CLK_TRAIL_4 | MAC_CSR_CLK_DIV_102 + | MAC_OP_CMD_READ | MAC_GMII_BUSY); + + /* Wait for MDIO frame transfer to complete before reading MDIO DATA register */ + status = phy_gmii_ready(io_mem_base); + if (status == CB_ERR) { + printk(BIOS_ERR, "%s TSN GMII busy. PHY Adr: 0x%x, Reg 0x%x\n", + __func__, phy_adr, reg_adr); + } else { + data = read16(io_mem_base + MAC_MDIO_DATA); + printk(BIOS_DEBUG, "%s PHY Adr: 0x%x, Reg: 0x%x , Data: 0x%x\n", + __func__, phy_adr, reg_adr, data); + } + return data; +} + +static void mdio_write(struct device *dev, uint8_t phy_adr, uint8_t reg_adr, uint16_t data) +{ + enum cb_err status; + /* Get the base address of the I/O registers in memory space */ + struct resource *gbe_tsn_res = find_resource(dev, PCI_BASE_ADDRESS_0); + void *io_mem_base = (void *)(uintptr_t)gbe_tsn_res->base; + + if (!io_mem_base) + return; + + write16(io_mem_base + MAC_MDIO_DATA, data); + clrsetbits32(io_mem_base + MAC_MDIO_ADR, MAC_MDIO_ADR_MASK, + MAC_PHYAD(phy_adr) | MAC_REGAD(reg_adr) + | MAC_CLK_TRAIL_4 | MAC_CSR_CLK_DIV_102 + | MAC_OP_CMD_WRITE | MAC_GMII_BUSY); + + /* Wait for MDIO frame transfer to complete before do next */ + status = phy_gmii_ready(io_mem_base); + if (status == CB_ERR) + printk(BIOS_ERR, "%s TSN GMII busy. PHY Adr: 0x%x, Reg 0x%x\n", + __func__, phy_adr, reg_adr); + else + printk(BIOS_DEBUG, "%s PHY Adr: 0x%x, Reg: 0x%x , Data: 0x%x\n", + __func__, phy_adr, reg_adr, data); +} + +static struct mdio_operations mdio_ops = { + .read = mdio_read, + .write = mdio_write, +}; + +struct device_operations mdio_dev_ops = { + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, + .ops_mdio = &mdio_ops, +}; + +void mdio_dev_enable(struct device *dev) +{ + dev->ops = &mdio_dev_ops; +} diff --git a/src/soc/intel/elkhartlake/tsn_gbe.c b/src/soc/intel/elkhartlake/tsn_gbe.c index 2a1468c..28ed0a4 100644 --- a/src/soc/intel/elkhartlake/tsn_gbe.c +++ b/src/soc/intel/elkhartlake/tsn_gbe.c @@ -1,12 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <console/console.h> +#include <device/mdio.h> #include <device/pci.h> #include <device/pci_ids.h> #include <intelblocks/lpss.h> +#include <soc/mdio.h> #include <soc/soc_chip.h> #include <soc/tsn_gbe.h> -#include <timer.h> static void program_mac_address(struct device *dev, void *base) { @@ -29,74 +30,23 @@ (mac[3] << 24) | (mac[2] << 16) | (mac[1] << 8) | mac[0]); } -enum cb_err phy_gmii_ready(void *base) -{ - struct stopwatch sw; - stopwatch_init_msecs_expire(&sw, TSN_GMII_TIMEOUT_MS); - do { - if (!(read32((base + TSN_MAC_MDIO_ADR)) & TSN_MAC_GMII_BUSY)) - return CB_SUCCESS; - - } while (!stopwatch_expired(&sw)); - - printk(BIOS_ERR, "%s Timeout after %lld msec\n", __func__, - stopwatch_duration_msecs(&sw)); - return CB_ERR; -} - -uint16_t tsn_mdio_read(void *base, uint8_t phy_adr, uint8_t reg_adr) -{ - uint16_t data = 0; - enum cb_err status; - - clrsetbits32(base + TSN_MAC_MDIO_ADR, TSN_MAC_MDIO_ADR_MASK, - TSN_MAC_PHYAD(phy_adr) | TSN_MAC_REGAD(reg_adr) - | TSN_MAC_CLK_TRAIL_4 | TSN_MAC_CSR_CLK_DIV_102 - | TSN_MAC_OP_CMD_READ | TSN_MAC_GMII_BUSY); - - /* Wait for MDIO frame transfer to complete before reading MDIO DATA register */ - status = phy_gmii_ready(base); - if (status == CB_ERR) { - printk(BIOS_ERR, "%s TSN GMII busy. PHY Adr: 0x%x, Reg 0x%x\n", - __func__, phy_adr, reg_adr); - } else { - data = read16(base + TSN_MAC_MDIO_DATA); - printk(BIOS_DEBUG, "%s PHY Adr: 0x%x, Reg: 0x%x , Data: 0x%x\n", - __func__, phy_adr, reg_adr, data); - } - return data; -} - -void tsn_mdio_write(void *base, uint8_t phy_adr, uint8_t reg_adr, uint16_t data) -{ - enum cb_err status; - - write16(base + TSN_MAC_MDIO_DATA, data); - clrsetbits32(base + TSN_MAC_MDIO_ADR, TSN_MAC_MDIO_ADR_MASK, - TSN_MAC_PHYAD(phy_adr) | TSN_MAC_REGAD(reg_adr) - | TSN_MAC_CLK_TRAIL_4 | TSN_MAC_CSR_CLK_DIV_102 - | TSN_MAC_OP_CMD_WRITE | TSN_MAC_GMII_BUSY); - - /* Wait for MDIO frame transfer to complete before do next */ - status = phy_gmii_ready(base); - if (status == CB_ERR) - printk(BIOS_ERR, "%s TSN GMII busy. PHY Adr: 0x%x, Reg 0x%x\n", - __func__, phy_adr, reg_adr); - else - printk(BIOS_DEBUG, "%s PHY Adr: 0x%x, Reg: 0x%x , Data: 0x%x\n", - __func__, phy_adr, reg_adr, data); -} - -static void tsn_set_phy2mac_irq_polarity(void *base, enum tsn_phy_irq_polarity pol) +static void tsn_set_phy2mac_irq_polarity(struct device *dev, enum tsn_phy_irq_polarity pol) { uint16_t gcr_reg; + const struct mdio_operations *mdio_ops; + + mdio_ops = dev_get_mdio_ops(dev); + if (!mdio_ops) { + printk(BIOS_WARNING, "MDIO: specified mdio device is missing mdio ops!\n"); + return; + } if (pol == RISING_EDGE) { /* Read TSN adhoc PHY sublayer register - global configuration register */ - gcr_reg = tsn_mdio_read(base, TSN_MAC_MDIO_ADHOC_ADR, TSN_MAC_MDIO_GCR); + gcr_reg = mdio_ops->read(dev, TSN_MAC_MDIO_ADHOC_ADR, TSN_MAC_MDIO_GCR); gcr_reg |= TSN_MAC_PHY2MAC_INTR_POL; - tsn_mdio_write(base, TSN_MAC_MDIO_ADHOC_ADR, TSN_MAC_MDIO_GCR, gcr_reg); + mdio_ops->write(dev, TSN_MAC_MDIO_ADHOC_ADR, TSN_MAC_MDIO_GCR, gcr_reg); } } @@ -114,19 +64,22 @@ void *io_mem_base = (void *)(uintptr_t)gbe_tsn_res->base; config_t *config = config_of(dev); + /* Enable MDIO interface */ + mdio_dev_enable(dev); + /* Program MAC address */ program_mac_address(dev, io_mem_base); /* Set PHY-to-MAC IRQ polarity according to devicetree */ switch (dev->path.pci.devfn) { case PCH_DEVFN_GBE: - tsn_set_phy2mac_irq_polarity(io_mem_base, config->pch_tsn_phy_irq_edge); + tsn_set_phy2mac_irq_polarity(dev, config->pch_tsn_phy_irq_edge); break; case PCH_DEVFN_PSEGBE0: - tsn_set_phy2mac_irq_polarity(io_mem_base, config->pse_tsn_phy_irq_edge[0]); + tsn_set_phy2mac_irq_polarity(dev, config->pse_tsn_phy_irq_edge[0]); break; case PCH_DEVFN_PSEGBE1: - tsn_set_phy2mac_irq_polarity(io_mem_base, config->pse_tsn_phy_irq_edge[1]); + tsn_set_phy2mac_irq_polarity(dev, config->pse_tsn_phy_irq_edge[1]); break; } } -- To view, visit https://review.coreboot.org/c/coreboot/+/69383 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5d1b9dd2f2ba8c18291fff314c13f0c3851784aa Gerrit-Change-Number: 69383 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newchange

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