coreboot-gerrit November 2022

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[XL] Change in coreboot[master]: payloads/cbflashrom: Add new payload CBFlashrom
by Iman Bingi (Code Review) 08 Nov '22

08 Nov '22

Iman Bingi has uploaded a new patch set (#3). ( https://review.coreboot.org/c/coreboot/+/69328 ) Change subject: payloads/cbflashrom: Add new payload CBFlashrom ...................................................................... payloads/cbflashrom: Add new payload CBFlashrom Flashrom with Graphical User Interface. Depends on libpayload and nuklear. Features: * Graphical menus with scrolling. * Text rendering engine (atm only bitmap font) * Support for keyboard and mouse * Support for USB and PS/2 devices * Support for FAT32 file system (USB drives) * Works as ELF payload * Works as Seabios secondary payload * Runs in qemu and on real hardware Shortcomings: * Doesn't work in VGA text mode * Untested TODO: * Test on as many hardware/platforms as possible Change-Id: Ib523ae9eb002f14749942137e53add4986098314 Signed-off-by: Ben Adu-Boahen <imanbingy(a)gmail.com> --- M payloads/Kconfig M payloads/Makefile.inc A payloads/cbflashrom/.gitignore A payloads/cbflashrom/Kconfig A payloads/cbflashrom/Makefile A payloads/cbflashrom/NuklearUI/NuklearCBFlashrom.c A payloads/cbflashrom/NuklearUI/NuklearCBFlashrom.h A payloads/cbflashrom/NuklearUI/NuklearCheckbox.c A payloads/cbflashrom/NuklearUI/NuklearCheckbox.h A payloads/cbflashrom/NuklearUI/NuklearCommon.h A payloads/cbflashrom/NuklearUI/NuklearDataGrid.c A payloads/cbflashrom/NuklearUI/NuklearDataGrid.h A payloads/cbflashrom/NuklearUI/NuklearFieldFile.c A payloads/cbflashrom/NuklearUI/NuklearFieldFile.h A payloads/cbflashrom/NuklearUI/NuklearFieldHex.c A payloads/cbflashrom/NuklearUI/NuklearFieldHex.h A payloads/cbflashrom/NuklearUI/NuklearFileChooser.c A payloads/cbflashrom/NuklearUI/NuklearFileChooser.h A payloads/cbflashrom/NuklearUI/NuklearHex.c A payloads/cbflashrom/NuklearUI/NuklearHex.h A payloads/cbflashrom/NuklearUI/NuklearInput.c A payloads/cbflashrom/NuklearUI/NuklearInput.h A payloads/cbflashrom/NuklearUI/NuklearObject.c A payloads/cbflashrom/NuklearUI/NuklearObject.h A payloads/cbflashrom/NuklearUI/NuklearStyle.c A payloads/cbflashrom/NuklearUI/NuklearStyle.h A payloads/cbflashrom/NuklearUI/NuklearUI.h A payloads/cbflashrom/arch/x86/cpuid.c A payloads/cbflashrom/arch/x86/cpuid.h A payloads/cbflashrom/arch/x86/memcpy.c A payloads/cbflashrom/arch/x86/memcpy.h A payloads/cbflashrom/cbflashrom.c A payloads/cbflashrom/cbflashrom.h A payloads/cbflashrom/flashrom/82802ab.c A payloads/cbflashrom/flashrom/COPYING A payloads/cbflashrom/flashrom/Doxyfile A payloads/cbflashrom/flashrom/MAINTAINERS A payloads/cbflashrom/flashrom/Makefile A payloads/cbflashrom/flashrom/Makefile.include A payloads/cbflashrom/flashrom/README A payloads/cbflashrom/flashrom/amd_imc.c A payloads/cbflashrom/flashrom/at45db.c A payloads/cbflashrom/flashrom/atahpt.c A payloads/cbflashrom/flashrom/atavia.c A payloads/cbflashrom/flashrom/bitbang_spi.c A payloads/cbflashrom/flashrom/board_enable.c A payloads/cbflashrom/flashrom/buspirate_spi.c A payloads/cbflashrom/flashrom/cbtable.c A payloads/cbflashrom/flashrom/ch341a_spi.c A payloads/cbflashrom/flashrom/chipset_enable.c A payloads/cbflashrom/flashrom/cli_common.c A payloads/cbflashrom/flashrom/cli_output.c A payloads/cbflashrom/flashrom/custom_baud.c A payloads/cbflashrom/flashrom/dediprog.c A payloads/cbflashrom/flashrom/developerbox_spi.c A payloads/cbflashrom/flashrom/digilent_spi.c A payloads/cbflashrom/flashrom/dirtyjtag_spi.c A payloads/cbflashrom/flashrom/dmi.c A payloads/cbflashrom/flashrom/drkaiser.c A payloads/cbflashrom/flashrom/edi.c A payloads/cbflashrom/flashrom/en29lv640b.c A payloads/cbflashrom/flashrom/flashchips.c A payloads/cbflashrom/flashrom/flashrom.8.tmpl A payloads/cbflashrom/flashrom/flashrom.c A payloads/cbflashrom/flashrom/fmap.c A payloads/cbflashrom/flashrom/ft2232_spi.c A payloads/cbflashrom/flashrom/gfxnvidia.c A payloads/cbflashrom/flashrom/helpers.c A payloads/cbflashrom/flashrom/helpers_fileio.c A payloads/cbflashrom/flashrom/hwaccess_physmap.c A payloads/cbflashrom/flashrom/hwaccess_x86_io.c A payloads/cbflashrom/flashrom/hwaccess_x86_msr.c A payloads/cbflashrom/flashrom/ich_descriptors.c A payloads/cbflashrom/flashrom/ichspi.c A payloads/cbflashrom/flashrom/include/chipdrivers.h A payloads/cbflashrom/flashrom/include/coreboot_tables.h A payloads/cbflashrom/flashrom/include/custom_baud.h A payloads/cbflashrom/flashrom/include/edi.h A payloads/cbflashrom/flashrom/include/ene.h A payloads/cbflashrom/flashrom/include/flash.h A payloads/cbflashrom/flashrom/include/flashchips.h A payloads/cbflashrom/flashrom/include/fmap.h A payloads/cbflashrom/flashrom/include/hwaccess_physmap.h A payloads/cbflashrom/flashrom/include/hwaccess_x86_io.h A payloads/cbflashrom/flashrom/include/hwaccess_x86_msr.h A payloads/cbflashrom/flashrom/include/i2c_helper.h A payloads/cbflashrom/flashrom/include/ich_descriptors.h A payloads/cbflashrom/flashrom/include/layout.h A payloads/cbflashrom/flashrom/include/libflashrom.h A payloads/cbflashrom/flashrom/include/platform.h A payloads/cbflashrom/flashrom/include/platform/pci.h A payloads/cbflashrom/flashrom/include/platform/swap.h A payloads/cbflashrom/flashrom/include/programmer.h A payloads/cbflashrom/flashrom/include/spi.h A payloads/cbflashrom/flashrom/include/usb_device.h A payloads/cbflashrom/flashrom/include/writeprotect.h A payloads/cbflashrom/flashrom/internal.c A payloads/cbflashrom/flashrom/internal.h A payloads/cbflashrom/flashrom/it8212.c A payloads/cbflashrom/flashrom/it87spi.c A payloads/cbflashrom/flashrom/jedec.c A payloads/cbflashrom/flashrom/jlink_spi.c A payloads/cbflashrom/flashrom/known_boards.c A payloads/cbflashrom/flashrom/layout.c A payloads/cbflashrom/flashrom/libflashrom.c A payloads/cbflashrom/flashrom/libflashrom.map A payloads/cbflashrom/flashrom/mcp6x_spi.c A payloads/cbflashrom/flashrom/meson.build A payloads/cbflashrom/flashrom/meson_options.txt A payloads/cbflashrom/flashrom/mstarddc_spi.c A payloads/cbflashrom/flashrom/nic3com.c A payloads/cbflashrom/flashrom/nicintel.c A payloads/cbflashrom/flashrom/nicintel_eeprom.c A payloads/cbflashrom/flashrom/nicintel_spi.c A payloads/cbflashrom/flashrom/nicnatsemi.c A payloads/cbflashrom/flashrom/nicrealtek.c A payloads/cbflashrom/flashrom/ogp_spi.c A payloads/cbflashrom/flashrom/opaque.c A payloads/cbflashrom/flashrom/parade_lspcon.c A payloads/cbflashrom/flashrom/parallel.c A payloads/cbflashrom/flashrom/pcidev.c A payloads/cbflashrom/flashrom/pickit2_spi.c A payloads/cbflashrom/flashrom/platform/endian_big.c A payloads/cbflashrom/flashrom/platform/endian_little.c A payloads/cbflashrom/flashrom/platform/memaccess.c A payloads/cbflashrom/flashrom/platform/meson.build A payloads/cbflashrom/flashrom/pony_spi.c A payloads/cbflashrom/flashrom/processor_enable.c A payloads/cbflashrom/flashrom/programmer.c A payloads/cbflashrom/flashrom/programmer_table.c A payloads/cbflashrom/flashrom/raiden_debug_spi.c A payloads/cbflashrom/flashrom/rayer_spi.c A payloads/cbflashrom/flashrom/realtek_mst_i2c_spi.c A payloads/cbflashrom/flashrom/s25f.c A payloads/cbflashrom/flashrom/satamv.c A payloads/cbflashrom/flashrom/satasii.c A payloads/cbflashrom/flashrom/sb600spi.c A payloads/cbflashrom/flashrom/serprog.c A payloads/cbflashrom/flashrom/sfdp.c A payloads/cbflashrom/flashrom/spi.c A payloads/cbflashrom/flashrom/spi25.c A payloads/cbflashrom/flashrom/spi25_statusreg.c A payloads/cbflashrom/flashrom/spi95.c A payloads/cbflashrom/flashrom/sst28sf040.c A payloads/cbflashrom/flashrom/sst49lfxxxc.c A payloads/cbflashrom/flashrom/sst_fwhub.c A payloads/cbflashrom/flashrom/stlinkv3_spi.c A payloads/cbflashrom/flashrom/stm50.c A payloads/cbflashrom/flashrom/test_build.sh A payloads/cbflashrom/flashrom/udelay.c A payloads/cbflashrom/flashrom/usb_device.c A payloads/cbflashrom/flashrom/usbblaster_spi.c A payloads/cbflashrom/flashrom/usbdev.c A payloads/cbflashrom/flashrom/w29ee011.c A payloads/cbflashrom/flashrom/w39.c A payloads/cbflashrom/flashrom/wbsio_spi.c A payloads/cbflashrom/flashrom/writeprotect.c A payloads/cbflashrom/flashrom/writeprotect_ranges.c A payloads/cbflashrom/fsys/usbstorage.c A payloads/cbflashrom/fsys/usbstorage.h A payloads/cbflashrom/gfx/gfx.c A payloads/cbflashrom/gfx/gfx.h A payloads/cbflashrom/gfx/splash.c A payloads/cbflashrom/gfx/splash.h A payloads/cbflashrom/lang/en.c A payloads/cbflashrom/lang/lang.c A payloads/cbflashrom/lang/lang.h A payloads/cbflashrom/libftdi/LICENSE A payloads/cbflashrom/libftdi/src/ftdi.c A payloads/cbflashrom/libftdi/src/ftdi.h A payloads/cbflashrom/libftdi/src/ftdi_i.h A payloads/cbflashrom/libftdi/src/ftdi_stream.c A payloads/cbflashrom/libjaylink/buffer.c A payloads/cbflashrom/libjaylink/core.c A payloads/cbflashrom/libjaylink/device.c A payloads/cbflashrom/libjaylink/discovery.c A payloads/cbflashrom/libjaylink/discovery_usb.c A payloads/cbflashrom/libjaylink/emucom.c A payloads/cbflashrom/libjaylink/error.c A payloads/cbflashrom/libjaylink/fileio.c A payloads/cbflashrom/libjaylink/jtag.c A payloads/cbflashrom/libjaylink/libjaylink-internal.h A payloads/cbflashrom/libjaylink/libjaylink.h A payloads/cbflashrom/libjaylink/list.c A payloads/cbflashrom/libjaylink/log.c A payloads/cbflashrom/libjaylink/strutil.c A payloads/cbflashrom/libjaylink/swd.c A payloads/cbflashrom/libjaylink/swo.c A payloads/cbflashrom/libjaylink/target.c A payloads/cbflashrom/libjaylink/transport.c A payloads/cbflashrom/libjaylink/transport_usb.c A payloads/cbflashrom/libjaylink/util.c A payloads/cbflashrom/libusb/libusb.c A payloads/cbflashrom/libusb/libusb.h A payloads/cbflashrom/logo/cbui.png A payloads/cbflashrom/lp.config A payloads/cbflashrom/util/buffers.c A payloads/cbflashrom/util/buffers.h A payloads/cbflashrom/util/vector.c A payloads/cbflashrom/util/vector.h 200 files changed, 92,857 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/69328/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/69328 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib523ae9eb002f14749942137e53add4986098314 Gerrit-Change-Number: 69328 Gerrit-PatchSet: 3 Gerrit-Owner: Iman Bingi <imanbingy(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: oc/intel/common/block/sgx/Kconfig: Drop unused Kconfig symbol
by Elyes Haouas (Code Review) 08 Nov '22

08 Nov '22

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69332 ) Change subject: oc/intel/common/block/sgx/Kconfig: Drop unused Kconfig symbol ...................................................................... oc/intel/common/block/sgx/Kconfig: Drop unused Kconfig symbol Change-Id: Ib3af0a1c509ab2e2eccf3e36ff604a1040995af4 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/soc/intel/common/block/sgx/Kconfig 1 file changed, 10 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/69332/1 diff --git a/src/soc/intel/common/block/sgx/Kconfig b/src/soc/intel/common/block/sgx/Kconfig index 92959ff..0dee10e 100644 --- a/src/soc/intel/common/block/sgx/Kconfig +++ b/src/soc/intel/common/block/sgx/Kconfig @@ -56,9 +56,6 @@ config SOC_INTEL_COMMON_BLOCK_SGX_PRMRR_SIZE_64MB bool "64 MiB" -config SOC_INTEL_COMMON_BLOCK_SGX_PRMRR_SIZE_32MB - bool "32 MiB" - endchoice endif -- To view, visit https://review.coreboot.org/c/coreboot/+/69332 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib3af0a1c509ab2e2eccf3e36ff604a1040995af4 Gerrit-Change-Number: 69332 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/intel/common/block/smbus/Kconfig: Drop unused Kconfig symbol
by Elyes Haouas (Code Review) 08 Nov '22

08 Nov '22

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69331 ) Change subject: soc/intel/common/block/smbus/Kconfig: Drop unused Kconfig symbol ...................................................................... soc/intel/common/block/smbus/Kconfig: Drop unused Kconfig symbol Change-Id: Ic46e1663609068439069f666beca17ed76c679f0 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/soc/intel/common/block/smbus/Kconfig 1 file changed, 10 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/69331/1 diff --git a/src/soc/intel/common/block/smbus/Kconfig b/src/soc/intel/common/block/smbus/Kconfig index db95ca7..3b3eb2f 100644 --- a/src/soc/intel/common/block/smbus/Kconfig +++ b/src/soc/intel/common/block/smbus/Kconfig @@ -7,13 +7,6 @@ config FIXED_SMBUS_IO_BASE default 0xefa0 -config SOC_INTEL_COMMON_BLOCK_SMBUS_ACPI_DRIVER - bool - default n - depends on SOC_INTEL_COMMON_BLOCK_SMBUS - help - Intel Processor SMBus ACPI driver support - config SOC_INTEL_COMMON_BLOCK_TCO bool help -- To view, visit https://review.coreboot.org/c/coreboot/+/69331 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic46e1663609068439069f666beca17ed76c679f0 Gerrit-Change-Number: 69331 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: treewide: Drop unused Kconfig symbols
by Elyes Haouas (Code Review) 08 Nov '22

08 Nov '22

Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62362 ) Change subject: treewide: Drop unused Kconfig symbols ...................................................................... Patch Set 13: (1 comment) File src/mainboard/portwell/m107/Kconfig: https://review.coreboot.org/c/coreboot/+/62362/comment/8416523c_f0fd5887 PS11, Line 22: config ONBOARD_MEM_SAMSUNG > This config is used indirect. […] isn't default ONBOARD_MEM_MICRON ? please see line #20 and please run 'grep -r ONBOARD_MEM_SAMSUNG' -- To view, visit https://review.coreboot.org/c/coreboot/+/62362 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I96380d4567356c81e17de469fd78cec2fcb7e5c9 Gerrit-Change-Number: 62362 Gerrit-PatchSet: 13 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Comment-Date: Tue, 08 Nov 2022 14:17:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/meteorlake: Remove PM Energy Report WA
by Felix Held (Code Review) 08 Nov '22

08 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69042 ) Change subject: soc/intel/meteorlake: Remove PM Energy Report WA ...................................................................... soc/intel/meteorlake: Remove PM Energy Report WA Disable Pch PM Energy Report WA was added to enhance boot time with HFPGA only. SoC needs reporting enabled. BUG=None TEST=Build and Boot Google, Rex and Intel, MTLRVP without any boot time regression.. Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> Change-Id: If5f1f9c6ab31652977d436a49a3531edffbd60c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69042 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> --- M src/soc/intel/meteorlake/fsp_params.c 1 file changed, 20 insertions(+), 8 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, but someone else must approve Sridhar Siricilla: Looks good to me, approved diff --git a/src/soc/intel/meteorlake/fsp_params.c b/src/soc/intel/meteorlake/fsp_params.c index 4fd8f79..4fe2f63 100644 --- a/src/soc/intel/meteorlake/fsp_params.c +++ b/src/soc/intel/meteorlake/fsp_params.c @@ -375,14 +375,6 @@ s_cfg->PsOnEnable = 1; /* Enable the energy efficient turbo mode */ s_cfg->EnergyEfficientTurbo = 1; - - /* - * UPDATEME: This is WA for HFPGA - * Disable Pch Pm Energy Report - * Energy Report is disabled to enhance boottime with HFPGA. - */ - s_cfg->PchPmDisableEnergyReport = 1; - s_cfg->PmcLpmS0ixSubStateEnableMask = get_supported_lpm_mask(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/69042 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If5f1f9c6ab31652977d436a49a3531edffbd60c5 Gerrit-Change-Number: 69042 Gerrit-PatchSet: 5 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/google/brask: Disable PCH USB2 phy power gating for brask
by Felix Held (Code Review) 08 Nov '22

08 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69272 ) Change subject: mb/google/brask: Disable PCH USB2 phy power gating for brask ...................................................................... mb/google/brask: Disable PCH USB2 phy power gating for brask The patch disables PCH USB2 Phy power gating to prevent possible display flicker issue for moli board. Please refer Intel doc#723158 for more information. BUG=b:257415959 TEST=Verify the build for brask board Change-Id: I518e90e9032e8f2186300b6b907cc9d84a1682e4 Signed-off-by: Ricky Chang <rickytlchang(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69272 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao(a)google.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb 1 file changed, 24 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Zhuohao Lee: Looks good to me, approved Subrata Banik: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb index 0d60a57..29fb5d0 100644 --- a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb @@ -1,4 +1,7 @@ chip soc/intel/alderlake + # As per Intel Advisory doc#723158, the change is required to prevent possible + # display flickering issue. + register "usb2_phy_sus_pg_disable" = "1" # GPE configuration register "pmc_gpe0_dw0" = "GPP_A" -- To view, visit https://review.coreboot.org/c/coreboot/+/69272 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I518e90e9032e8f2186300b6b907cc9d84a1682e4 Gerrit-Change-Number: 69272 Gerrit-PatchSet: 3 Gerrit-Owner: Ricky Chang <rickytlchang(a)google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel: Use `PWRMBASE` over static `Index 0` for PMC
by Felix Held (Code Review) 08 Nov '22

08 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69227 ) Change subject: soc/intel: Use `PWRMBASE` over static `Index 0` for PMC ...................................................................... soc/intel: Use `PWRMBASE` over static `Index 0` for PMC This patch replaces static index 0 for PMC read resources with PCI configuration offset 0x10 (PWRMBASE). TEST=Able to build and boot Google, Rex to OS. Without this change: [SPEW ] PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 0 With this change: [SPEW ] PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 10 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Iee2523876a8045e70effd5824afc327d1113038b Reviewed-on: https://review.coreboot.org/c/coreboot/+/69227 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/soc/intel/alderlake/pmc.c M src/soc/intel/cannonlake/pmc.c M src/soc/intel/elkhartlake/pmc.c M src/soc/intel/jasperlake/pmc.c M src/soc/intel/meteorlake/pmc.c M src/soc/intel/tigerlake/pmc.c 6 files changed, 38 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved diff --git a/src/soc/intel/alderlake/pmc.c b/src/soc/intel/alderlake/pmc.c index 87cc54a..c28ee2d 100644 --- a/src/soc/intel/alderlake/pmc.c +++ b/src/soc/intel/alderlake/pmc.c @@ -85,7 +85,8 @@ struct resource *res; /* Add the fixed MMIO resource */ - mmio_resource_kb(dev, 0, PCH_PWRM_BASE_ADDRESS / KiB, PCH_PWRM_BASE_SIZE / KiB); + mmio_resource_kb(dev, PWRMBASE, PCH_PWRM_BASE_ADDRESS / KiB, + PCH_PWRM_BASE_SIZE / KiB); /* Add the fixed I/O resource */ res = new_resource(dev, 1); diff --git a/src/soc/intel/cannonlake/pmc.c b/src/soc/intel/cannonlake/pmc.c index f0a32b93..b85a12a 100644 --- a/src/soc/intel/cannonlake/pmc.c +++ b/src/soc/intel/cannonlake/pmc.c @@ -74,7 +74,8 @@ struct resource *res; /* Add the fixed MMIO resource */ - mmio_resource_kb(dev, 0, PCH_PWRM_BASE_ADDRESS / KiB, PCH_PWRM_BASE_SIZE / KiB); + mmio_resource_kb(dev, PWRMBASE, PCH_PWRM_BASE_ADDRESS / KiB, + PCH_PWRM_BASE_SIZE / KiB); /* Add the fixed I/O resource */ res = new_resource(dev, 1); diff --git a/src/soc/intel/elkhartlake/pmc.c b/src/soc/intel/elkhartlake/pmc.c index e556ac8..27d00d7 100644 --- a/src/soc/intel/elkhartlake/pmc.c +++ b/src/soc/intel/elkhartlake/pmc.c @@ -71,7 +71,8 @@ { struct resource *res; - mmio_resource_kb(dev, 0, PCH_PWRM_BASE_ADDRESS / KiB, PCH_PWRM_BASE_SIZE / KiB); + mmio_resource_kb(dev, PWRMBASE, PCH_PWRM_BASE_ADDRESS / KiB, + PCH_PWRM_BASE_SIZE / KiB); res = new_resource(dev, 1); res->base = (resource_t)ACPI_BASE_ADDRESS; diff --git a/src/soc/intel/jasperlake/pmc.c b/src/soc/intel/jasperlake/pmc.c index 4a48345..8f79f0c 100644 --- a/src/soc/intel/jasperlake/pmc.c +++ b/src/soc/intel/jasperlake/pmc.c @@ -71,7 +71,8 @@ { struct resource *res; - mmio_resource_kb(dev, 0, PCH_PWRM_BASE_ADDRESS / KiB, PCH_PWRM_BASE_SIZE / KiB); + mmio_resource_kb(dev, PWRMBASE, PCH_PWRM_BASE_ADDRESS / KiB, + PCH_PWRM_BASE_SIZE / KiB); res = new_resource(dev, 1); res->base = (resource_t)ACPI_BASE_ADDRESS; diff --git a/src/soc/intel/meteorlake/pmc.c b/src/soc/intel/meteorlake/pmc.c index 0ab15c4..dbfc4be 100644 --- a/src/soc/intel/meteorlake/pmc.c +++ b/src/soc/intel/meteorlake/pmc.c @@ -80,7 +80,8 @@ struct resource *res; /* Add the fixed MMIO resource */ - mmio_resource_kb(dev, 0, PCH_PWRM_BASE_ADDRESS / KiB, PCH_PWRM_BASE_SIZE / KiB); + mmio_resource_kb(dev, PWRMBASE, PCH_PWRM_BASE_ADDRESS / KiB, + PCH_PWRM_BASE_SIZE / KiB); /* Add the fixed I/O resource */ res = new_resource(dev, 1); diff --git a/src/soc/intel/tigerlake/pmc.c b/src/soc/intel/tigerlake/pmc.c index 31a9cc4..5ad8a89 100644 --- a/src/soc/intel/tigerlake/pmc.c +++ b/src/soc/intel/tigerlake/pmc.c @@ -84,7 +84,8 @@ struct resource *res; /* Add the fixed MMIO resource */ - mmio_resource_kb(dev, 0, PCH_PWRM_BASE_ADDRESS / KiB, PCH_PWRM_BASE_SIZE / KiB); + mmio_resource_kb(dev, PWRMBASE, PCH_PWRM_BASE_ADDRESS / KiB, + PCH_PWRM_BASE_SIZE / KiB); /* Add the fixed I/O resource */ res = new_resource(dev, 1); -- To view, visit https://review.coreboot.org/c/coreboot/+/69227 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iee2523876a8045e70effd5824afc327d1113038b Gerrit-Change-Number: 69227 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/google/nissa/var/craask: Add ambient thermal sensor settings
by Felix Held (Code Review) 08 Nov '22

08 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69197 ) ( 5 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/nissa/var/craask: Add ambient thermal sensor settings ...................................................................... mb/google/nissa/var/craask: Add ambient thermal sensor settings BUG=b:239495499 TEST=emerge-nissa coreboot Signed-off-by: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Change-Id: I026a8b3e1a27bedc3e0082e15e80a74a2f8adfda Reviewed-on: https://review.coreboot.org/c/coreboot/+/69197 Reviewed-by: Reka Norman <rekanorman(a)chromium.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Vidya Gopalakrishnan <vidya.gopalakrishnan(a)intel.com> --- M src/mainboard/google/brya/variants/craask/overridetree.cb 1 file changed, 21 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Vidya Gopalakrishnan: Looks good to me, but someone else must approve Reka Norman: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/craask/overridetree.cb b/src/mainboard/google/brya/variants/craask/overridetree.cb index c77787f..ebf8c30 100644 --- a/src/mainboard/google/brya/variants/craask/overridetree.cb +++ b/src/mainboard/google/brya/variants/craask/overridetree.cb @@ -124,6 +124,7 @@ ## sensor information register "options.tsr[0].desc" = ""Memory"" register "options.tsr[1].desc" = ""Charger"" + register "options.tsr[2].desc" = ""Ambient"" # TODO: below values are initial reference values only ## Passive Policy @@ -131,6 +132,7 @@ [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000), [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 75, 5000), + [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 75, 5000), }" ## Critical Policy @@ -138,6 +140,7 @@ [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN), [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN), }" register "controls.power_limits" = "{ -- To view, visit https://review.coreboot.org/c/coreboot/+/69197 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I026a8b3e1a27bedc3e0082e15e80a74a2f8adfda Gerrit-Change-Number: 69197 Gerrit-PatchSet: 7 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Peter Ou <peter.ou(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Vidya Gopalakrishnan <vidya.gopalakrishnan(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Cathy Chen <cathy_chen(a)quanta.corp-partner.google.com> Gerrit-CC: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-CC: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: mb/google/brya/var/kano: Add mipi hi556 camera support
by Felix Held (Code Review) 08 Nov '22

08 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68890 ) Change subject: mb/google/brya/var/kano: Add mipi hi556 camera support ...................................................................... mb/google/brya/var/kano: Add mipi hi556 camera support This patch supports multiple camera modules based on FW_CONFIG. BUG=b:251235140 TEST=Test the changes with ov2740/hi556 camera. Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Change-Id: I34dbf67634ecd364c40c6e934217af3d8efe1689 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68890 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jim Lai <jim.lai(a)intel.com> Reviewed-by: Ricardo Ribalda <ribalda(a)google.com> Reviewed-by: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/variants/kano/overridetree.cb 1 file changed, 62 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Ren Kuo: Looks good to me, approved Jim Lai: Looks good to me, but someone else must approve Ricardo Ribalda: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/brya/variants/kano/overridetree.cb b/src/mainboard/google/brya/variants/kano/overridetree.cb index c28dd28..a1667eb 100644 --- a/src/mainboard/google/brya/variants/kano/overridetree.cb +++ b/src/mainboard/google/brya/variants/kano/overridetree.cb @@ -10,6 +10,7 @@ field UFC 4 5 option UFC_USB 0 option UFC_MIPI_OVTI2740 1 + option UFC_MIPI_HI556 2 end field STYLUS 6 option STYLUS_ABSENT 0 @@ -197,6 +198,7 @@ register "cio2_prt[0]" = "1" device generic 0 on probe UFC UFC_MIPI_OVTI2740 + probe UFC UFC_MIPI_HI556 end end end @@ -322,6 +324,45 @@ end end chip drivers/intel/mipi_camera + register "acpi_hid" = ""INT3537"" + register "acpi_uid" = "0" + register "acpi_name" = ""CAM0"" + register "chip_name" = ""Hi-556 Camera"" + register "device_type" = "INTEL_ACPI_CAMERA_SENSOR" + register "has_power_resource" = "1" + + register "ssdb.lanes_used" = "2" + register "ssdb.link_used" = "1" + register "num_freq_entries" = "1" + register "link_freq[0]" = "437 * MHz" # 437 MHz + register "remote_name" = ""IPU0"" + register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D3_COLD" + + #Controls + register "clk_panel.clks[0].clknum" = "IMGCLKOUT_3" + register "clk_panel.clks[0].freq" = "FREQ_19_2_MHZ" + + register "gpio_panel.gpio[0].gpio_num" = "GPP_C4" #power + register "gpio_panel.gpio[1].gpio_num" = "GPP_F20" #reset + + #_ON + register "on_seq.ops_cnt" = "4" + register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)" + register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 5)" + register "on_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 5)" + register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(1, 5)" + + #_OFF + register "off_seq.ops_cnt" = "3" + register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)" + register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(1, 0)" + register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" + + device i2c 20 on + probe UFC UFC_MIPI_HI556 + end + end + chip drivers/intel/mipi_camera register "acpi_hid" = "ACPI_DT_NAMESPACE_HID" register "acpi_uid" = "1" register "acpi_name" = ""NVM0"" @@ -336,6 +377,7 @@ device i2c 50 on probe UFC UFC_MIPI_OVTI2740 + probe UFC UFC_MIPI_HI556 end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/68890 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I34dbf67634ecd364c40c6e934217af3d8efe1689 Gerrit-Change-Number: 68890 Gerrit-PatchSet: 4 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Andy Yeh <andy.yeh(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jim Lai <jim.lai(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Ofer Fried <oferfried(a)google.com> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ricardo Ribalda <ribalda(a)google.com> Gerrit-Reviewer: Ricky Liang <jcliang(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Grace Kao <grace.kao(a)intel.com> Gerrit-CC: Ricardo Ribalda <ribalda(a)chromium.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/google/brya/var/kinox: Disable PCH USB2 phy power gating
by Felix Held (Code Review) 08 Nov '22

08 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69205 ) Change subject: mb/google/brya/var/kinox: Disable PCH USB2 phy power gating ...................................................................... mb/google/brya/var/kinox: Disable PCH USB2 phy power gating The patch disables PCH USB2 Phy power gating to prevent possible display flicker issue for kinox board. Please refer Intel doc#723158 for more information. BUG=b:257373738 TEST=Verify the build for kinox board Signed-off-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Change-Id: Ifcf4f89ea4c61ec4f9a31edba069d2111ca06010 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69205 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Ricky Chang <rickytlchang(a)google.com> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/variants/kinox/overridetree.cb 1 file changed, 26 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Ricky Chang: Looks good to me, but someone else must approve Subrata Banik: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/kinox/overridetree.cb b/src/mainboard/google/brya/variants/kinox/overridetree.cb index 8356320..01610c1 100644 --- a/src/mainboard/google/brya/variants/kinox/overridetree.cb +++ b/src/mainboard/google/brya/variants/kinox/overridetree.cb @@ -12,6 +12,10 @@ # GPE configuration register "pmc_gpe0_dw1" = "GPP_H" + # As per Intel Advisory doc#723158, the change is required to prevent possible + # display flickering issue. + register "usb2_phy_sus_pg_disable" = "1" + # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | -- To view, visit https://review.coreboot.org/c/coreboot/+/69205 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifcf4f89ea4c61ec4f9a31edba069d2111ca06010 Gerrit-Change-Number: 69205 Gerrit-PatchSet: 6 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Ricky Chang <rickytlchang(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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