coreboot-gerrit November 2022

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[L] Change in coreboot[master]: southbridge/amd: Unify smbus.{c,h} and make them common
by Elyes Haouas (Code Review) 08 Nov '22

08 Nov '22

Attention is currently required from: Michał Żygowski, Paul Menzel, Michał Kopeć. Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61890 ) Change subject: southbridge/amd: Unify smbus.{c,h} and make them common ...................................................................... Patch Set 4: (1 comment) File src/southbridge/amd/common/smbus.h: https://review.coreboot.org/c/coreboot/+/61890/comment/5ae25118_98d108a7 PS4, Line 27: #define AX_INDXC 0 > Some archaeology: Commit 63e62b03a8 (This code provides southbridge initialization for SB800 south b […] SB800 deleted -- To view, visit https://review.coreboot.org/c/coreboot/+/61890 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ef8e4168b470435b244844e41ddb7f564bddf65 Gerrit-Change-Number: 61890 Gerrit-PatchSet: 4 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Martin Roth <martin.roth(a)tinkermill.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Comment-Date: Tue, 08 Nov 2022 14:44:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[L] Change in coreboot[master]: southbridge/amd: Unify smbus.{c,h} and make them common
by Elyes Haouas (Code Review) 08 Nov '22

08 Nov '22

Attention is currently required from: Michał Żygowski, Michał Kopeć, Elyes Haouas. Hello build bot (Jenkins), Michał Żygowski, Michał Kopeć, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61890 to look at the new patch set (#5). Change subject: southbridge/amd: Unify smbus.{c,h} and make them common ...................................................................... southbridge/amd: Unify smbus.{c,h} and make them common Change-Id: I9ef8e4168b470435b244844e41ddb7f564bddf65 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/southbridge/amd/pi/hudson/Makefile.inc M src/southbridge/amd/pi/hudson/hudson.c M src/southbridge/amd/pi/hudson/sm.c D src/southbridge/amd/pi/hudson/smbus.c D src/southbridge/amd/pi/hudson/smbus.h 5 files changed, 14 insertions(+), 293 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/61890/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/61890 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ef8e4168b470435b244844e41ddb7f564bddf65 Gerrit-Change-Number: 61890 Gerrit-PatchSet: 5 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Martin Roth <martin.roth(a)tinkermill.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: util/superiotool/fintek.c: Fix F71808A hardware monitor readouts
by 9elements QA (Code Review) 08 Nov '22

08 Nov '22

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62060 ) Change subject: util/superiotool/fintek.c: Fix F71808A hardware monitor readouts ...................................................................... Patch Set 4: Automatic boot test returned (PASS/FAIL/TOTAL): 14 / 1 / 15 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/134710 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/134709 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/134708 FAIL: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/134707 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/134706 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/134705 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/134704 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/134703 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/134702 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/134701 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/134700 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/134699 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/134698 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/134697 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/134696 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/62060 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b2b98c62f9305c6f4885c2ce3b1444801dcb9d5 Gerrit-Change-Number: 62060 Gerrit-PatchSet: 4 Gerrit-Owner: Ravi Mistry Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Tue, 08 Nov 2022 14:43:41 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: /: Remove unused <inttypes.h>
by Felix Held (Code Review) 08 Nov '22

08 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69026 ) Change subject: /: Remove unused <inttypes.h> ...................................................................... /: Remove unused <inttypes.h> Change-Id: I16aa756039973e164c887ff5237bda69d042a235 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69026 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/qualcomm/common/qupv3_i2c.c M src/soc/ti/am335x/mmc.c M src/soc/ti/am335x/mmc.h 3 files changed, 13 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/soc/qualcomm/common/qupv3_i2c.c b/src/soc/qualcomm/common/qupv3_i2c.c index 8f0880e..91844e3 100644 --- a/src/soc/qualcomm/common/qupv3_i2c.c +++ b/src/soc/qualcomm/common/qupv3_i2c.c @@ -4,7 +4,6 @@ #include <console/console.h> #include <device/i2c_simple.h> #include <gpio.h> -#include <inttypes.h> #include <lib.h> #include <soc/clock.h> #include <soc/qcom_qup_se.h> diff --git a/src/soc/ti/am335x/mmc.c b/src/soc/ti/am335x/mmc.c index b65030e..577434c 100644 --- a/src/soc/ti/am335x/mmc.c +++ b/src/soc/ti/am335x/mmc.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <inttypes.h> #include <string.h> #include <console/console.h> #include <commonlib/sd_mmc_ctrlr.h> diff --git a/src/soc/ti/am335x/mmc.h b/src/soc/ti/am335x/mmc.h index 757795d..3293332 100644 --- a/src/soc/ti/am335x/mmc.h +++ b/src/soc/ti/am335x/mmc.h @@ -3,7 +3,6 @@ #ifndef AM335X_MMC_H #define AM335X_MMC_H -#include <inttypes.h> #include <commonlib/sd_mmc_ctrlr.h> #define MMCHS0_BASE 0x48060000 -- To view, visit https://review.coreboot.org/c/coreboot/+/69026 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I16aa756039973e164c887ff5237bda69d042a235 Gerrit-Change-Number: 69026 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: /: Remove unused <inttypes.h>
by Felix Held (Code Review) 08 Nov '22

08 Nov '22

Attention is currently required from: Elyes Haouas. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69026 ) Change subject: /: Remove unused <inttypes.h> ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69026 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I16aa756039973e164c887ff5237bda69d042a235 Gerrit-Change-Number: 69026 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Tue, 08 Nov 2022 14:42:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/ti/am335x/cbmem.c: Use MiB macro
by Felix Held (Code Review) 08 Nov '22

08 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61332 ) Change subject: soc/ti/am335x/cbmem.c: Use MiB macro ...................................................................... soc/ti/am335x/cbmem.c: Use MiB macro Use "* MiB" instead of "<< 20". Change-Id: Iab6592804961a34fae6dc8012bfbc70023421a49 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61332 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/ti/am335x/cbmem.c 1 file changed, 17 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/soc/ti/am335x/cbmem.c b/src/soc/ti/am335x/cbmem.c index 3765874..170695e 100644 --- a/src/soc/ti/am335x/cbmem.c +++ b/src/soc/ti/am335x/cbmem.c @@ -1,9 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <cbmem.h> +#include <commonlib/bsd/helpers.h> #include <symbols.h> void *cbmem_top_chipset(void) { - return _dram + (CONFIG_DRAM_SIZE_MB << 20); + return _dram + CONFIG_DRAM_SIZE_MB * MiB; } -- To view, visit https://review.coreboot.org/c/coreboot/+/61332 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab6592804961a34fae6dc8012bfbc70023421a49 Gerrit-Change-Number: 61332 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/ti/am335x/cbmem.c: Use MiB macro
by Felix Held (Code Review) 08 Nov '22

08 Nov '22

Attention is currently required from: Elyes Haouas. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61332 ) Change subject: soc/ti/am335x/cbmem.c: Use MiB macro ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/61332 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab6592804961a34fae6dc8012bfbc70023421a49 Gerrit-Change-Number: 61332 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Tue, 08 Nov 2022 14:39:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: cpu: Include <cpu/cpu.h> instead of <arch/cpu.h>
by Felix Held (Code Review) 08 Nov '22

08 Nov '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69037 ) Change subject: cpu: Include <cpu/cpu.h> instead of <arch/cpu.h> ...................................................................... cpu: Include <cpu/cpu.h> instead of <arch/cpu.h> Also sort includes. Change-Id: Ia4a3807e45777e2a596878fe09e3c80b1fd2704d Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69037 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> --- M src/cpu/amd/pi/00730F01/update_microcode.c M src/cpu/intel/common/common_init.c M src/cpu/intel/common/fsb.c M src/cpu/intel/common/hyperthreading.c M src/cpu/intel/haswell/acpi.c M src/cpu/intel/haswell/haswell.h M src/cpu/intel/hyperthreading/intel_sibling.c M src/cpu/intel/microcode/microcode.c M src/cpu/intel/model_2065x/acpi.c M src/cpu/intel/model_206ax/acpi.c M src/cpu/intel/model_206ax/bootblock.c M src/cpu/intel/model_206ax/model_206ax.h M src/cpu/intel/slot_1/l2_cache.c M src/cpu/intel/speedstep/acpi.c M src/cpu/intel/speedstep/speedstep.c M src/cpu/intel/turbo/turbo.c M src/cpu/x86/mtrr/xip_cache.c M src/cpu/x86/name/name.c M src/cpu/x86/pae/pgtbl.c M src/cpu/x86/tsc/delay_tsc.c 20 files changed, 58 insertions(+), 41 deletions(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved diff --git a/src/cpu/amd/pi/00730F01/update_microcode.c b/src/cpu/amd/pi/00730F01/update_microcode.c index 7c15f9b..694af3f 100644 --- a/src/cpu/amd/pi/00730F01/update_microcode.c +++ b/src/cpu/amd/pi/00730F01/update_microcode.c @@ -1,13 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <stdint.h> -#include <arch/cpu.h> -#include <cpu/amd/microcode.h> +#include <cbfs.h> #include <commonlib/helpers.h> #include <console/console.h> -#include <cpu/x86/msr.h> +#include <cpu/amd/microcode.h> #include <cpu/amd/msr.h> -#include <cbfs.h> +#include <cpu/cpu.h> +#include <cpu/x86/msr.h> +#include <stdint.h> /* * Values and header structure from: diff --git a/src/cpu/intel/common/common_init.c b/src/cpu/intel/common/common_init.c index 9da162d..b24f742 100644 --- a/src/cpu/intel/common/common_init.c +++ b/src/cpu/intel/common/common_init.c @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpigen.h> -#include <arch/cpu.h> #include <console/console.h> +#include <cpu/cpu.h> #include <cpu/intel/msr.h> #include <cpu/intel/turbo.h> #include <cpu/x86/msr.h> diff --git a/src/cpu/intel/common/fsb.c b/src/cpu/intel/common/fsb.c index 92f88cd..c535d5d 100644 --- a/src/cpu/intel/common/fsb.c +++ b/src/cpu/intel/common/fsb.c @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <arch/cpu.h> #include <commonlib/helpers.h> #include <console/console.h> +#include <cpu/cpu.h> #include <cpu/intel/fsb.h> #include <cpu/intel/speedstep.h> #include <cpu/x86/msr.h> diff --git a/src/cpu/intel/common/hyperthreading.c b/src/cpu/intel/common/hyperthreading.c index f9170b3..85c4477 100644 --- a/src/cpu/intel/common/hyperthreading.c +++ b/src/cpu/intel/common/hyperthreading.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <cpu/cpu.h> #include <cpu/intel/common/common.h> -#include <arch/cpu.h> #include <types.h> bool intel_ht_supported(void) diff --git a/src/cpu/intel/haswell/acpi.c b/src/cpu/intel/haswell/acpi.c index 5e5fa81..1f028c3 100644 --- a/src/cpu/intel/haswell/acpi.c +++ b/src/cpu/intel/haswell/acpi.c @@ -1,14 +1,15 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <types.h> -#include <console/console.h> #include <acpi/acpi.h> #include <acpi/acpigen.h> -#include <arch/cpu.h> -#include <cpu/x86/msr.h> +#include <console/console.h> +#include <cpu/cpu.h> #include <cpu/intel/speedstep.h> #include <cpu/intel/turbo.h> +#include <cpu/x86/msr.h> #include <device/device.h> +#include <types.h> + #include "haswell.h" #include "chip.h" diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index 133a129..5697d0f 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -3,7 +3,7 @@ #ifndef _CPU_INTEL_HASWELL_H #define _CPU_INTEL_HASWELL_H -#include <arch/cpu.h> +#include <cpu/cpu.h> #include <stdint.h> /* CPU types without stepping */ diff --git a/src/cpu/intel/hyperthreading/intel_sibling.c b/src/cpu/intel/hyperthreading/intel_sibling.c index 9fde031..773d8e2 100644 --- a/src/cpu/intel/hyperthreading/intel_sibling.c +++ b/src/cpu/intel/hyperthreading/intel_sibling.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <arch/cpu.h> #include <console/console.h> +#include <cpu/cpu.h> #include <cpu/intel/hyperthreading.h> #include <device/device.h> #include <option.h> diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c index ac9453f..6f6e2f1 100644 --- a/src/cpu/intel/microcode/microcode.c +++ b/src/cpu/intel/microcode/microcode.c @@ -2,9 +2,9 @@ /* Microcode update for Intel PIII and later CPUs */ -#include <arch/cpu.h> #include <cbfs.h> #include <console/console.h> +#include <cpu/cpu.h> #include <cpu/intel/microcode.h> #include <cpu/x86/msr.h> #include <smp/spinlock.h> diff --git a/src/cpu/intel/model_2065x/acpi.c b/src/cpu/intel/model_2065x/acpi.c index 9d11ef0..0409b8a 100644 --- a/src/cpu/intel/model_2065x/acpi.c +++ b/src/cpu/intel/model_2065x/acpi.c @@ -1,14 +1,15 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <types.h> -#include <console/console.h> #include <acpi/acpi.h> #include <acpi/acpigen.h> -#include <arch/cpu.h> -#include <cpu/x86/msr.h> +#include <console/console.h> +#include <cpu/cpu.h> #include <cpu/intel/speedstep.h> #include <cpu/intel/turbo.h> +#include <cpu/x86/msr.h> #include <device/device.h> +#include <types.h> + #include "model_2065x.h" #include "chip.h" diff --git a/src/cpu/intel/model_206ax/acpi.c b/src/cpu/intel/model_206ax/acpi.c index 08548c5..06913bc 100644 --- a/src/cpu/intel/model_206ax/acpi.c +++ b/src/cpu/intel/model_206ax/acpi.c @@ -1,12 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <console/console.h> #include <acpi/acpi.h> #include <acpi/acpigen.h> -#include <arch/cpu.h> -#include <cpu/x86/msr.h> +#include <console/console.h> +#include <cpu/cpu.h> #include <cpu/intel/speedstep.h> #include <cpu/intel/turbo.h> +#include <cpu/x86/msr.h> #include <device/device.h> #include <stdint.h> diff --git a/src/cpu/intel/model_206ax/bootblock.c b/src/cpu/intel/model_206ax/bootblock.c index 6d2e486..cfbe8aee 100644 --- a/src/cpu/intel/model_206ax/bootblock.c +++ b/src/cpu/intel/model_206ax/bootblock.c @@ -1,11 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <stdint.h> #include <arch/bootblock.h> -#include <arch/cpu.h> -#include <cpu/x86/msr.h> #include <arch/io.h> +#include <cpu/cpu.h> +#include <cpu/x86/msr.h> #include <halt.h> +#include <stdint.h> #include "model_206ax.h" diff --git a/src/cpu/intel/model_206ax/model_206ax.h b/src/cpu/intel/model_206ax/model_206ax.h index 04e4639..b145523 100644 --- a/src/cpu/intel/model_206ax/model_206ax.h +++ b/src/cpu/intel/model_206ax/model_206ax.h @@ -3,7 +3,7 @@ #ifndef _CPU_INTEL_MODEL_206AX_H #define _CPU_INTEL_MODEL_206AX_H -#include <arch/cpu.h> +#include <cpu/cpu.h> #include <stdint.h> /* SandyBridge CPU stepping */ diff --git a/src/cpu/intel/slot_1/l2_cache.c b/src/cpu/intel/slot_1/l2_cache.c index fa43366..e4f8e95 100644 --- a/src/cpu/intel/slot_1/l2_cache.c +++ b/src/cpu/intel/slot_1/l2_cache.c @@ -23,12 +23,12 @@ * Covington-core Celerons do not have L2 cache. */ -#include <stdint.h> -#include <arch/cpu.h> #include <console/console.h> +#include <cpu/cpu.h> #include <cpu/intel/l2_cache.h> #include <cpu/x86/cache.h> #include <cpu/x86/msr.h> +#include <stdint.h> /* Latency Tables */ struct latency_entry { diff --git a/src/cpu/intel/speedstep/acpi.c b/src/cpu/intel/speedstep/acpi.c index d997ee8..839fec4 100644 --- a/src/cpu/intel/speedstep/acpi.c +++ b/src/cpu/intel/speedstep/acpi.c @@ -1,13 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <types.h> -#include <console/console.h> #include <acpi/acpi.h> #include <acpi/acpigen.h> -#include <arch/cpu.h> +#include <console/console.h> +#include <cpu/cpu.h> #include <cpu/intel/fsb.h> #include <cpu/intel/speedstep.h> #include <device/device.h> +#include <types.h> static int determine_total_number_of_cores(void) { diff --git a/src/cpu/intel/speedstep/speedstep.c b/src/cpu/intel/speedstep/speedstep.c index 9235272..b1b300d 100644 --- a/src/cpu/intel/speedstep/speedstep.c +++ b/src/cpu/intel/speedstep/speedstep.c @@ -1,11 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <types.h> -#include <string.h> -#include <arch/cpu.h> -#include <cpu/x86/msr.h> #include <console/console.h> +#include <cpu/cpu.h> #include <cpu/intel/speedstep.h> +#include <cpu/x86/msr.h> +#include <string.h> +#include <types.h> /** * @brief Gather speedstep limits for current processor diff --git a/src/cpu/intel/turbo/turbo.c b/src/cpu/intel/turbo/turbo.c index 5d84745..0b3b782 100644 --- a/src/cpu/intel/turbo/turbo.c +++ b/src/cpu/intel/turbo/turbo.c @@ -1,9 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <console/console.h> +#include <cpu/cpu.h> #include <cpu/intel/turbo.h> #include <cpu/x86/msr.h> -#include <arch/cpu.h> #if CONFIG(CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED) static inline int get_global_turbo_state(void) diff --git a/src/cpu/x86/mtrr/xip_cache.c b/src/cpu/x86/mtrr/xip_cache.c index 6ed96af..dc3bf24 100644 --- a/src/cpu/x86/mtrr/xip_cache.c +++ b/src/cpu/x86/mtrr/xip_cache.c @@ -1,10 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <arch/cpu.h> -#include <program_loading.h> #include <commonlib/region.h> #include <console/console.h> +#include <cpu/cpu.h> #include <cpu/x86/mtrr.h> +#include <program_loading.h> /* For now this is a good lowest common denominator for the total CPU cache. TODO: fetch the total amount of cache from CPUID leaf2. */ diff --git a/src/cpu/x86/name/name.c b/src/cpu/x86/name/name.c index bf62aef..1b71e5d 100644 --- a/src/cpu/x86/name/name.c +++ b/src/cpu/x86/name/name.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <arch/cpu.h> +#include <cpu/cpu.h> #include <cpu/x86/name.h> #include <stdint.h> #include <string.h> diff --git a/src/cpu/x86/pae/pgtbl.c b/src/cpu/x86/pae/pgtbl.c index dceeb88..e16fa02 100644 --- a/src/cpu/x86/pae/pgtbl.c +++ b/src/cpu/x86/pae/pgtbl.c @@ -1,9 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <arch/cpu.h> #include <cbfs.h> #include <commonlib/helpers.h> #include <console/console.h> +#include <cpu/cpu.h> #include <cpu/x86/cr.h> #include <cpu/x86/msr.h> #include <cpu/x86/pae.h> diff --git a/src/cpu/x86/tsc/delay_tsc.c b/src/cpu/x86/tsc/delay_tsc.c index 978a6ee..4253b18 100644 --- a/src/cpu/x86/tsc/delay_tsc.c +++ b/src/cpu/x86/tsc/delay_tsc.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <arch/cpu.h> +#include <cpu/cpu.h> #include <cpu/x86/tsc.h> #include <delay.h> #include <stdint.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/69037 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia4a3807e45777e2a596878fe09e3c80b1fd2704d Gerrit-Change-Number: 69037 Gerrit-PatchSet: 4 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: sb/intel/common/spi: Fix building for 64bit
by build bot (Jenkins) (Code Review) 08 Nov '22

08 Nov '22

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69389 ) Change subject: sb/intel/common/spi: Fix building for 64bit ...................................................................... Patch Set 1: (1 comment) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-163001): https://review.coreboot.org/c/coreboot/+/69389/comment/e47fce5d_0958faf2 PS1, Line 8: Possible unwrapped commit description (prefer a maximum 72 chars per line) -- To view, visit https://review.coreboot.org/c/coreboot/+/69389 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7bcb6dbf286438115c854d618eaa2da21c81400d Gerrit-Change-Number: 69389 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 08 Nov 2022 14:35:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: cpu/x86/Kconfig.debug_cpu: Drop unused symbol
by Elyes Haouas (Code Review) 08 Nov '22

08 Nov '22

Attention is currently required from: Arthur Heymans. Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69362 ) Change subject: cpu/x86/Kconfig.debug_cpu: Drop unused symbol ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69362 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b611773e596bea4788b05a3f58485fb3e002402 Gerrit-Change-Number: 69362 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Tue, 08 Nov 2022 14:33:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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