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Change subject: cpu/x86/smm: Add PCI BAR store functionality
......................................................................
Patch Set 7:
(1 comment)
File src/include/cpu/x86/smm.h:
https://review.coreboot.org/c/coreboot/+/67931/comment/d0321da1_06e116e8
PS5, Line 225: smm_runtime
> I'm fine with either approach, but this way allows the SMM init code to call this function without h […]
Ack
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Change subject: soc/intel/common: add units to soc_power_limits_config elements
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Patch Set 1: Code-Review+1
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Hello Raul Rangel, Caveh Jalali, Boris Mittelberg,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/69391
to look at the new patch set (#2).
Change subject: google/chromeec: Add ACPI method for EC Panic
......................................................................
google/chromeec: Add ACPI method for EC Panic
Add an ACPI method to handle EC_HOST_EVENT_PANIC (bit 24) events.
EC panic is not covered by the standard (0-F) ACPI notify values.
Arbitrarily choosing B0 notify, which is in the 84-BF device specific
ACPI notify range.
This will be a no-op until the kernel driver is also updated to handle
this event.
BUG=b:258195448
BRANCH=None
TEST=Observe event with modified cros_ec_lpc driver
Change-Id: Iafa642c1c50f9a0083a8e618e1eabec9a7ce39b4
---
M src/ec/google/chromeec/acpi/ec.asl
1 file changed, 31 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/69391/2
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Change subject: cpu/intel/haswell: Move chip_ops to cpu cluster
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Patch Set 11: Code-Review+1
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Change subject: mb/*: Remove lapic from devicetree
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Patch Set 6: Code-Review+1
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Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61517 )
Change subject: [WIP]aopen/dxplplusu: Enable SMM_ASEG
......................................................................
Patch Set 3:
(1 comment)
File src/southbridge/intel/i82801dx/smihandler.c:
https://review.coreboot.org/c/coreboot/+/61517/comment/3d978f8f_832734e5
PS3, Line 35: reg16 = inw(pmbase + PM1_STS);
: /* set status bits are cleared by writing 1 to them */
: outw(reg16, pmbase
> maybe {read,write}_pmbaseXX (src/southbridge/intel/common/pmbase.c)
That can happen in follow-ups. It's not reasonable to expect code that was removed a yesterday to be fully reviewed and fixed up to get merged in the tree again.
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Change subject: google/chromeec: Add ACPI method for EC Panic
......................................................................
Patch Set 1:
(1 comment)
File src/ec/google/chromeec/acpi/ec.asl:
https://review.coreboot.org/c/coreboot/+/69391/comment/8b4a2678_d173781c
PS1, Line 415: 0xB0
Can you #define this value?
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