coreboot-gerrit November 2022

coreboot-gerrit@coreboot.org

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7286 discussions

[XL] Change in coreboot[master]: Revert "mb/aopen/dxplplusu: Remove board"
by Elyes Haouas (Code Review) 08 Nov '22

08 Nov '22

Attention is currently required from: Angel Pons, Kyösti Mälkki, Felix Held. Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69339 ) Change subject: Revert "mb/aopen/dxplplusu: Remove board" ...................................................................... Patch Set 4: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/69339 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia1cd02278240d1b5d006fb2a7730d3d86390f85b Gerrit-Change-Number: 69339 Gerrit-PatchSet: 4 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 08 Nov 2022 15:53:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: util/scripts: Add script to run abuild on specific SOCs
by Elyes Haouas (Code Review) 08 Nov '22

08 Nov '22

Attention is currently required from: Martin L Roth. Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68956 ) Change subject: util/scripts: Add script to run abuild on specific SOCs ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: Would you please add an option to enable CONFIG_IWYU ? maybe in a follow-up patch ? -- To view, visit https://review.coreboot.org/c/coreboot/+/68956 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifc71c28bf64a805f203a815a9468ff9fe882aad3 Gerrit-Change-Number: 68956 Gerrit-PatchSet: 2 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Comment-Date: Tue, 08 Nov 2022 15:43:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/alderlake: Don't send early EOP if ME is/should be disabled
by Sean Rhodes (Code Review) 08 Nov '22

08 Nov '22

Attention is currently required from: Tarun Tuli, SRIDHAR SIRICILLA, Subrata Banik, Tim Wawrzynczak, Angel Pons. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67760 ) Change subject: soc/intel/alderlake: Don't send early EOP if ME is/should be disabled ...................................................................... Patch Set 4: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/67760/comment/e80b74a3_4333a30a PS3, Line 8: : This option can cause issues when the Intel ME is disabled > have u seen this code? […] Done Patchset: PS3: > > @subrata Any feedback on this? Or could we merge PS:1 as to avoid problems in master? […] Done File src/soc/intel/alderlake/chip.c: https://review.coreboot.org/c/coreboot/+/67760/comment/68d65e80_b8fea42c PS1, Line 207: 0) > can we use the macro instead `0` to define the ME state? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/67760 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1cdb97474ba0f37bf61f22d72cd3cc840f817652 Gerrit-Change-Number: 67760 Gerrit-PatchSet: 4 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: SRIDHAR SIRICILLA Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: SRIDHAR SIRICILLA Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Comment-Date: Tue, 08 Nov 2022 15:39:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sean Rhodes <sean(a)starlabs.systems> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Tim Wawrzynczak <inforichland(a)gmail.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: util/scripts: Add script to run abuild on specific SOCs
by Elyes Haouas (Code Review) 08 Nov '22

08 Nov '22

Attention is currently required from: Martin L Roth. Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68956 ) Change subject: util/scripts: Add script to run abuild on specific SOCs ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68956 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifc71c28bf64a805f203a815a9468ff9fe882aad3 Gerrit-Change-Number: 68956 Gerrit-PatchSet: 2 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Comment-Date: Tue, 08 Nov 2022 15:36:17 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/intel/mtlrvp: Enable ACPI and add ACPI table
by 9elements QA (Code Review) 08 Nov '22

08 Nov '22

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/66100 ) Change subject: mb/intel/mtlrvp: Enable ACPI and add ACPI table ...................................................................... Patch Set 8: Automatic boot test returned (PASS/FAIL/TOTAL): 14 / 1 / 15 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/134740 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/134739 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/134738 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/134737 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/134736 FAIL: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/134735 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/134734 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/134733 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/134732 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/134731 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/134730 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/134729 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/134728 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/134727 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/134726 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/66100 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8264197fd0acdd7e19b9a36fb22822447b013202 Gerrit-Change-Number: 66100 Gerrit-PatchSet: 8 Gerrit-Owner: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Tue, 08 Nov 2022 15:30:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in coreboot[master]: southbridge/amd: Unify smbus.{c,h} and make them common
by Elyes Haouas (Code Review) 08 Nov '22

08 Nov '22

Attention is currently required from: Michał Żygowski, Paul Menzel, Michał Kopeć. Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61890 ) Change subject: southbridge/amd: Unify smbus.{c,h} and make them common ...................................................................... Patch Set 6: (1 comment) Patchset: PS4: > `soc/amd` created a new file `alink. […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/61890 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ef8e4168b470435b244844e41ddb7f564bddf65 Gerrit-Change-Number: 61890 Gerrit-PatchSet: 6 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Martin Roth <martin.roth(a)tinkermill.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Comment-Date: Tue, 08 Nov 2022 15:29:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/amd: Move "smu.c" to common
by Elyes Haouas (Code Review) 08 Nov '22

08 Nov '22

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69338 ) Change subject: soc/amd: Move "smu.c" to common ...................................................................... soc/amd: Move "smu.c" to common Change-Id: I1bfa797e3460adddeefa916bb68e22beddaf6373 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/soc/amd/cezanne/Makefile.inc D src/soc/amd/cezanne/smu.c R src/soc/amd/common/smu.c M src/soc/amd/glinda/Makefile.inc D src/soc/amd/glinda/smu.c M src/soc/amd/mendocino/Makefile.inc D src/soc/amd/mendocino/smu.c M src/soc/amd/morgana/Makefile.inc D src/soc/amd/morgana/smu.c M src/soc/amd/picasso/Makefile.inc 10 files changed, 15 insertions(+), 77 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/69338/1 diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc index bc2df40..dcbe663 100644 --- a/src/soc/amd/cezanne/Makefile.inc +++ b/src/soc/amd/cezanne/Makefile.inc @@ -45,7 +45,7 @@ smm-y += gpio.c smm-y += smihandler.c -smm-y += smu.c +smm-y += ../common/smu.c smm-$(CONFIG_DEBUG_SMI) += uart.c CPPFLAGS_common += -I$(src)/soc/amd/cezanne/include diff --git a/src/soc/amd/cezanne/smu.c b/src/soc/amd/cezanne/smu.c deleted file mode 100644 index 1496957..0000000 --- a/src/soc/amd/cezanne/smu.c +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <console/console.h> -#include <amdblocks/smu.h> -#include <soc/smu.h> - -/* - * Request the SMU to put system into S3, S4, or S5. On entry, SlpTyp determines S-State and - * SlpTypeEn gets set by the SMU. Function does not return if successful. - */ -void smu_sx_entry(void) -{ - struct smu_payload msg = { 0 }; /* Unused for SMC_MSG_S3ENTRY */ - - printk(BIOS_DEBUG, "SMU: Put system into S3/S4/S5\n"); - send_smu_message(SMC_MSG_S3ENTRY, &msg); -} diff --git a/src/soc/amd/picasso/smu.c b/src/soc/amd/common/smu.c similarity index 100% rename from src/soc/amd/picasso/smu.c rename to src/soc/amd/common/smu.c diff --git a/src/soc/amd/glinda/Makefile.inc b/src/soc/amd/glinda/Makefile.inc index e03ed67..000f976 100644 --- a/src/soc/amd/glinda/Makefile.inc +++ b/src/soc/amd/glinda/Makefile.inc @@ -48,7 +48,7 @@ smm-y += gpio.c smm-y += smihandler.c -smm-y += smu.c +smm-y += ../common/smu.c smm-$(CONFIG_DEBUG_SMI) += uart.c CPPFLAGS_common += -I$(src)/soc/amd/glinda/include diff --git a/src/soc/amd/glinda/smu.c b/src/soc/amd/glinda/smu.c deleted file mode 100644 index d8cd081..0000000 --- a/src/soc/amd/glinda/smu.c +++ /dev/null @@ -1,19 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <console/console.h> -#include <amdblocks/smu.h> -#include <soc/smu.h> - -/* TODO: can this be made common? */ - -/* - * Request the SMU to put system into S3, S4, or S5. On entry, SlpTyp determines S-State and - * SlpTypeEn gets set by the SMU. Function does not return if successful. - */ -void smu_sx_entry(void) -{ - struct smu_payload msg = { 0 }; /* Unused for SMC_MSG_S3ENTRY */ - - printk(BIOS_DEBUG, "SMU: Put system into S3/S4/S5\n"); - send_smu_message(SMC_MSG_S3ENTRY, &msg); -} diff --git a/src/soc/amd/mendocino/Makefile.inc b/src/soc/amd/mendocino/Makefile.inc index c3f7278..c685b4a 100644 --- a/src/soc/amd/mendocino/Makefile.inc +++ b/src/soc/amd/mendocino/Makefile.inc @@ -47,7 +47,7 @@ smm-y += gpio.c smm-y += smihandler.c -smm-y += smu.c +smm-y += ../common/smu.c smm-$(CONFIG_DEBUG_SMI) += uart.c CPPFLAGS_common += -I$(src)/soc/amd/mendocino/include diff --git a/src/soc/amd/mendocino/smu.c b/src/soc/amd/mendocino/smu.c deleted file mode 100644 index 1496957..0000000 --- a/src/soc/amd/mendocino/smu.c +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <console/console.h> -#include <amdblocks/smu.h> -#include <soc/smu.h> - -/* - * Request the SMU to put system into S3, S4, or S5. On entry, SlpTyp determines S-State and - * SlpTypeEn gets set by the SMU. Function does not return if successful. - */ -void smu_sx_entry(void) -{ - struct smu_payload msg = { 0 }; /* Unused for SMC_MSG_S3ENTRY */ - - printk(BIOS_DEBUG, "SMU: Put system into S3/S4/S5\n"); - send_smu_message(SMC_MSG_S3ENTRY, &msg); -} diff --git a/src/soc/amd/morgana/Makefile.inc b/src/soc/amd/morgana/Makefile.inc index 036e458..38b1a8a 100644 --- a/src/soc/amd/morgana/Makefile.inc +++ b/src/soc/amd/morgana/Makefile.inc @@ -48,7 +48,7 @@ smm-y += gpio.c smm-y += smihandler.c -smm-y += smu.c +smm-y += ../common/smu.c smm-$(CONFIG_DEBUG_SMI) += uart.c CPPFLAGS_common += -I$(src)/soc/amd/morgana/include diff --git a/src/soc/amd/morgana/smu.c b/src/soc/amd/morgana/smu.c deleted file mode 100644 index d8cd081..0000000 --- a/src/soc/amd/morgana/smu.c +++ /dev/null @@ -1,19 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <console/console.h> -#include <amdblocks/smu.h> -#include <soc/smu.h> - -/* TODO: can this be made common? */ - -/* - * Request the SMU to put system into S3, S4, or S5. On entry, SlpTyp determines S-State and - * SlpTypeEn gets set by the SMU. Function does not return if successful. - */ -void smu_sx_entry(void) -{ - struct smu_payload msg = { 0 }; /* Unused for SMC_MSG_S3ENTRY */ - - printk(BIOS_DEBUG, "SMU: Put system into S3/S4/S5\n"); - send_smu_message(SMC_MSG_S3ENTRY, &msg); -} diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index fc3ee11..12b1710 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -50,7 +50,7 @@ smm-y += uart.c endif smm-y += gpio.c -smm-y += smu.c +smm-y += ../common/smu.c CPPFLAGS_common += -I$(src)/soc/amd/picasso/include CPPFLAGS_common += -I$(src)/soc/amd/picasso/acpi -- To view, visit https://review.coreboot.org/c/coreboot/+/69338 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1bfa797e3460adddeefa916bb68e22beddaf6373 Gerrit-Change-Number: 69338 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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[L] Change in coreboot[master]: mb/*: Remove lapic from devicetree
by Jonathon Hall (Code Review) 08 Nov '22

08 Nov '22

Attention is currently required from: Felix Singer, Frans Hendriks, Patrick Rudolph, Jonathan Zhang, Jeremy Soller, Angel Pons, Arthur Heymans, Michael Niewöhner, Piotr Król, Tim Crawford, Tarun Tuli, Nico Huber, Michał Żygowski, Maxim Polyakov, Johnny Lin, Christian Walter, Morgan Jang, Werner Zeh, Tim Chu. Jonathon Hall has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69303 ) Change subject: mb/*: Remove lapic from devicetree ...................................................................... Patch Set 6: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/69303 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5258a769c0f0ee4bbc4facc19737eed187b68c73 Gerrit-Change-Number: 69303 Gerrit-PatchSet: 6 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Tue, 08 Nov 2022 15:26:46 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XL] Change in coreboot[master]: payloads/cbflashrom: Add new payload CBFlashrom
by Iman Bingi (Code Review) 08 Nov '22

08 Nov '22

Iman Bingi has uploaded a new patch set (#4). ( https://review.coreboot.org/c/coreboot/+/69328 ) Change subject: payloads/cbflashrom: Add new payload CBFlashrom ...................................................................... payloads/cbflashrom: Add new payload CBFlashrom Flashrom with Graphical User Interface. Depends on libpayload and nuklear. Features: * Graphical menus with scrolling. * Text rendering engine (atm only bitmap font) * Support for keyboard and mouse * Support for USB and PS/2 devices * Support for FAT32 file system (USB drives) * Works as ELF payload * Works as Seabios secondary payload * Runs in qemu and on real hardware Shortcomings: * Doesn't work in VGA text mode * Untested TODO: * Test on as many hardware/platforms as possible Change-Id: Ib523ae9eb002f14749942137e53add4986098314 Signed-off-by: Ben Adu-Boahen <imanbingy(a)gmail.com> --- M payloads/Kconfig M payloads/Makefile.inc A payloads/cbflashrom/.gitignore A payloads/cbflashrom/Kconfig A payloads/cbflashrom/Makefile A payloads/cbflashrom/NuklearUI/NuklearCBFlashrom.c A payloads/cbflashrom/NuklearUI/NuklearCBFlashrom.h A payloads/cbflashrom/NuklearUI/NuklearCheckbox.c A payloads/cbflashrom/NuklearUI/NuklearCheckbox.h A payloads/cbflashrom/NuklearUI/NuklearCommon.h A payloads/cbflashrom/NuklearUI/NuklearDataGrid.c A payloads/cbflashrom/NuklearUI/NuklearDataGrid.h A payloads/cbflashrom/NuklearUI/NuklearFieldFile.c A payloads/cbflashrom/NuklearUI/NuklearFieldFile.h A payloads/cbflashrom/NuklearUI/NuklearFieldHex.c A payloads/cbflashrom/NuklearUI/NuklearFieldHex.h A payloads/cbflashrom/NuklearUI/NuklearFileChooser.c A payloads/cbflashrom/NuklearUI/NuklearFileChooser.h A payloads/cbflashrom/NuklearUI/NuklearHex.c A payloads/cbflashrom/NuklearUI/NuklearHex.h A payloads/cbflashrom/NuklearUI/NuklearInput.c A payloads/cbflashrom/NuklearUI/NuklearInput.h A payloads/cbflashrom/NuklearUI/NuklearObject.c A payloads/cbflashrom/NuklearUI/NuklearObject.h A payloads/cbflashrom/NuklearUI/NuklearStyle.c A payloads/cbflashrom/NuklearUI/NuklearStyle.h A payloads/cbflashrom/NuklearUI/NuklearUI.h A payloads/cbflashrom/arch/x86/cpuid.c A payloads/cbflashrom/arch/x86/cpuid.h A payloads/cbflashrom/arch/x86/memcpy.c A payloads/cbflashrom/arch/x86/memcpy.h A payloads/cbflashrom/cbflashrom.c A payloads/cbflashrom/cbflashrom.h A payloads/cbflashrom/flashrom/82802ab.c A payloads/cbflashrom/flashrom/COPYING A payloads/cbflashrom/flashrom/Doxyfile A payloads/cbflashrom/flashrom/MAINTAINERS A payloads/cbflashrom/flashrom/Makefile A payloads/cbflashrom/flashrom/Makefile.include A payloads/cbflashrom/flashrom/README A payloads/cbflashrom/flashrom/amd_imc.c A payloads/cbflashrom/flashrom/at45db.c A payloads/cbflashrom/flashrom/atahpt.c A payloads/cbflashrom/flashrom/atavia.c A payloads/cbflashrom/flashrom/bitbang_spi.c A payloads/cbflashrom/flashrom/board_enable.c A payloads/cbflashrom/flashrom/buspirate_spi.c A payloads/cbflashrom/flashrom/cbtable.c A payloads/cbflashrom/flashrom/ch341a_spi.c A payloads/cbflashrom/flashrom/chipset_enable.c A payloads/cbflashrom/flashrom/cli_common.c A payloads/cbflashrom/flashrom/cli_output.c A payloads/cbflashrom/flashrom/custom_baud.c A payloads/cbflashrom/flashrom/dediprog.c A payloads/cbflashrom/flashrom/developerbox_spi.c A payloads/cbflashrom/flashrom/digilent_spi.c A payloads/cbflashrom/flashrom/dirtyjtag_spi.c A payloads/cbflashrom/flashrom/dmi.c A payloads/cbflashrom/flashrom/drkaiser.c A payloads/cbflashrom/flashrom/edi.c A payloads/cbflashrom/flashrom/en29lv640b.c A payloads/cbflashrom/flashrom/flashchips.c A payloads/cbflashrom/flashrom/flashrom.8.tmpl A payloads/cbflashrom/flashrom/flashrom.c A payloads/cbflashrom/flashrom/fmap.c A payloads/cbflashrom/flashrom/ft2232_spi.c A payloads/cbflashrom/flashrom/gfxnvidia.c A payloads/cbflashrom/flashrom/helpers.c A payloads/cbflashrom/flashrom/helpers_fileio.c A payloads/cbflashrom/flashrom/hwaccess_physmap.c A payloads/cbflashrom/flashrom/hwaccess_x86_io.c A payloads/cbflashrom/flashrom/hwaccess_x86_msr.c A payloads/cbflashrom/flashrom/ich_descriptors.c A payloads/cbflashrom/flashrom/ichspi.c A payloads/cbflashrom/flashrom/include/chipdrivers.h A payloads/cbflashrom/flashrom/include/coreboot_tables.h A payloads/cbflashrom/flashrom/include/custom_baud.h A payloads/cbflashrom/flashrom/include/edi.h A payloads/cbflashrom/flashrom/include/ene.h A payloads/cbflashrom/flashrom/include/flash.h A payloads/cbflashrom/flashrom/include/flashchips.h A payloads/cbflashrom/flashrom/include/fmap.h A payloads/cbflashrom/flashrom/include/hwaccess_physmap.h A payloads/cbflashrom/flashrom/include/hwaccess_x86_io.h A payloads/cbflashrom/flashrom/include/hwaccess_x86_msr.h A payloads/cbflashrom/flashrom/include/i2c_helper.h A payloads/cbflashrom/flashrom/include/ich_descriptors.h A payloads/cbflashrom/flashrom/include/layout.h A payloads/cbflashrom/flashrom/include/libflashrom.h A payloads/cbflashrom/flashrom/include/platform.h A payloads/cbflashrom/flashrom/include/platform/pci.h A payloads/cbflashrom/flashrom/include/platform/swap.h A payloads/cbflashrom/flashrom/include/programmer.h A payloads/cbflashrom/flashrom/include/spi.h A payloads/cbflashrom/flashrom/include/usb_device.h A payloads/cbflashrom/flashrom/include/writeprotect.h A payloads/cbflashrom/flashrom/internal.c A payloads/cbflashrom/flashrom/internal.h A payloads/cbflashrom/flashrom/it8212.c A payloads/cbflashrom/flashrom/it87spi.c A payloads/cbflashrom/flashrom/jedec.c A payloads/cbflashrom/flashrom/jlink_spi.c A payloads/cbflashrom/flashrom/known_boards.c A payloads/cbflashrom/flashrom/layout.c A payloads/cbflashrom/flashrom/libflashrom.c A payloads/cbflashrom/flashrom/libflashrom.map A payloads/cbflashrom/flashrom/mcp6x_spi.c A payloads/cbflashrom/flashrom/meson.build A payloads/cbflashrom/flashrom/meson_options.txt A payloads/cbflashrom/flashrom/mstarddc_spi.c A payloads/cbflashrom/flashrom/nic3com.c A payloads/cbflashrom/flashrom/nicintel.c A payloads/cbflashrom/flashrom/nicintel_eeprom.c A payloads/cbflashrom/flashrom/nicintel_spi.c A payloads/cbflashrom/flashrom/nicnatsemi.c A payloads/cbflashrom/flashrom/nicrealtek.c A payloads/cbflashrom/flashrom/ogp_spi.c A payloads/cbflashrom/flashrom/opaque.c A payloads/cbflashrom/flashrom/parade_lspcon.c A payloads/cbflashrom/flashrom/parallel.c A payloads/cbflashrom/flashrom/pcidev.c A payloads/cbflashrom/flashrom/pickit2_spi.c A payloads/cbflashrom/flashrom/platform/endian_big.c A payloads/cbflashrom/flashrom/platform/endian_little.c A payloads/cbflashrom/flashrom/platform/memaccess.c A payloads/cbflashrom/flashrom/platform/meson.build A payloads/cbflashrom/flashrom/pony_spi.c A payloads/cbflashrom/flashrom/processor_enable.c A payloads/cbflashrom/flashrom/programmer.c A payloads/cbflashrom/flashrom/programmer_table.c A payloads/cbflashrom/flashrom/raiden_debug_spi.c A payloads/cbflashrom/flashrom/rayer_spi.c A payloads/cbflashrom/flashrom/realtek_mst_i2c_spi.c A payloads/cbflashrom/flashrom/s25f.c A payloads/cbflashrom/flashrom/satamv.c A payloads/cbflashrom/flashrom/satasii.c A payloads/cbflashrom/flashrom/sb600spi.c A payloads/cbflashrom/flashrom/serprog.c A payloads/cbflashrom/flashrom/sfdp.c A payloads/cbflashrom/flashrom/spi.c A payloads/cbflashrom/flashrom/spi25.c A payloads/cbflashrom/flashrom/spi25_statusreg.c A payloads/cbflashrom/flashrom/spi95.c A payloads/cbflashrom/flashrom/sst28sf040.c A payloads/cbflashrom/flashrom/sst49lfxxxc.c A payloads/cbflashrom/flashrom/sst_fwhub.c A payloads/cbflashrom/flashrom/stlinkv3_spi.c A payloads/cbflashrom/flashrom/stm50.c A payloads/cbflashrom/flashrom/test_build.sh A payloads/cbflashrom/flashrom/udelay.c A payloads/cbflashrom/flashrom/usb_device.c A payloads/cbflashrom/flashrom/usbblaster_spi.c A payloads/cbflashrom/flashrom/usbdev.c A payloads/cbflashrom/flashrom/w29ee011.c A payloads/cbflashrom/flashrom/w39.c A payloads/cbflashrom/flashrom/wbsio_spi.c A payloads/cbflashrom/flashrom/writeprotect.c A payloads/cbflashrom/flashrom/writeprotect_ranges.c A payloads/cbflashrom/fsys/usbstorage.c A payloads/cbflashrom/fsys/usbstorage.h A payloads/cbflashrom/gfx/gfx.c A payloads/cbflashrom/gfx/gfx.h A payloads/cbflashrom/gfx/splash.c A payloads/cbflashrom/gfx/splash.h A payloads/cbflashrom/lang/en.c A payloads/cbflashrom/lang/lang.c A payloads/cbflashrom/lang/lang.h A payloads/cbflashrom/libftdi/LICENSE A payloads/cbflashrom/libftdi/src/ftdi.c A payloads/cbflashrom/libftdi/src/ftdi.h A payloads/cbflashrom/libftdi/src/ftdi_i.h A payloads/cbflashrom/libftdi/src/ftdi_stream.c A payloads/cbflashrom/libjaylink/buffer.c A payloads/cbflashrom/libjaylink/core.c A payloads/cbflashrom/libjaylink/device.c A payloads/cbflashrom/libjaylink/discovery.c A payloads/cbflashrom/libjaylink/discovery_usb.c A payloads/cbflashrom/libjaylink/emucom.c A payloads/cbflashrom/libjaylink/error.c A payloads/cbflashrom/libjaylink/fileio.c A payloads/cbflashrom/libjaylink/jtag.c A payloads/cbflashrom/libjaylink/libjaylink-internal.h A payloads/cbflashrom/libjaylink/libjaylink.h A payloads/cbflashrom/libjaylink/list.c A payloads/cbflashrom/libjaylink/log.c A payloads/cbflashrom/libjaylink/strutil.c A payloads/cbflashrom/libjaylink/swd.c A payloads/cbflashrom/libjaylink/swo.c A payloads/cbflashrom/libjaylink/target.c A payloads/cbflashrom/libjaylink/transport.c A payloads/cbflashrom/libjaylink/transport_usb.c A payloads/cbflashrom/libjaylink/util.c A payloads/cbflashrom/libusb/libusb.c A payloads/cbflashrom/libusb/libusb.h A payloads/cbflashrom/logo/cbui.png A payloads/cbflashrom/lp.config A payloads/cbflashrom/util/buffers.c A payloads/cbflashrom/util/buffers.h A payloads/cbflashrom/util/vector.c A payloads/cbflashrom/util/vector.h 200 files changed, 92,852 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/69328/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/69328 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib523ae9eb002f14749942137e53add4986098314 Gerrit-Change-Number: 69328 Gerrit-PatchSet: 4 Gerrit-Owner: Iman Bingi <imanbingy(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/intel/broadwell: Hook up PCI domain and CPU cluster ops to device...
by Jonathon Hall (Code Review) 08 Nov '22

08 Nov '22

Attention is currently required from: Arthur Heymans. Jonathon Hall has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69301 ) Change subject: soc/intel/broadwell: Hook up PCI domain and CPU cluster ops to devicetree ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/69301 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I77a333827552741453d8b575f2a8009b3e1bf8f1 Gerrit-Change-Number: 69301 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Tue, 08 Nov 2022 15:19:18 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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