coreboot-gerrit November 2022

coreboot-gerrit@coreboot.org

1 participants
7286 discussions

[S] Change in coreboot[master]: configs: Buildtest 64bit amd/picasso
by Arthur Heymans (Code Review) 12 Nov '22

12 Nov '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69508 ) Change subject: configs: Buildtest 64bit amd/picasso ...................................................................... configs: Buildtest 64bit amd/picasso Change-Id: Ia7b9925ab0a594a0ec26746cbe938f7cf2aa0118 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- A configs/config.google_vilboz.x86_64 1 file changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/69508/1 diff --git a/configs/config.google_vilboz.x86_64 b/configs/config.google_vilboz.x86_64 new file mode 100644 index 0000000..74036ae --- /dev/null +++ b/configs/config.google_vilboz.x86_64 @@ -0,0 +1,3 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_BOARD_GOOGLE_VILBOZ=y +CONFIG_USE_EXP_X86_64_SUPPORT=y -- To view, visit https://review.coreboot.org/c/coreboot/+/69508 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia7b9925ab0a594a0ec26746cbe938f7cf2aa0118 Gerrit-Change-Number: 69508 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[master]: soc/amd/psp_smm_gen2.c: Fix 64bit mode integer conversion
by Arthur Heymans (Code Review) 12 Nov '22

12 Nov '22

1 0

[S] Change in coreboot[master]: device/Kconfig: Don't allow native mode in x86_64
by Arthur Heymans (Code Review) 12 Nov '22

12 Nov '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69506 ) Change subject: device/Kconfig: Don't allow native mode in x86_64 ...................................................................... device/Kconfig: Don't allow native mode in x86_64 This option is not working so don't advertise it. Change-Id: I910162756a567289b2484a5445360a3197ae848c Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/device/Kconfig 1 file changed, 13 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/69506/1 diff --git a/src/device/Kconfig b/src/device/Kconfig index a41f261..34600ad 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -197,7 +197,7 @@ config PCI_OPTION_ROM_RUN_REALMODE prompt "Native mode" bool - depends on ARCH_X86 + depends on ARCH_X86 && !ARCH_RAMSTAGE_X86_64 help If you select this option, PCI Option ROMs will be executed natively on the CPU in real mode. No CPU emulation is involved, -- To view, visit https://review.coreboot.org/c/coreboot/+/69506 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I910162756a567289b2484a5445360a3197ae848c Gerrit-Change-Number: 69506 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

1 0

[M] Change in coreboot[master]: arch/x86/Kconfig: Move AMD stages arch to common code
by Arthur Heymans (Code Review) 12 Nov '22

12 Nov '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, Felix Held. Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69505 ) Change subject: arch/x86/Kconfig: Move AMD stages arch to common code ...................................................................... arch/x86/Kconfig: Move AMD stages arch to common code Use VBOOT_STARTS_BEFORE_BOOTBLOCK to determine whether the VERSTAGE needs to be build as x86 stage. Change-Id: I126801a1f6f523435935bb300f3e2807db347f63 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/Kconfig M src/soc/amd/cezanne/Kconfig M src/soc/amd/glinda/Kconfig M src/soc/amd/mendocino/Kconfig M src/soc/amd/morgana/Kconfig M src/soc/amd/picasso/Kconfig 6 files changed, 16 insertions(+), 42 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/69505/1 diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index b60f600..f7b9250 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -28,9 +28,9 @@ config ARCH_ALL_STAGES_X86_32 bool - default ARCH_ALL_STAGES_X86 && !ARCH_ALL_STAGES_X86_64 + default !ARCH_ALL_STAGES_X86_64 select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 + select ARCH_VERSTAGE_X86_32 if !VBOOT_STARTS_BEFORE_BOOTBLOCK select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 select ARCH_SUPPORTS_CLANG @@ -61,14 +61,10 @@ config ARCH_ALL_STAGES_X86_64 bool select ARCH_BOOTBLOCK_X86_64 - select ARCH_VERSTAGE_X86_64 + select ARCH_VERSTAGE_X86_64 if !VBOOT_STARTS_BEFORE_BOOTBLOCK select ARCH_ROMSTAGE_X86_64 select ARCH_RAMSTAGE_X86_64 -config ARCH_ALL_STAGES_X86 - bool - default y - config HAVE_EXP_X86_64_SUPPORT bool help diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 1630df2..30e3e73 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -10,10 +10,6 @@ config SOC_SPECIFIC_OPTIONS def_bool y select ACPI_SOC_NVS - select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 if !VBOOT_STARTS_BEFORE_BOOTBLOCK - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 select ARCH_X86 select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH select DRIVERS_USB_ACPI @@ -88,9 +84,6 @@ select X86_AMD_FIXED_MTRRS select X86_INIT_NEED_1_SIPI -config ARCH_ALL_STAGES_X86 - default n - config CHIPSET_DEVICETREE string default "soc/amd/cezanne/chipset.cb" diff --git a/src/soc/amd/glinda/Kconfig b/src/soc/amd/glinda/Kconfig index 6c09ac9..5bf1d5f 100644 --- a/src/soc/amd/glinda/Kconfig +++ b/src/soc/amd/glinda/Kconfig @@ -13,10 +13,6 @@ config SOC_SPECIFIC_OPTIONS def_bool y select ACPI_SOC_NVS - select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 if !VBOOT_STARTS_BEFORE_BOOTBLOCK - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 select ARCH_X86 select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH select DRIVERS_USB_ACPI @@ -93,9 +89,6 @@ select X86_AMD_FIXED_MTRRS select X86_INIT_NEED_1_SIPI -config ARCH_ALL_STAGES_X86 - default n - config CHIPSET_DEVICETREE string default "soc/amd/glinda/chipset.cb" diff --git a/src/soc/amd/mendocino/Kconfig b/src/soc/amd/mendocino/Kconfig index 9da6138..05c349f 100644 --- a/src/soc/amd/mendocino/Kconfig +++ b/src/soc/amd/mendocino/Kconfig @@ -23,10 +23,6 @@ config SOC_SPECIFIC_OPTIONS def_bool y select ACPI_SOC_NVS - select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 if !VBOOT_STARTS_BEFORE_BOOTBLOCK - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 select ARCH_X86 select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH select DRIVERS_USB_ACPI @@ -106,9 +102,6 @@ select X86_AMD_FIXED_MTRRS select X86_INIT_NEED_1_SIPI -config ARCH_ALL_STAGES_X86 - default n - config CHIPSET_DEVICETREE string default "soc/amd/mendocino/chipset_mendocino.cb" if SOC_AMD_MENDOCINO diff --git a/src/soc/amd/morgana/Kconfig b/src/soc/amd/morgana/Kconfig index 37d3613..23d296c 100644 --- a/src/soc/amd/morgana/Kconfig +++ b/src/soc/amd/morgana/Kconfig @@ -13,10 +13,6 @@ config SOC_SPECIFIC_OPTIONS def_bool y select ACPI_SOC_NVS - select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 if !VBOOT_STARTS_BEFORE_BOOTBLOCK - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 select ARCH_X86 select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH select DRIVERS_USB_ACPI @@ -93,9 +89,6 @@ select X86_AMD_FIXED_MTRRS select X86_INIT_NEED_1_SIPI -config ARCH_ALL_STAGES_X86 - default n - config CHIPSET_DEVICETREE string default "soc/amd/morgana/chipset.cb" diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index e852826..7f56803 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -11,10 +11,6 @@ def_bool y select ACPI_SOC_NVS select ADD_FSP_BINARIES if USE_AMD_BLOBS - select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 if !VBOOT_STARTS_BEFORE_BOOTBLOCK - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 select ARCH_X86 select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH select CONSOLE_CBMEM_PRINT_PRE_BOOTBLOCK_CONTENTS if VBOOT_STARTS_BEFORE_BOOTBLOCK @@ -80,9 +76,6 @@ select X86_AMD_FIXED_MTRRS select X86_INIT_NEED_1_SIPI -config ARCH_ALL_STAGES_X86 - default n - config CHIPSET_DEVICETREE string default "soc/amd/picasso/chipset.cb" -- To view, visit https://review.coreboot.org/c/coreboot/+/69505 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I126801a1f6f523435935bb300f3e2807db347f63 Gerrit-Change-Number: 69505 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[master]: soc/amd/picasso: Add support for 64bit builds
by Arthur Heymans (Code Review) 12 Nov '22

12 Nov '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Arthur Heymans, Fred Reitberger. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Fred Reitberger, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63727 to look at the new patch set (#8). Change subject: soc/amd/picasso: Add support for 64bit builds ...................................................................... soc/amd/picasso: Add support for 64bit builds Tested on google/vilboz (running the PCI rom with yabel). Change-Id: Icd72c4eef7805aacba6378632cbac7de9527673b Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/amd/common/block/cpu/noncar/pre_c.S M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/Makefile.inc 3 files changed, 28 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/63727/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/63727 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd72c4eef7805aacba6378632cbac7de9527673b Gerrit-Change-Number: 63727 Gerrit-PatchSet: 8 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newpatchset

1 0

[S] Change in coreboot[master]: soc/amd/picasso: add mb_pre_fspm() definition and weak implementation
by Matt DeVillier (Code Review) 12 Nov '22

12 Nov '22

Attention is currently required from: Jason Glenesk, Fred Reitberger, Felix Held. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69452 ) Change subject: soc/amd/picasso: add mb_pre_fspm() definition and weak implementation ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/69452/comment/8cdb5b1e_792ed8ee PS1, Line 10: ; will be moved in a : subsequent commit > Will it, though? CB:69454 is abandoned Done -- To view, visit https://review.coreboot.org/c/coreboot/+/69452 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia422aaa9e80355f9a9f8f850368441e5c8ff6598 Gerrit-Change-Number: 69452 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sat, 12 Nov 2022 16:56:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: soc/amd/picasso: add mb_pre_fspm() definition and weak implementation
by Matt DeVillier (Code Review) 12 Nov '22

12 Nov '22

Attention is currently required from: Jason Glenesk, Matt DeVillier, Fred Reitberger, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Jason Glenesk, Angel Pons, Martin Roth, Fred Reitberger, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69452 to look at the new patch set (#2). Change subject: soc/amd/picasso: add mb_pre_fspm() definition and weak implementation ...................................................................... soc/amd/picasso: add mb_pre_fspm() definition and weak implementation On newer AMD platforms, mb_pre_fspm() is used to set GPIOs in romstage for PCIe reset (currently set in bootblock) and touchscreen power sequencing (not yet implemented, but will be later in the patch train). Change-Id: Ia422aaa9e80355f9a9f8f850368441e5c8ff6598 Signed-off-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> --- M src/soc/amd/picasso/fsp_m_params.c M src/soc/amd/picasso/include/soc/platform_descriptors.h 2 files changed, 20 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/69452/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69452 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia422aaa9e80355f9a9f8f850368441e5c8ff6598 Gerrit-Change-Number: 69452 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

1 0

[S] Change in coreboot[master]: driver/intel/fsp2_0/hand_off_block: rework fsp_display_fvi_version_hob
by Felix Held (Code Review) 12 Nov '22

12 Nov '22

Attention is currently required from: Subrata Banik, Andrey Petrov. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69499 ) Change subject: driver/intel/fsp2_0/hand_off_block: rework fsp_display_fvi_version_hob ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/69499/comment/c6f857b1_706458ce PS1, Line 12: just noticed that the part of the commit message that should have said that this slightly changes behavior that it will only process one HOB somehow got lost when i split the change into multiple patches. i'm not 100% sure if there can be more than one of those HOBs; if there can be more than one, i'd need to rework this patch -- To view, visit https://review.coreboot.org/c/coreboot/+/69499 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3398043dbdb3fc618277cefdd349b2c935bbfa52 Gerrit-Change-Number: 69499 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Comment-Date: Sat, 12 Nov 2022 15:59:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: cpu/cpu.h: Change the function signature
by Arthur Heymans (Code Review) 12 Nov '22

12 Nov '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69504 ) Change subject: cpu/cpu.h: Change the function signature ...................................................................... cpu/cpu.h: Change the function signature There is no need to pass the CPU index around. Change-Id: Iad8e3cb318e6520ac5877118dbf43597dedb75b9 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/cpu.c M src/cpu/x86/mp_init.c M src/include/cpu/cpu.h 3 files changed, 17 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/69504/1 diff --git a/src/arch/x86/cpu.c b/src/arch/x86/cpu.c index f4cb83a..ed1c15c 100644 --- a/src/arch/x86/cpu.c +++ b/src/arch/x86/cpu.c @@ -228,7 +228,7 @@ return cpus_default_apic_id[logical_cpu]; } -void cpu_initialize(unsigned int index) +void cpu_initialize(void) { /* Because we busy wait at the printk spinlock. * It is important to keep the number of printed messages @@ -241,7 +241,7 @@ info = cpu_info(); - printk(BIOS_INFO, "Initializing CPU #%d\n", index); + printk(BIOS_INFO, "Initializing CPU #%zd\n", info->index); cpu = info->cpu; if (!cpu) @@ -283,7 +283,7 @@ } post_log_clear(); - printk(BIOS_INFO, "CPU #%d initialized\n", index); + printk(BIOS_INFO, "CPU #%zd initialized\n", info->index); } void lb_arch_add_records(struct lb_header *header) diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 0e4a571..87c3fa2 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -628,14 +628,6 @@ return bsp_do_flight_plan(p); } -/* Calls cpu_initialize(info->index) which calls the coreboot CPU drivers. */ -static void mp_initialize_cpu(void) -{ - /* Call back into driver infrastructure for the AP initialization. */ - struct cpu_info *info = cpu_info(); - cpu_initialize(info->index); -} - void smm_initiate_relocation_parallel(void) { if (lapic_busy()) { @@ -1078,7 +1070,7 @@ /* Perform SMM relocation. */ MP_FR_NOBLOCK_APS(trigger_smm_relocation, trigger_smm_relocation), /* Initialize each CPU through the driver framework. */ - MP_FR_BLOCK_APS(mp_initialize_cpu, mp_initialize_cpu), + MP_FR_BLOCK_APS(cpu_initialize, cpu_initialize), /* Wait for APs to finish then optionally start looking for work. */ MP_FR_BLOCK_APS(ap_wait_for_instruction, NULL), }; diff --git a/src/include/cpu/cpu.h b/src/include/cpu/cpu.h index 955bd73..a77cb33 100644 --- a/src/include/cpu/cpu.h +++ b/src/include/cpu/cpu.h @@ -6,7 +6,7 @@ #include <arch/cpu.h> /* IWYU pragma: export */ #include <stdint.h> -void cpu_initialize(unsigned int cpu_index); +void cpu_initialize(void); /* Returns default APIC id based on logical_cpu number or < 0 on failure. */ int cpu_get_apic_id(int logical_cpu); uintptr_t cpu_get_lapic_addr(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/69504 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iad8e3cb318e6520ac5877118dbf43597dedb75b9 Gerrit-Change-Number: 69504 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[master]: cpu/cpu.h: Remove unused functions
by Arthur Heymans (Code Review) 12 Nov '22

12 Nov '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69503 ) Change subject: cpu/cpu.h: Remove unused functions ...................................................................... cpu/cpu.h: Remove unused functions These were dropped with LEGACY_SMP_INIT. Change-Id: Iecaf9ba3d31d22311557b885b31e98a0edd74d96 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/include/cpu/cpu.h 1 file changed, 12 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/69503/1 diff --git a/src/include/cpu/cpu.h b/src/include/cpu/cpu.h index e668de8..955bd73 100644 --- a/src/include/cpu/cpu.h +++ b/src/include/cpu/cpu.h @@ -13,8 +13,6 @@ /* Function to keep track of cpu default apic_id */ void cpu_add_map_entry(unsigned int index); struct bus; -void initialize_cpus(struct bus *cpu_bus); -asmlinkage void secondary_cpu_init(unsigned int cpu_index); int cpu_phys_address_size(void); #if ENV_RAMSTAGE -- To view, visit https://review.coreboot.org/c/coreboot/+/69503 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iecaf9ba3d31d22311557b885b31e98a0edd74d96 Gerrit-Change-Number: 69503 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2022