coreboot-gerrit November 2022

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[S] Change in coreboot[master]: src/soc/intel/xeon_sp/ras/hest.c: fix HEST table length
by Arthur Heymans (Code Review) 12 Nov '22

12 Nov '22

Attention is currently required from: Jonathan Zhang, Johnny Lin, Christian Walter, Li Jinfeng, Tim Chu. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69500 ) Change subject: src/soc/intel/xeon_sp/ras/hest.c: fix HEST table length ...................................................................... Patch Set 3: Code-Review-1 (2 comments) Patchset: PS3: The whole table generation is just plain wrong. I don't think it makes sense to just fix the returned without fixing the actual table genereation. File src/soc/intel/xeon_sp/ras/hest.c: https://review.coreboot.org/c/coreboot/+/69500/comment/bbdb5420_91cae2c8 PS3, Line 62: void *current; : current = (void *)(hest); : void *next = current; : next = hest + 1; Arithmetics on pointers to void is not defined in C. Gcc does accept it and sets size to 1 but it's not portable. Also it looks plain wrong. next will be right in the middle of the header. Look at the stoneyridge code on how it might be done. -- To view, visit https://review.coreboot.org/c/coreboot/+/69500 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4780785bac782aa966def3f042f365a1ead9d9d8 Gerrit-Change-Number: 69500 Gerrit-PatchSet: 3 Gerrit-Owner: Li Jinfeng <lijinfeng01(a)inspur.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Li Jinfeng <lijinfeng01(a)inspur.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Sat, 12 Nov 2022 14:22:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: arch/x86/mpspec.c: Drop weak write_smp_table()
by Arthur Heymans (Code Review) 12 Nov '22

12 Nov '22

Attention is currently required from: Kyösti Mälkki. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69489 ) Change subject: arch/x86/mpspec.c: Drop weak write_smp_table() ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69489 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1f38fb32a9436de64dfaf82e426cbd64b220ffa7 Gerrit-Change-Number: 69489 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Sat, 12 Nov 2022 14:05:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XL] Change in coreboot[master]: mb/*: Replace SNB PCI devices with references from chipset.cb
by build bot (Jenkins) (Code Review) 12 Nov '22

12 Nov '22

Attention is currently required from: Angel Pons, Alexander Couzens, Evgeny Zinoviev. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69502 ) Change subject: mb/*: Replace SNB PCI devices with references from chipset.cb ...................................................................... Patch Set 1: (8 comments) File src/mainboard/apple/macbookair4_2/devicetree.cb: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-163395): https://review.coreboot.org/c/coreboot/+/69502/comment/bf2376f0_6c1d58b9 PS1, Line 43: device ref hda on # High Definition Audio Audio controller Possible repeated word: 'Audio' File src/mainboard/asrock/b75pro3-m/devicetree.cb: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-163395): https://review.coreboot.org/c/coreboot/+/69502/comment/5733543b_5ac4bf47 PS1, Line 60: device ref hda on # High Definition Audio Audio controller Possible repeated word: 'Audio' File src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-163395): https://review.coreboot.org/c/coreboot/+/69502/comment/53fecaff_929a1bdc PS1, Line 33: device ref hda on end # High Definition Audio Audio controller Possible repeated word: 'Audio' File src/mainboard/hp/z220_series/devicetree.cb: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-163395): https://review.coreboot.org/c/coreboot/+/69502/comment/b080055f_79eacd8b PS1, Line 37: device ref hda on end # High Definition Audio Audio controller Possible repeated word: 'Audio' File src/mainboard/lenovo/l520/devicetree.cb: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-163395): https://review.coreboot.org/c/coreboot/+/69502/comment/6ad36cb4_9ed3338a PS1, Line 44: device ref hda on end # High Definition Audio Audio controller Possible repeated word: 'Audio' File src/mainboard/lenovo/s230u/devicetree.cb: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-163395): https://review.coreboot.org/c/coreboot/+/69502/comment/86ee302e_a7f51e1f PS1, Line 48: device ref hda on end # High Definition Audio Audio controller Possible repeated word: 'Audio' File src/mainboard/lenovo/t430/devicetree.cb: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-163395): https://review.coreboot.org/c/coreboot/+/69502/comment/24d6a344_5651ac81 PS1, Line 46: device ref hda on end # High Definition Audio Audio controller Possible repeated word: 'Audio' File src/mainboard/lenovo/x131e/devicetree.cb: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-163395): https://review.coreboot.org/c/coreboot/+/69502/comment/f9f8751d_ae05dfb0 PS1, Line 58: device ref hda on end # High Definition Audio Audio controller Possible repeated word: 'Audio' -- To view, visit https://review.coreboot.org/c/coreboot/+/69502 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I74c34a97ea4340fb11a0db422a48e1418221627e Gerrit-Change-Number: 69502 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Comment-Date: Sat, 12 Nov 2022 14:05:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/asus/p5gc-mx: Drop HAVE_MP_TABLE
by Arthur Heymans (Code Review) 12 Nov '22

12 Nov '22

Attention is currently required from: Kyösti Mälkki. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69487 ) Change subject: mb/asus/p5gc-mx: Drop HAVE_MP_TABLE ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69487 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib50a7656cef40d0d3ffcc408cc0858c1dae7b9e5 Gerrit-Change-Number: 69487 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Sat, 12 Nov 2022 14:04:54 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XL] Change in coreboot[master]: mb/*: Replace SNB PCI devices with references from chipset.cb
by Arthur Heymans (Code Review) 12 Nov '22

12 Nov '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69502 ) Change subject: mb/*: Replace SNB PCI devices with references from chipset.cb ...................................................................... mb/*: Replace SNB PCI devices with references from chipset.cb Change-Id: I74c34a97ea4340fb11a0db422a48e1418221627e Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/apple/macbookair4_2/devicetree.cb M src/mainboard/asrock/b75pro3-m/devicetree.cb M src/mainboard/asrock/h77pro4-m/devicetree.cb M src/mainboard/asus/h61-series/devicetree.cb M src/mainboard/asus/maximus_iv_gene-z/devicetree.cb M src/mainboard/asus/p8x7x-series/devicetree.cb M src/mainboard/biostar/th61-itx/devicetree.cb M src/mainboard/compulab/intense_pc/devicetree.cb M src/mainboard/dell/snb_ivb_workstations/variants/baseboard/devicetree.cb M src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb M src/mainboard/gigabyte/ga-h61m-series/devicetree.cb M src/mainboard/google/butterfly/devicetree.cb M src/mainboard/google/link/devicetree.cb M src/mainboard/google/parrot/devicetree.cb M src/mainboard/google/stout/devicetree.cb M src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb M src/mainboard/hp/snb_ivb_laptops/devicetree.cb M src/mainboard/hp/z220_series/devicetree.cb M src/mainboard/intel/dcp847ske/devicetree.cb M src/mainboard/intel/emeraldlake2/devicetree.cb M src/mainboard/kontron/ktqm77/devicetree.cb M src/mainboard/lenovo/l520/devicetree.cb M src/mainboard/lenovo/s230u/devicetree.cb M src/mainboard/lenovo/t420/devicetree.cb M src/mainboard/lenovo/t420s/devicetree.cb M src/mainboard/lenovo/t430/devicetree.cb M src/mainboard/lenovo/t430s/devicetree.cb M src/mainboard/lenovo/t520/devicetree.cb M src/mainboard/lenovo/t530/devicetree.cb M src/mainboard/lenovo/x131e/devicetree.cb M src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb M src/mainboard/lenovo/x220/devicetree.cb M src/mainboard/lenovo/x230/devicetree.cb M src/mainboard/msi/ms7707/devicetree.cb M src/mainboard/roda/rv11/variants/rv11/devicetree.cb M src/mainboard/roda/rv11/variants/rw11/devicetree.cb M src/mainboard/samsung/lumpy/devicetree.cb M src/mainboard/samsung/stumpy/devicetree.cb M src/mainboard/sapphire/pureplatinumh61/devicetree.cb M src/mainboard/supermicro/x9sae/devicetree.cb M src/mainboard/supermicro/x9scl/devicetree.cb 41 files changed, 1,025 insertions(+), 1,015 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/69502/1 diff --git a/src/mainboard/apple/macbookair4_2/devicetree.cb b/src/mainboard/apple/macbookair4_2/devicetree.cb index df2f154..f623c89 100644 --- a/src/mainboard/apple/macbookair4_2/devicetree.cb +++ b/src/mainboard/apple/macbookair4_2/devicetree.cb @@ -26,67 +26,67 @@ register "pcie_port_coalesce" = "true" register "sata_interface_speed_support" = "0x3" register "sata_port_map" = "0x1" - device pci 16.0 on # Management Engine Interface 1 + device ref mei1 on # Management Engine Interface 1 subsystemid 0x8086 0x7270 end - device pci 16.1 off # Management Engine Interface 2 + device ref mei2 off # Management Engine Interface 2 end - device pci 16.2 off # Management Engine IDE-R + device ref me_ide_r off # Management Engine IDE-R end - device pci 16.3 off # Management Engine KT + device ref me_kt off # Management Engine KT end - device pci 19.0 off # Intel Gigabit Ethernet + device ref gbe off # Intel Gigabit Ethernet end - device pci 1a.0 on # USB2 EHCI #2 Unsupported PCI device 8086:1c2c + device ref ehci2 on # USB2 EHCI #2 Unsupported PCI device 8086:1c2c subsystemid 0x8086 0x7270 end - device pci 1b.0 on # High Definition Audio Audio controller + device ref hda on # High Definition Audio Audio controller subsystemid 0x8086 0x7270 end - device pci 1c.0 on # PCIe Port #1 + device ref rp1 on # PCIe Port #1 subsystemid 0x8086 0x7270 end - device pci 1c.1 on # PCIe Port #2 + device ref rp2 on # PCIe Port #2 subsystemid 0x8086 0x7270 end - device pci 1c.2 off # PCIe Port #3 + device ref rp3 off # PCIe Port #3 end - device pci 1c.3 off # PCIe Port #4 + device ref rp4 off # PCIe Port #4 end - device pci 1c.4 off # PCIe Port #5 + device ref rp5 off # PCIe Port #5 end - device pci 1c.5 off # PCIe Port #6 + device ref rp6 off # PCIe Port #6 end - device pci 1c.6 off # PCIe Port #7 + device ref rp7 off # PCIe Port #7 end - device pci 1c.7 off # PCIe Port #8 + device ref rp8 off # PCIe Port #8 end - device pci 1d.0 on # USB2 EHCI #1 Unsupported PCI device 8086:1c27 + device ref ehci1 on # USB2 EHCI #1 Unsupported PCI device 8086:1c27 subsystemid 0x8086 0x7270 end - device pci 1e.0 off # PCI bridge + device ref pci_b off # PCI bridge end - device pci 1f.0 on # LPC bridge PCI-LPC bridge + device ref lpc on # LPC bridge PCI-LPC bridge subsystemid 0x8086 0x7270 end - device pci 1f.2 on # SATA Controller 1 + device ref sata1 on # SATA Controller 1 subsystemid 0x8086 0x7270 end - device pci 1f.3 on # SMBus + device ref smbus on # SMBus subsystemid 0x8086 0x7270 end - device pci 1f.5 off # SATA Controller 2 + device ref sata2 off # SATA Controller 2 end - device pci 1f.6 off # Thermal + device ref thermal off # Thermal end end - device pci 00.0 on # Host bridge Host bridge + device ref hb on # Host bridge Host bridge subsystemid 0x106b 0x00eb end - device pci 01.0 on # PCIe Bridge for discrete graphics Unsupported PCI device 8086:0101 + device ref peg10 on # PCIe Bridge for discrete graphics Unsupported PCI device 8086:0101 subsystemid 0x106b 0x00eb end - device pci 02.0 on # Internal graphics VGA controller + device ref igd on # Internal graphics VGA controller subsystemid 0x106b 0x00eb end device pci 1a.7 on diff --git a/src/mainboard/asrock/b75pro3-m/devicetree.cb b/src/mainboard/asrock/b75pro3-m/devicetree.cb index f45418f..e121156 100644 --- a/src/mainboard/asrock/b75pro3-m/devicetree.cb +++ b/src/mainboard/asrock/b75pro3-m/devicetree.cb @@ -15,13 +15,13 @@ register "gpu_pch_backlight" = "0x00000000" device domain 0 on - device pci 00.0 on + device ref hb on subsystemid 0x1849 0x0150 end - device pci 01.0 on + device ref peg10 on subsystemid 0x1849 0x0151 end - device pci 02.0 on + device ref igd on subsystemid 0x1849 0x0152 end chip southbridge/intel/bd82x6x @@ -39,53 +39,53 @@ register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" - device pci 14.0 on # USB 3.0 Controller + device ref xhci on # USB 3.0 Controller subsystemid 0x1849 0x1e31 end - device pci 16.0 on # Management Engine Interface 1 + device ref mei1 on # Management Engine Interface 1 subsystemid 0x1849 0x1e3a end - device pci 16.1 off # Management Engine Interface 2 + device ref mei2 off # Management Engine Interface 2 end - device pci 16.2 off # Management Engine IDE-R + device ref me_ide_r off # Management Engine IDE-R end - device pci 16.3 on # Management Engine KT + device ref me_kt on # Management Engine KT subsystemid 0x1849 0x1e3d end - device pci 19.0 off # Intel Gigabit Ethernet + device ref gbe off # Intel Gigabit Ethernet end - device pci 1a.0 on # USB2 EHCI #2 + device ref ehci2 on # USB2 EHCI #2 subsystemid 0x1849 0x1e2d end - device pci 1b.0 on # High Definition Audio Audio controller + device ref hda on # High Definition Audio Audio controller subsystemid 0x1849 0x8892 end - device pci 1c.0 on # PCIe Port #1 + device ref rp1 on # PCIe Port #1 subsystemid 0x1849 0x1e10 end - device pci 1c.1 off # PCIe Port #2 + device ref rp2 off # PCIe Port #2 end - device pci 1c.2 off # PCIe Port #3 + device ref rp3 off # PCIe Port #3 end - device pci 1c.3 off # PCIe Port #4 + device ref rp4 off # PCIe Port #4 end - device pci 1c.4 on # PCIe Port #5, ASMedia ASM1062 SATA Controller + device ref rp5 on # PCIe Port #5, ASMedia ASM1062 SATA Controller subsystemid 0x1849 0x1e18 end - device pci 1c.5 on # PCIe Port #6, Realtek PCIe GbE Controller + device ref rp6 on # PCIe Port #6, Realtek PCIe GbE Controller subsystemid 0x1849 0x1e1a end - device pci 1c.6 off # PCIe Port #7 + device ref rp7 off # PCIe Port #7 end - device pci 1c.7 off # PCIe Port #8 + device ref rp8 off # PCIe Port #8 end - device pci 1d.0 on # USB2 EHCI #1 + device ref ehci1 on # USB2 EHCI #1 subsystemid 0x1849 0x1e26 end - device pci 1e.0 on # PCI bridge + device ref pci_b on # PCI bridge subsystemid 0x1849 0x244e end - device pci 1f.0 on # LPC bridge + device ref lpc on # LPC bridge subsystemid 0x1849 0x1e49 chip superio/nuvoton/nct6776 device pnp 2e.0 off end # Floppy @@ -130,15 +130,15 @@ device pnp 2e.17 on end # GPIOA end end - device pci 1f.2 on # SATA Controller 1 + device ref sata1 on # SATA Controller 1 subsystemid 0x1849 0x1e02 end - device pci 1f.3 on # SMBus + device ref smbus on # SMBus subsystemid 0x1849 0x1e22 end - device pci 1f.5 off # SATA Controller 2 + device ref sata2 off # SATA Controller 2 end - device pci 1f.6 off # Thermal + device ref thermal off # Thermal end end end diff --git a/src/mainboard/asrock/h77pro4-m/devicetree.cb b/src/mainboard/asrock/h77pro4-m/devicetree.cb index 7d94706..a3129a2 100644 --- a/src/mainboard/asrock/h77pro4-m/devicetree.cb +++ b/src/mainboard/asrock/h77pro4-m/devicetree.cb @@ -2,11 +2,11 @@ chip northbridge/intel/sandybridge device domain 0 on - device pci 00.0 on # Host bridge + device ref hb on # Host bridge subsystemid 0x1849 0x0100 end - device pci 01.0 on end # PEG - slot "PCIE1" - device pci 02.0 on # iGPU + device ref peg10 on end # PEG - slot "PCIE1" + device ref igd on # iGPU subsystemid 0x1849 0x0102 end chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH @@ -20,45 +20,45 @@ register "superspeed_capable_ports" = "0x0000000f" register "xhci_overcurrent_mapping" = "0x00000c03" register "xhci_switchable_ports" = "0x0000000f" - device pci 14.0 on # USB 3.0 Controller + device ref xhci on # USB 3.0 Controller subsystemid 0x1849 0x1e31 end - device pci 16.0 on # Management Engine Interface 1 + device ref mei1 on # Management Engine Interface 1 subsystemid 0x1849 0x1e3a end - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 19.0 off end # Intel Gigabit Ethernet - device pci 1a.0 on # USB2 EHCI #2 + device ref mei2 off end # Management Engine Interface 2 + device ref me_ide_r off end # Management Engine IDE-R + device ref me_kt off end # Management Engine KT + device ref gbe off end # Intel Gigabit Ethernet + device ref ehci2 on # USB2 EHCI #2 subsystemid 0x1849 0x1e2d end - device pci 1b.0 on # High Definition Audio + device ref hda on # High Definition Audio subsystemid 0x1849 0x8892 end - device pci 1c.0 on # PCIe Port #1 - slot "PCIE4", 4 lanes + device ref rp1 on # PCIe Port #1 - slot "PCIE4", 4 lanes subsystemid 0x1849 0x1e10 end - device pci 1c.1 off end # PCIe Port #2 - device pci 1c.2 off end # PCIe Port #3 - device pci 1c.3 off end # PCIe Port #4 - device pci 1c.4 on # PCIe Port #5 - slot "PCIE2", 1 lane + device ref rp2 off end # PCIe Port #2 + device ref rp3 off end # PCIe Port #3 + device ref rp4 off end # PCIe Port #4 + device ref rp5 on # PCIe Port #5 - slot "PCIE2", 1 lane subsystemid 0x1849 0x1e18 end - device pci 1c.5 on # PCIe Port #6 - RTL8111E GbE + device ref rp6 on # PCIe Port #6 - RTL8111E GbE subsystemid 0x1849 0x1e1a end - device pci 1c.6 on # PCIe Port #7 - slot "PCIE3", 1 lane + device ref rp7 on # PCIe Port #7 - slot "PCIE3", 1 lane subsystemid 0x1849 0x1e16 end - device pci 1c.7 on # PCIe Port #8 - ASM1061 SATA Controller + device ref rp8 on # PCIe Port #8 - ASM1061 SATA Controller subsystemid 0x1849 0x1e1e end - device pci 1d.0 on # USB2 EHCI #1 + device ref ehci1 on # USB2 EHCI #1 subsystemid 0x1849 0x1e26 end - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on # LPC bridge + device ref pci_b off end # PCI bridge + device ref lpc on # LPC bridge subsystemid 0x1849 0x1e4a chip superio/nuvoton/nct6776 device pnp 2e.0 off end # Floppy @@ -118,14 +118,14 @@ device pnp 2e.17 off end # GPIOA end end - device pci 1f.2 on # SATA (AHCI) + device ref sata1 on # SATA (AHCI) subsystemid 0x1849 0x1e02 end - device pci 1f.3 on # SMBus + device ref smbus on # SMBus subsystemid 0x1849 0x1e22 end - device pci 1f.5 off end # SATA (Legacy) - device pci 1f.6 off end # Thermal + device ref sata2 off end # SATA (Legacy) + device ref thermal off end # Thermal end end end diff --git a/src/mainboard/asus/h61-series/devicetree.cb b/src/mainboard/asus/h61-series/devicetree.cb index abed76a..897cb8f 100644 --- a/src/mainboard/asus/h61-series/devicetree.cb +++ b/src/mainboard/asus/h61-series/devicetree.cb @@ -2,39 +2,39 @@ chip northbridge/intel/sandybridge device domain 0 on - device pci 00.0 on end # Host bridge - device pci 01.0 on end # PEG - device pci 02.0 on end # iGPU + device ref hb on end # Host bridge + device ref peg10 on end # PEG + device ref igd on end # iGPU chip southbridge/intel/bd82x6x register "sata_port_map" = "0x33" register "spi_lvscc" = "0x2005" register "spi_uvscc" = "0x2005" - device pci 16.0 on end # MEI #1 - device pci 16.1 off end # MEI #2 - device pci 16.2 off end # ME IDE-R - device pci 16.3 off end # ME KT - device pci 19.0 off end # Intel GbE - device pci 1a.0 on end # EHCI #2 - device pci 1b.0 on end # HD Audio + device ref mei1 on end # MEI #1 + device ref mei2 off end # MEI #2 + device ref me_ide_r off end # ME IDE-R + device ref me_kt off end # ME KT + device ref gbe off end # Intel GbE + device ref ehci2 on end # EHCI #2 + device ref hda on end # HD Audio - device pci 1c.0 off end # RP #1 - device pci 1c.1 off end # RP #2 - device pci 1c.2 off end # RP #3 - device pci 1c.3 off end # RP #4 - device pci 1c.4 off end # RP #5 - device pci 1c.5 off end # RP #6 - device pci 1c.6 off end # RP #7 - device pci 1c.7 off end # RP #8 + device ref rp1 off end # RP #1 + device ref rp2 off end # RP #2 + device ref rp3 off end # RP #3 + device ref rp4 off end # RP #4 + device ref rp5 off end # RP #5 + device ref rp6 off end # RP #6 + device ref rp7 off end # RP #7 + device ref rp8 off end # RP #8 - device pci 1d.0 on end # EHCI #1 - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on end # LPC bridge - device pci 1f.2 on end # SATA (AHCI) - device pci 1f.3 on end # SMBus - device pci 1f.5 off end # SATA (Legacy) - device pci 1f.6 off end # Thermal + device ref ehci1 on end # EHCI #1 + device ref pci_b off end # PCI bridge + device ref lpc on end # LPC bridge + device ref sata1 on end # SATA (AHCI) + device ref smbus on end # SMBus + device ref sata2 off end # SATA (Legacy) + device ref thermal off end # Thermal end end end diff --git a/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb b/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb index 41fc4dc..134a393 100644 --- a/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb +++ b/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb @@ -4,9 +4,9 @@ device domain 0 on subsystemid 0x1043 0x844d inherit - device pci 00.0 on end # Host bridge - device pci 01.0 on end # PCIe bridge for discrete graphics - device pci 02.0 on end # VGA controller + device ref hb on end # Host bridge + device ref peg10 on end # PCIe bridge for discrete graphics + device ref igd on end # VGA controller chip southbridge/intel/bd82x6x register "gen1_dec" = "0x00000295" # Super I/O HWM @@ -14,28 +14,28 @@ register "spi_lvscc" = "0x2005" register "spi_uvscc" = "0x2005" - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 19.0 on # Intel Gigabit Ethernet + device ref mei1 on end # Management Engine Interface 1 + device ref mei2 off end # Management Engine Interface 2 + device ref me_ide_r off end # Management Engine IDE-R + device ref me_kt off end # Management Engine KT + device ref gbe on # Intel Gigabit Ethernet subsystemid 0x1043 0x849c end - device pci 1a.0 on end # USB2 EHCI #2 - device pci 1b.0 on # HD audio controller + device ref ehci2 on end # USB2 EHCI #2 + device ref hda on # HD audio controller subsystemid 0x1043 0x84dc end - device pci 1c.0 on end # PCIe port #1 - device pci 1c.1 off end # PCIe port #2 - device pci 1c.2 off end # PCIe port #3 - device pci 1c.3 off end # PCIe port #4 - device pci 1c.4 on end # PCIe port #5 - device pci 1c.5 on end # PCIe port #6 - device pci 1c.6 on end # PCIe port #7 - device pci 1c.7 off end # PCIe port #8 - device pci 1d.0 on end # USB2 EHCI #1 - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on # LPC bridge + device ref rp1 on end # PCIe port #1 + device ref rp2 off end # PCIe port #2 + device ref rp3 off end # PCIe port #3 + device ref rp4 off end # PCIe port #4 + device ref rp5 on end # PCIe port #5 + device ref rp6 on end # PCIe port #6 + device ref rp7 on end # PCIe port #7 + device ref rp8 off end # PCIe port #8 + device ref ehci1 on end # USB2 EHCI #1 + device ref pci_b off end # PCI bridge + device ref lpc on # LPC bridge chip superio/nuvoton/nct6776 device pnp 2e.0 off end # Floppy device pnp 2e.1 off end # Parallel @@ -74,10 +74,10 @@ device pnp 2e.17 off end # GPIOA end end - device pci 1f.2 on end # SATA controller 1 - device pci 1f.3 on end # SMBus - device pci 1f.5 off end # SATA controller 2 - device pci 1f.6 off end # Thermal + device ref sata1 on end # SATA controller 1 + device ref smbus on end # SMBus + device ref sata2 off end # SATA controller 2 + device ref thermal off end # Thermal end end end diff --git a/src/mainboard/asus/p8x7x-series/devicetree.cb b/src/mainboard/asus/p8x7x-series/devicetree.cb index 75566d1..6c81211 100644 --- a/src/mainboard/asus/p8x7x-series/devicetree.cb +++ b/src/mainboard/asus/p8x7x-series/devicetree.cb @@ -2,9 +2,9 @@ chip northbridge/intel/sandybridge device domain 0 on - device pci 00.0 on end # Host bridge - device pci 01.0 on end # PCIEX16_1 - device pci 02.0 on end # iGPU + device ref hb on end # Host bridge + device ref peg10 on end # PCIEX16_1 + device ref igd on end # iGPU chip southbridge/intel/bd82x6x register "sata_interface_speed_support" = "0x3" @@ -15,32 +15,32 @@ register "xhci_overcurrent_mapping" = "0x00000c03" register "xhci_switchable_ports" = "0x0000000f" - device pci 14.0 on end # xHCI - device pci 16.0 on end # MEI #1 - device pci 16.1 off end # MEI #2 - device pci 16.2 off end # ME IDE-R - device pci 16.3 off end # ME KT - device pci 19.0 off end # Intel GbE - device pci 1a.0 on end # EHCI #2 - device pci 1b.0 on end # HD Audio + device ref xhci on end # xHCI + device ref mei1 on end # MEI #1 + device ref mei2 off end # MEI #2 + device ref me_ide_r off end # ME IDE-R + device ref me_kt off end # ME KT + device ref gbe off end # Intel GbE + device ref ehci2 on end # EHCI #2 + device ref hda on end # HD Audio - device pci 1c.0 off end # RP #1 - device pci 1c.1 off end # RP #2 - device pci 1c.2 off end # RP #3 - device pci 1c.3 off end # RP #4 - device pci 1c.4 off end # RP #5 - device pci 1c.5 off end # RP #6 - device pci 1c.6 off end # RP #7 - device pci 1c.7 off end # RP #8 + device ref rp1 off end # RP #1 + device ref rp2 off end # RP #2 + device ref rp3 off end # RP #3 + device ref rp4 off end # RP #4 + device ref rp5 off end # RP #5 + device ref rp6 off end # RP #6 + device ref rp7 off end # RP #7 + device ref rp8 off end # RP #8 - device pci 1d.0 on end # EHCI #1 - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on # LPC bridge + device ref ehci1 on end # EHCI #1 + device ref pci_b off end # PCI bridge + device ref lpc on # LPC bridge end - device pci 1f.2 on end # SATA (AHCI) - device pci 1f.3 on end # SMBus - device pci 1f.5 off end # SATA (Legacy) - device pci 1f.6 off end # Thermal + device ref sata1 on end # SATA (AHCI) + device ref smbus on end # SMBus + device ref sata2 off end # SATA (Legacy) + device ref thermal off end # Thermal end end end diff --git a/src/mainboard/biostar/th61-itx/devicetree.cb b/src/mainboard/biostar/th61-itx/devicetree.cb index 5999a1d..ed8f0fba 100644 --- a/src/mainboard/biostar/th61-itx/devicetree.cb +++ b/src/mainboard/biostar/th61-itx/devicetree.cb @@ -4,9 +4,9 @@ device domain 0 on subsystemid 0x1565 0x3108 inherit - device pci 00.0 on end # Host bridge - device pci 01.0 on end # PEG - device pci 02.0 on end # iGPU + device ref hb on end # Host bridge + device ref peg10 on end # PEG + device ref igd on end # iGPU chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "gen1_dec" = "0x003c0a01" @@ -15,18 +15,18 @@ register "spi_lvscc" = "0x2005" register "spi_uvscc" = "0x2005" - device pci 16.0 on end # MEI #1 - device pci 1a.0 on end # EHCI #2 - device pci 1b.0 on end # HD Audio - device pci 1c.0 on end # RP #1: Realtek RTL8111F GbE NIC - device pci 1c.1 on end # RP #2: ASMedia ASM1042 USB3 #1 - device pci 1c.2 on end # RP #3: ASMedia ASM1042 USB3 #2 - device pci 1c.3 off end # RP #4 - device pci 1c.4 off end # RP #5 - device pci 1c.5 off end # RP #6 - device pci 1d.0 on end # EHCI #1 - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on # LPC bridge + device ref mei1 on end # MEI #1 + device ref ehci2 on end # EHCI #2 + device ref hda on end # HD Audio + device ref rp1 on end # RP #1: Realtek RTL8111F GbE NIC + device ref rp2 on end # RP #2: ASMedia ASM1042 USB3 #1 + device ref rp3 on end # RP #3: ASMedia ASM1042 USB3 #2 + device ref rp4 off end # RP #4 + device ref rp5 off end # RP #5 + device ref rp6 off end # RP #6 + device ref ehci1 on end # EHCI #1 + device ref pci_b off end # PCI bridge + device ref lpc on # LPC bridge chip superio/ite/it8728f device pnp 2e.0 off end # Floppy device pnp 2e.1 off end # COM1 @@ -56,10 +56,10 @@ device pnp 2e.a off end # CIR end end - device pci 1f.2 on end # SATA #1 - device pci 1f.3 on end # SMBus - device pci 1f.5 off end # SATA #2 (IDE mode) - device pci 1f.6 on end # Thermal subsystem + device ref sata1 on end # SATA #1 + device ref smbus on end # SMBus + device ref sata2 off end # SATA #2 (IDE mode) + device ref thermal on end # Thermal subsystem end end end diff --git a/src/mainboard/compulab/intense_pc/devicetree.cb b/src/mainboard/compulab/intense_pc/devicetree.cb index 1ce2341..091e110 100644 --- a/src/mainboard/compulab/intense_pc/devicetree.cb +++ b/src/mainboard/compulab/intense_pc/devicetree.cb @@ -7,16 +7,16 @@ register "gpu_dp_d_hotplug" = "4" device domain 0 on - device pci 00.0 on # Host bridge + device ref hb on # Host bridge subsystemid 0x8086 0x2010 end - device pci 01.0 on # PCIe Bridge for discrete graphics + device ref peg10 on # PCIe Bridge for discrete graphics subsystemid 0x8086 0x2010 end - device pci 01.1 on # PCIe Bridge for discrete graphics + device ref peg11 on # PCIe Bridge for discrete graphics subsystemid 0x8086 0x2010 end - device pci 02.0 on # Internal graphics VGA controller + device ref igd on # Internal graphics VGA controller subsystemid 0x8086 0x2211 end @@ -47,29 +47,29 @@ register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" - device pci 14.0 on end # USB 3.0 Controller - device pci 16.0 off end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 19.0 on end # Intel Gigabit Ethernet - device pci 1a.0 on end # USB2 EHCI #2 - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 on end # PCIe Port #1 - device pci 1c.1 on end # PCIe Port #2 - device pci 1c.2 on end # PCIe Port #3 - device pci 1c.3 off end # PCIe Port #4 - device pci 1c.4 on end # PCIe Port #5 - device pci 1c.5 off end # PCIe Port #6 - device pci 1c.6 off end # PCIe Port #7 - device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on end # USB2 EHCI #1 - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on end # LPC bridge - device pci 1f.2 on end # SATA Controller 1 - device pci 1f.3 on end # SMBus - device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 on end # Thermal + device ref xhci on end # USB 3.0 Controller + device ref mei1 off end # Management Engine Interface 1 + device ref mei2 off end # Management Engine Interface 2 + device ref me_ide_r off end # Management Engine IDE-R + device ref me_kt off end # Management Engine KT + device ref gbe on end # Intel Gigabit Ethernet + device ref ehci2 on end # USB2 EHCI #2 + device ref hda on end # High Definition Audio + device ref rp1 on end # PCIe Port #1 + device ref rp2 on end # PCIe Port #2 + device ref rp3 on end # PCIe Port #3 + device ref rp4 off end # PCIe Port #4 + device ref rp5 on end # PCIe Port #5 + device ref rp6 off end # PCIe Port #6 + device ref rp7 off end # PCIe Port #7 + device ref rp8 off end # PCIe Port #8 + device ref ehci1 on end # USB2 EHCI #1 + device ref pci_b off end # PCI bridge + device ref lpc on end # LPC bridge + device ref sata1 on end # SATA Controller 1 + device ref smbus on end # SMBus + device ref sata2 off end # SATA Controller 2 + device ref thermal on end # Thermal end end end diff --git a/src/mainboard/dell/snb_ivb_workstations/variants/baseboard/devicetree.cb b/src/mainboard/dell/snb_ivb_workstations/variants/baseboard/devicetree.cb index 94351fa..3931f14 100644 --- a/src/mainboard/dell/snb_ivb_workstations/variants/baseboard/devicetree.cb +++ b/src/mainboard/dell/snb_ivb_workstations/variants/baseboard/devicetree.cb @@ -1,12 +1,12 @@ chip northbridge/intel/sandybridge device domain 0 on - device pci 00.0 on end # Host bridge Host bridge - device pci 01.0 on # PEG1 (blue slot1) + device ref hb on end # Host bridge Host bridge + device ref peg10 on # PEG1 (blue slot1) smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthLong" "SLOT1" "SlotDataBusWidth16X" end - device pci 02.0 on end # Internal graphics VGA controller - device pci 06.0 off end # PEG2 + device ref igd on end # Internal graphics VGA controller + device ref peg60 off end # PEG2 chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH register "gpe0_en" = "0x00002a46" @@ -24,25 +24,25 @@ register "superspeed_capable_ports" = "0x0000000f" register "xhci_overcurrent_mapping" = "0x08040201" register "xhci_switchable_ports" = "0x0000000f" - device pci 14.0 on end # USB 3.0 Controller - device pci 16.0 off end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 19.0 on end # Intel Gigabit Ethernet - device pci 1a.0 on end # USB2 EHCI #2 - device pci 1b.0 on end # High Definition Audio controller - device pci 1c.0 off end # PCIe Port #1 - device pci 1c.1 off end # PCIe Port #2 - device pci 1c.2 off end # PCIe Port #3 - device pci 1c.3 off end # PCIe Port #4 - device pci 1c.4 off end # PCIe Port #5 - device pci 1c.5 off end # PCIe Port #6 - device pci 1c.6 off end # PCIe Port #7 - device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on end # USB2 EHCI #1 - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on # LPC bridge + device ref xhci on end # USB 3.0 Controller + device ref mei1 off end # Management Engine Interface 1 + device ref mei2 off end # Management Engine Interface 2 + device ref me_ide_r off end # Management Engine IDE-R + device ref me_kt off end # Management Engine KT + device ref gbe on end # Intel Gigabit Ethernet + device ref ehci2 on end # USB2 EHCI #2 + device ref hda on end # High Definition Audio controller + device ref rp1 off end # PCIe Port #1 + device ref rp2 off end # PCIe Port #2 + device ref rp3 off end # PCIe Port #3 + device ref rp4 off end # PCIe Port #4 + device ref rp5 off end # PCIe Port #5 + device ref rp6 off end # PCIe Port #6 + device ref rp7 off end # PCIe Port #7 + device ref rp8 off end # PCIe Port #8 + device ref ehci1 on end # USB2 EHCI #1 + device ref pci_b off end # PCI bridge + device ref lpc on # LPC bridge chip drivers/pc80/tpm device pnp 0c31.0 on end end @@ -72,10 +72,10 @@ device pnp 2e.11 off end # PP end end - device pci 1f.2 on end # SATA Controller 1 - device pci 1f.3 on end # SMBus - device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 on end # Thermal + device ref sata1 on end # SATA Controller 1 + device ref smbus on end # SMBus + device ref sata2 off end # SATA Controller 2 + device ref thermal on end # Thermal end end end diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb index d7263c8..d23cc5a 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb +++ b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb @@ -1,11 +1,11 @@ chip northbridge/intel/sandybridge device domain 0 on subsystemid 0x1458 0x5000 inherit - device pci 00.0 on # Host bridge + device ref hb on # Host bridge subsystemid 0x1458 0x5000 end - device pci 01.0 on end # PCIe Bridge for discrete graphics - device pci 02.0 on # Integrated VGA controller + device ref peg10 on end # PCIe Bridge for discrete graphics + device ref igd on # Integrated VGA controller subsystemid 0x1458 0xd000 end @@ -20,37 +20,37 @@ register "superspeed_capable_ports" = "0xf" - device pci 14.0 on # USB 3.0 Controller + device ref xhci on # USB 3.0 Controller subsystemid 0x1458 0x5007 end - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 19.0 off end # Intel Gigabit Ethernet - device pci 1a.0 on # USB2 EHCI #2 + device ref mei1 on end # Management Engine Interface 1 + device ref mei2 off end # Management Engine Interface 2 + device ref me_ide_r off end # Management Engine IDE-R + device ref me_kt off end # Management Engine KT + device ref gbe off end # Intel Gigabit Ethernet + device ref ehci2 on # USB2 EHCI #2 subsystemid 0x1458 0x5006 end - device pci 1b.0 on # High Definition Audio + device ref hda on # High Definition Audio subsystemid 0x1458 0xa002 end - device pci 1c.0 on end # PCIe Port #1 - device pci 1c.1 off end # PCIe Port #2 - device pci 1c.2 off end # PCIe Port #3 - device pci 1c.3 off end # PCIe Port #4 - device pci 1c.4 on # PCIe Port #5 + device ref rp1 on end # PCIe Port #1 + device ref rp2 off end # PCIe Port #2 + device ref rp3 off end # PCIe Port #3 + device ref rp4 off end # PCIe Port #4 + device ref rp5 on # PCIe Port #5 device pci 00.0 on # PCI 10ec:8168 subsystemid 0x1458 0xe000 end end - device pci 1c.5 off end # PCIe Port #6 - device pci 1c.6 off end # PCIe Port #7 - device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on # USB2 EHCI #1 + device ref rp6 off end # PCIe Port #6 + device ref rp7 off end # PCIe Port #7 + device ref rp8 off end # PCIe Port #8 + device ref ehci1 on # USB2 EHCI #1 subsystemid 0x1458 0x5006 end - device pci 1e.0 on end # PCI bridge - device pci 1f.0 on # ISA/LPC bridge + device ref pci_b on end # PCI bridge + device ref lpc on # ISA/LPC bridge subsystemid 0x1458 0x5001 chip superio/ite/it8728f device pnp 2e.0 off end # FDC @@ -88,14 +88,14 @@ device pnp 0c31.0 on end end end - device pci 1f.2 on # SATA Controller 1 + device ref sata1 on # SATA Controller 1 subsystemid 0x1458 0xb005 end - device pci 1f.3 on # SMBus + device ref smbus on # SMBus subsystemid 0x1458 0x5001 end device pci 1f.4 off end - device pci 1f.5 off end # SATA Controller 2 + device ref sata2 off end # SATA Controller 2 end end end diff --git a/src/mainboard/gigabyte/ga-h61m-series/devicetree.cb b/src/mainboard/gigabyte/ga-h61m-series/devicetree.cb index 299c134..3fd3eac 100644 --- a/src/mainboard/gigabyte/ga-h61m-series/devicetree.cb +++ b/src/mainboard/gigabyte/ga-h61m-series/devicetree.cb @@ -4,9 +4,9 @@ device domain 0 on subsystemid 0x1458 0x5000 inherit - device pci 00.0 on end # Host bridge - device pci 01.0 on end # PEG - device pci 02.0 on end # iGPU + device ref hb on end # Host bridge + device ref peg10 on end # PEG + device ref igd on end # iGPU chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "gen1_dec" = "0x003c0a01" @@ -15,17 +15,17 @@ register "spi_lvscc" = "0x2005" register "spi_uvscc" = "0x2005" - device pci 16.0 on end # MEI #1 - device pci 1a.0 on end # USB2 EHCI #2 - device pci 1b.0 on end # HD Audio + device ref mei1 on end # MEI #1 + device ref ehci2 on end # USB2 EHCI #2 + device ref hda on end # HD Audio - device pci 1d.0 on end # USB2 EHCI #1 - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on end # LPC bridge - device pci 1f.2 on end # SATA Controller 1 - device pci 1f.3 on end # SMBus - device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 on end # Thermal + device ref ehci1 on end # USB2 EHCI #1 + device ref pci_b off end # PCI bridge + device ref lpc on end # LPC bridge + device ref sata1 on end # SATA Controller 1 + device ref smbus on end # SMBus + device ref sata2 off end # SATA Controller 2 + device ref thermal on end # Thermal end end end diff --git a/src/mainboard/google/butterfly/devicetree.cb b/src/mainboard/google/butterfly/devicetree.cb index 5ff7f9d..220ba07 100644 --- a/src/mainboard/google/butterfly/devicetree.cb +++ b/src/mainboard/google/butterfly/devicetree.cb @@ -21,9 +21,9 @@ register "max_mem_clock_mhz" = "666" # DDR3-1333 device domain 0 on - device pci 00.0 on end # host bridge - device pci 01.0 off end # PCIe Bridge for discrete graphics - device pci 02.0 on end # vga controller + device ref hb on end # host bridge + device ref peg10 off end # PCIe Bridge for discrete graphics + device ref igd on end # vga controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH # GPI routing @@ -48,27 +48,27 @@ # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "true" - device pci 14.0 on end # USB 3.0 Controller - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 19.0 off end # Intel Gigabit Ethernet - device pci 1a.0 on end # USB2 EHCI #2 - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 on end # PCIe Port #1 (mini PCIe Slot - WLAN & Serial debug) - device pci 1c.1 on end # PCIe Port #2 (ETH0) - device pci 1c.2 on end # PCIe Port #3 (Card Reader) + device ref xhci on end # USB 3.0 Controller + device ref mei1 on end # Management Engine Interface 1 + device ref mei2 off end # Management Engine Interface 2 + device ref me_ide_r off end # Management Engine IDE-R + device ref me_kt off end # Management Engine KT + device ref gbe off end # Intel Gigabit Ethernet + device ref ehci2 on end # USB2 EHCI #2 + device ref hda on end # High Definition Audio + device ref rp1 on end # PCIe Port #1 (mini PCIe Slot - WLAN & Serial debug) + device ref rp2 on end # PCIe Port #2 (ETH0) + device ref rp3 on end # PCIe Port #3 (Card Reader) #force ASPM for PCIe bridge to Card Reader register "pcie_aspm[2]" = "0x3" - device pci 1c.3 off end # PCIe Port #4 - device pci 1c.4 off end # PCIe Port #5 - device pci 1c.5 off end # PCIe Port #6 - device pci 1c.6 off end # PCIe Port #7 - device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on end # USB2 EHCI #1 - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on #LPC bridge + device ref rp4 off end # PCIe Port #4 + device ref rp5 off end # PCIe Port #5 + device ref rp6 off end # PCIe Port #6 + device ref rp7 off end # PCIe Port #7 + device ref rp8 off end # PCIe Port #8 + device ref ehci1 on end # USB2 EHCI #1 + device ref pci_b off end # PCI bridge + device ref lpc on #LPC bridge chip drivers/pc80/tpm device pnp 0c31.0 on end end @@ -78,10 +78,10 @@ end end end # LPC bridge - device pci 1f.2 on end # SATA Controller 1 - device pci 1f.3 on end # SMBus - device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 on end # Thermal + device ref sata1 on end # SATA Controller 1 + device ref smbus on end # SMBus + device ref sata2 off end # SATA Controller 2 + device ref thermal on end # Thermal end end end diff --git a/src/mainboard/google/link/devicetree.cb b/src/mainboard/google/link/devicetree.cb index 4116188..929056e 100644 --- a/src/mainboard/google/link/devicetree.cb +++ b/src/mainboard/google/link/devicetree.cb @@ -21,8 +21,8 @@ device domain 0 on subsystemid 0x1ae0 0xc000 inherit - device pci 00.0 on end # host bridge - device pci 02.0 on end # vga controller + device ref hb on end # host bridge + device ref igd on end # vga controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH # GPI routing @@ -46,24 +46,24 @@ # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "true" - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 19.0 off end # Intel Gigabit Ethernet - device pci 1a.0 on end # USB2 EHCI #2 - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 off end # PCIe Port #1 (WLAN remapped) - device pci 1c.1 off end # PCIe Port #2 - device pci 1c.2 on end # PCIe Port #3 (WLAN actual) - device pci 1c.3 off end # PCIe Port #4 - device pci 1c.4 off end # PCIe Port #5 - device pci 1c.5 off end # PCIe Port #6 - device pci 1c.6 off end # PCIe Port #7 - device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on end # USB2 EHCI #1 - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on + device ref mei1 on end # Management Engine Interface 1 + device ref mei2 off end # Management Engine Interface 2 + device ref me_ide_r off end # Management Engine IDE-R + device ref me_kt off end # Management Engine KT + device ref gbe off end # Intel Gigabit Ethernet + device ref ehci2 on end # USB2 EHCI #2 + device ref hda on end # High Definition Audio + device ref rp1 off end # PCIe Port #1 (WLAN remapped) + device ref rp2 off end # PCIe Port #2 + device ref rp3 on end # PCIe Port #3 (WLAN actual) + device ref rp4 off end # PCIe Port #4 + device ref rp5 off end # PCIe Port #5 + device ref rp6 off end # PCIe Port #6 + device ref rp7 off end # PCIe Port #7 + device ref rp8 off end # PCIe Port #8 + device ref ehci1 on end # USB2 EHCI #1 + device ref pci_b off end # PCI bridge + device ref lpc on chip drivers/pc80/tpm device pnp 0c31.0 on end end @@ -75,10 +75,10 @@ end end end # LPC bridge - device pci 1f.2 on end # SATA Controller 1 - device pci 1f.3 on end # SMBus - device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 on end # Thermal + device ref sata1 on end # SATA Controller 1 + device ref smbus on end # SMBus + device ref sata2 off end # SATA Controller 2 + device ref thermal on end # Thermal end end end diff --git a/src/mainboard/google/parrot/devicetree.cb b/src/mainboard/google/parrot/devicetree.cb index 7c1cc81..96d546a 100644 --- a/src/mainboard/google/parrot/devicetree.cb +++ b/src/mainboard/google/parrot/devicetree.cb @@ -20,8 +20,8 @@ register "max_mem_clock_mhz" = "666" device domain 0 on - device pci 00.0 on end # host bridge - device pci 02.0 on end # vga controller + device ref hb on end # host bridge + device ref igd on end # vga controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH # GPI routing @@ -44,34 +44,34 @@ # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "true" - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 19.0 off end # Intel Gigabit Ethernet - device pci 1a.0 on end # USB2 EHCI #2 - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 off end # PCIe Port #1 - device pci 1c.1 on end # PCIe Port #2 (WLAN) - device pci 1c.2 on end # PCIe Port #3 (ETH0) - device pci 1c.3 off end # PCIe Port #4 - device pci 1c.4 off end # PCIe Port #5 - device pci 1c.5 off end # PCIe Port #6 - device pci 1c.6 off end # PCIe Port #7 - device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on end # USB2 EHCI #1 - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on + device ref mei1 on end # Management Engine Interface 1 + device ref mei2 off end # Management Engine Interface 2 + device ref me_ide_r off end # Management Engine IDE-R + device ref me_kt off end # Management Engine KT + device ref gbe off end # Intel Gigabit Ethernet + device ref ehci2 on end # USB2 EHCI #2 + device ref hda on end # High Definition Audio + device ref rp1 off end # PCIe Port #1 + device ref rp2 on end # PCIe Port #2 (WLAN) + device ref rp3 on end # PCIe Port #3 (ETH0) + device ref rp4 off end # PCIe Port #4 + device ref rp5 off end # PCIe Port #5 + device ref rp6 off end # PCIe Port #6 + device ref rp7 off end # PCIe Port #7 + device ref rp8 off end # PCIe Port #8 + device ref ehci1 on end # USB2 EHCI #1 + device ref pci_b off end # PCI bridge + device ref lpc on chip ec/compal/ene932 # 60/64 KBC device pnp ff.1 on # dummy address end end end # LPC bridge - device pci 1f.2 on end # SATA Controller 1 - device pci 1f.3 on end # SMBus - device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 on end # Thermal + device ref sata1 on end # SATA Controller 1 + device ref smbus on end # SMBus + device ref sata2 off end # SATA Controller 2 + device ref thermal on end # Thermal end end end diff --git a/src/mainboard/google/stout/devicetree.cb b/src/mainboard/google/stout/devicetree.cb index 7c20a65..c089628 100644 --- a/src/mainboard/google/stout/devicetree.cb +++ b/src/mainboard/google/stout/devicetree.cb @@ -21,8 +21,8 @@ device domain 0 on subsystemid 0x1ae0 0xc000 inherit - device pci 00.0 on end # host bridge - device pci 02.0 on end # vga controller + device ref hb on end # host bridge + device ref igd on end # vga controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH # GPI routing @@ -49,26 +49,26 @@ # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "true" - device pci 14.0 on end # USB 3.0 Controller - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 19.0 off end # Intel Gigabit Ethernet - device pci 1a.0 on end # USB2 EHCI #2 (AUO4, BlueTooth) - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 on end # PCIe Port #1 - device pci 1c.1 on end # PCIe Port #2 (WLAN) - device pci 1c.2 on end # PCIe Port #3 (Card Reader) + device ref xhci on end # USB 3.0 Controller + device ref mei1 on end # Management Engine Interface 1 + device ref mei2 off end # Management Engine Interface 2 + device ref me_ide_r off end # Management Engine IDE-R + device ref me_kt off end # Management Engine KT + device ref gbe off end # Intel Gigabit Ethernet + device ref ehci2 on end # USB2 EHCI #2 (AUO4, BlueTooth) + device ref hda on end # High Definition Audio + device ref rp1 on end # PCIe Port #1 + device ref rp2 on end # PCIe Port #2 (WLAN) + device ref rp3 on end # PCIe Port #3 (Card Reader) register "pcie_aspm[2]" = "0x3" - device pci 1c.3 off end # PCIe Port #4 - device pci 1c.4 off end # PCIe Port #5 - device pci 1c.5 on end # PCIe Port #6 (LAN) - device pci 1c.6 off end # PCIe Port #7 - device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on end # USB2 EHCI #1 (Camera, WLAN, WWAN) - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on + device ref rp4 off end # PCIe Port #4 + device ref rp5 off end # PCIe Port #5 + device ref rp6 on end # PCIe Port #6 (LAN) + device ref rp7 off end # PCIe Port #7 + device ref rp8 off end # PCIe Port #8 + device ref ehci1 on end # USB2 EHCI #1 (Camera, WLAN, WWAN) + device ref pci_b off end # PCI bridge + device ref lpc on chip drivers/pc80/tpm device pnp 0c31.0 on end end @@ -78,10 +78,10 @@ end end end # LPC bridge - device pci 1f.2 on end # SATA Controller 1 (HDD/SSD) - device pci 1f.3 on end # SMBus Controller - device pci 1f.5 off end # SATA Controller 2 (MSATA) - device pci 1f.6 off end # Thermal + device ref sata1 on end # SATA Controller 1 (HDD/SSD) + device ref smbus on end # SMBus Controller + device ref sata2 off end # SATA Controller 2 (MSATA) + device ref thermal off end # Thermal end end end diff --git a/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb b/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb index ce100b4..5738c0d 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb +++ b/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb @@ -9,9 +9,9 @@ device domain 0 on subsystemid 0x103c 0x1495 inherit - device pci 00.0 on end # Host bridge Host bridge - device pci 01.0 on end # PCIe Bridge for discrete graphics - device pci 02.0 on end # Internal graphics VGA controller + device ref hb on end # Host bridge Host bridge + device ref peg10 on end # PCIe Bridge for discrete graphics + device ref igd on end # Internal graphics VGA controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "docking_supported" = "0" @@ -24,24 +24,24 @@ register "spi_lvscc" = "0x2005" register "spi_uvscc" = "0x0" - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 on end # Management Engine KT - device pci 19.0 on end # Intel Gigabit Ethernet - device pci 1a.0 on end # USB2 EHCI #2 - device pci 1b.0 on end # High Definition Audio Audio controller - device pci 1c.0 on end # PCIe Port #1 - device pci 1c.1 off end # PCIe Port #2 - device pci 1c.2 off end # PCIe Port #3 - device pci 1c.3 off end # PCIe Port #4 - device pci 1c.4 on end # PCIe Port #5 - device pci 1c.5 off end # PCIe Port #6 - device pci 1c.6 on end # PCIe Port #7 - device pci 1c.7 on end # PCIe Port #8 - device pci 1d.0 on end # USB2 EHCI #1 - device pci 1e.0 on end # PCI bridge - device pci 1f.0 on # LPC bridge PCI-LPC bridge + device ref mei1 on end # Management Engine Interface 1 + device ref mei2 off end # Management Engine Interface 2 + device ref me_ide_r off end # Management Engine IDE-R + device ref me_kt on end # Management Engine KT + device ref gbe on end # Intel Gigabit Ethernet + device ref ehci2 on end # USB2 EHCI #2 + device ref hda on end # High Definition Audio Audio controller + device ref rp1 on end # PCIe Port #1 + device ref rp2 off end # PCIe Port #2 + device ref rp3 off end # PCIe Port #3 + device ref rp4 off end # PCIe Port #4 + device ref rp5 on end # PCIe Port #5 + device ref rp6 off end # PCIe Port #6 + device ref rp7 on end # PCIe Port #7 + device ref rp8 on end # PCIe Port #8 + device ref ehci1 on end # USB2 EHCI #1 + device ref pci_b on end # PCI bridge + device ref lpc on # LPC bridge PCI-LPC bridge chip superio/common device pnp 2e.ff on # passes SIO base addr to SSDT gen chip superio/nuvoton/npcd378 @@ -146,10 +146,10 @@ device pnp 4e.0 on end # TPM module end end - device pci 1f.2 on end # SATA Controller 1 - device pci 1f.3 on end # SMBus - device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 off end # Thermal + device ref sata1 on end # SATA Controller 1 + device ref smbus on end # SMBus + device ref sata2 off end # SATA Controller 2 + device ref thermal off end # Thermal end end end diff --git a/src/mainboard/hp/snb_ivb_laptops/devicetree.cb b/src/mainboard/hp/snb_ivb_laptops/devicetree.cb index a4d723f..ccf49e8 100644 --- a/src/mainboard/hp/snb_ivb_laptops/devicetree.cb +++ b/src/mainboard/hp/snb_ivb_laptops/devicetree.cb @@ -18,7 +18,7 @@ device domain 0 on - device pci 00.0 on end # Host bridge + device ref hb on end # Host bridge chip southbridge/intel/bd82x6x # Intel Cougar or Panther Point PCH register "pcie_port_coalesce" = "true" @@ -26,24 +26,24 @@ register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0" - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 19.0 on end # Intel Gigabit Ethernet - device pci 1a.0 on end # USB2 EHCI #2 - device pci 1b.0 on end # HD Audio controller - device pci 1d.0 on end # USB2 EHCI #1 - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on # LPC bridge + device ref mei1 on end # Management Engine Interface 1 + device ref mei2 off end # Management Engine Interface 2 + device ref me_ide_r off end # Management Engine IDE-R + device ref me_kt off end # Management Engine KT + device ref gbe on end # Intel Gigabit Ethernet + device ref ehci2 on end # USB2 EHCI #2 + device ref hda on end # HD Audio controller + device ref ehci1 on end # USB2 EHCI #1 + device ref pci_b off end # PCI bridge + device ref lpc on # LPC bridge chip drivers/pc80/tpm device pnp 0c31.0 on end end end - device pci 1f.2 on end # SATA Controller 1 - device pci 1f.3 on end # SMBus - device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 off end # Thermal + device ref sata1 on end # SATA Controller 1 + device ref smbus on end # SMBus + device ref sata2 off end # SATA Controller 2 + device ref thermal off end # Thermal end end end diff --git a/src/mainboard/hp/z220_series/devicetree.cb b/src/mainboard/hp/z220_series/devicetree.cb index 6794b62..40e49df 100644 --- a/src/mainboard/hp/z220_series/devicetree.cb +++ b/src/mainboard/hp/z220_series/devicetree.cb @@ -9,10 +9,10 @@ device domain 0 on subsystemid 0x103c 0x1791 inherit - device pci 00.0 on end # Host bridge Host bridge - device pci 01.0 on end # PCIe Bridge for discrete graphics - device pci 02.0 on end # Internal graphics VGA controller - device pci 06.0 off end # Extra x4 port on north bridge + device ref hb on end # Host bridge Host bridge + device ref peg10 on end # PCIe Bridge for discrete graphics + device ref igd on end # Internal graphics VGA controller + device ref peg60 off end # Extra x4 port on north bridge chip southbridge/intel/bd82x6x # Intel Series 7 PCH register "docking_supported" = "0" @@ -27,25 +27,25 @@ register "xhci_switchable_ports" = "0x0000000f" register "xhci_overcurrent_mapping" = "0x0000000f" - device pci 14.0 on end # xHCI - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 on end # Management Engine KT - device pci 19.0 on end # Intel Gigabit Ethernet - device pci 1a.0 on end # USB2 EHCI #2 - device pci 1b.0 on end # High Definition Audio Audio controller - device pci 1c.0 on end # PCIe Port #1 - device pci 1c.1 off end # PCIe Port #2 - device pci 1c.2 off end # PCIe Port #3 - device pci 1c.3 off end # PCIe Port #4 - device pci 1c.4 on end # PCIe Port #5 - device pci 1c.5 off end # PCIe Port #6 - device pci 1c.6 off end # PCIe Port #7 - device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on end # USB2 EHCI #1 - device pci 1e.0 on end # PCI bridge - device pci 1f.0 on # LPC bridge PCI-LPC bridge + device ref xhci on end # xHCI + device ref mei1 on end # Management Engine Interface 1 + device ref mei2 off end # Management Engine Interface 2 + device ref me_ide_r off end # Management Engine IDE-R + device ref me_kt on end # Management Engine KT + device ref gbe on end # Intel Gigabit Ethernet + device ref ehci2 on end # USB2 EHCI #2 + device ref hda on end # High Definition Audio Audio controller + device ref rp1 on end # PCIe Port #1 + device ref rp2 off end # PCIe Port #2 + device ref rp3 off end # PCIe Port #3 + device ref rp4 off end # PCIe Port #4 + device ref rp5 on end # PCIe Port #5 + device ref rp6 off end # PCIe Port #6 + device ref rp7 off end # PCIe Port #7 + device ref rp8 off end # PCIe Port #8 + device ref ehci1 on end # USB2 EHCI #1 + device ref pci_b on end # PCI bridge + device ref lpc on # LPC bridge PCI-LPC bridge chip superio/common device pnp 2e.ff on # passes SIO base addr to SSDT gen chip superio/nuvoton/npcd378 @@ -150,10 +150,10 @@ device pnp 4e.0 on end # TPM module end end - device pci 1f.2 on end # SATA Controller 1 - device pci 1f.3 on end # SMBus - device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 off end # Thermal + device ref sata1 on end # SATA Controller 1 + device ref smbus on end # SMBus + device ref sata2 off end # SATA Controller 2 + device ref thermal off end # Thermal end end end diff --git a/src/mainboard/intel/dcp847ske/devicetree.cb b/src/mainboard/intel/dcp847ske/devicetree.cb index 5400af7..867c9ce 100644 --- a/src/mainboard/intel/dcp847ske/devicetree.cb +++ b/src/mainboard/intel/dcp847ske/devicetree.cb @@ -12,9 +12,9 @@ register "gpu_dp_b_hotplug" = "0x06" device domain 0 on - device pci 00.0 on end # Host bridge - device pci 01.0 off end # PCIe Bridge for discrete graphics - device pci 02.0 on end # Internal graphics VGA controller + device ref hb on end # Host bridge + device ref peg10 off end # PCIe Bridge for discrete graphics + device ref igd on end # Internal graphics VGA controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "sata_port_map" = "0x1" @@ -23,25 +23,25 @@ register "gen1_dec" = "0x00fc0a01" # SuperIO @0xa00-0xaff - device pci 14.0 off end # USB xHCI - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 19.0 on end # Intel Gigabit Ethernet - device pci 1a.0 off end # USB2 EHCI #2 - device pci 1b.0 on end # HD Audio controller - device pci 1c.0 on end # PCIe Port #1 (unused) - device pci 1c.1 on end # PCIe Port #2 (full-length mPCIe/mSATA) - device pci 1c.2 on end # PCIe Port #3 (half-length mPCIe) - device pci 1c.3 off end # PCIe Port #4 - device pci 1c.4 off end # PCIe Port #5 - device pci 1c.5 off end # PCIe Port #6 - device pci 1c.6 off end # PCIe Port #7 - device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on end # USB2 EHCI #1 - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on # LPC bridge + device ref xhci off end # USB xHCI + device ref mei1 on end # Management Engine Interface 1 + device ref mei2 off end # Management Engine Interface 2 + device ref me_ide_r off end # Management Engine IDE-R + device ref me_kt off end # Management Engine KT + device ref gbe on end # Intel Gigabit Ethernet + device ref ehci2 off end # USB2 EHCI #2 + device ref hda on end # HD Audio controller + device ref rp1 on end # PCIe Port #1 (unused) + device ref rp2 on end # PCIe Port #2 (full-length mPCIe/mSATA) + device ref rp3 on end # PCIe Port #3 (half-length mPCIe) + device ref rp4 off end # PCIe Port #4 + device ref rp5 off end # PCIe Port #5 + device ref rp6 off end # PCIe Port #6 + device ref rp7 off end # PCIe Port #7 + device ref rp8 off end # PCIe Port #8 + device ref ehci1 on end # USB2 EHCI #1 + device ref pci_b off end # PCI bridge + device ref lpc on # LPC bridge chip superio/nuvoton/nct6776 device pnp 4e.0 off end # Floppy device pnp 4e.1 off end # Parallel port @@ -82,10 +82,10 @@ device pnp 4e.17 off end # GPIOA end end - device pci 1f.2 on end # SATA Controller 1 - device pci 1f.3 on end # SMBus - device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 off end # Thermal + device ref sata1 on end # SATA Controller 1 + device ref smbus on end # SMBus + device ref sata2 off end # SATA Controller 2 + device ref thermal off end # Thermal end end end diff --git a/src/mainboard/intel/emeraldlake2/devicetree.cb b/src/mainboard/intel/emeraldlake2/devicetree.cb index 2eeb745..a598d46 100644 --- a/src/mainboard/intel/emeraldlake2/devicetree.cb +++ b/src/mainboard/intel/emeraldlake2/devicetree.cb @@ -20,8 +20,8 @@ end device domain 0 on - device pci 00.0 on end # host bridge - device pci 02.0 on end # vga controller + device ref hb on end # host bridge + device ref igd on end # vga controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH # GPI routing @@ -41,28 +41,28 @@ # SuperIO range is 0x700-0x73f register "gen3_dec" = "0x003c0701" - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 19.0 off end # Intel Gigabit Ethernet - device pci 1a.0 on end # USB2 EHCI #2 - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 on end # PCIe Port #1 (WLAN) - device pci 1c.1 off end # PCIe Port #2 - device pci 1c.2 on end # PCIe Port #3 (Debug) - device pci 1c.3 on end # PCIe Port #4 (LAN) - device pci 1c.4 off end # PCIe Port #5 - device pci 1c.5 off end # PCIe Port #6 - device pci 1c.6 off end # PCIe Port #7 - device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on end # USB2 EHCI #1 - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on end # LPC bridge - device pci 1f.2 on end # SATA Controller 1 - device pci 1f.3 on end # SMBus - device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 on end # Thermal + device ref mei1 on end # Management Engine Interface 1 + device ref mei2 off end # Management Engine Interface 2 + device ref me_ide_r off end # Management Engine IDE-R + device ref me_kt off end # Management Engine KT + device ref gbe off end # Intel Gigabit Ethernet + device ref ehci2 on end # USB2 EHCI #2 + device ref hda on end # High Definition Audio + device ref rp1 on end # PCIe Port #1 (WLAN) + device ref rp2 off end # PCIe Port #2 + device ref rp3 on end # PCIe Port #3 (Debug) + device ref rp4 on end # PCIe Port #4 (LAN) + device ref rp5 off end # PCIe Port #5 + device ref rp6 off end # PCIe Port #6 + device ref rp7 off end # PCIe Port #7 + device ref rp8 off end # PCIe Port #8 + device ref ehci1 on end # USB2 EHCI #1 + device ref pci_b off end # PCI bridge + device ref lpc on end # LPC bridge + device ref sata1 on end # SATA Controller 1 + device ref smbus on end # SMBus + device ref sata2 off end # SATA Controller 2 + device ref thermal on end # Thermal end end end diff --git a/src/mainboard/kontron/ktqm77/devicetree.cb b/src/mainboard/kontron/ktqm77/devicetree.cb index bf87661..ced2b13 100644 --- a/src/mainboard/kontron/ktqm77/devicetree.cb +++ b/src/mainboard/kontron/ktqm77/devicetree.cb @@ -10,9 +10,9 @@ end device domain 0 on - device pci 00.0 on end # host bridge - device pci 01.0 on end # PCIe Bridge x16 - device pci 02.0 on end # vga controller + device ref hb on end # host bridge + device ref peg10 on end # PCIe Bridge x16 + device ref igd on end # vga controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH # Enable all SATA ports 0-5 @@ -32,29 +32,29 @@ register "xhci_switchable_ports" = "0x0f" register "superspeed_capable_ports" = "0x0f" - device pci 14.0 on end # USB 3.0 Controller - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 19.0 on end # Intel Gigabit Ethernet - device pci 1a.0 on end # USB2 EHCI #2 - device pci 1b.0 on end # High Definition Audio + device ref xhci on end # USB 3.0 Controller + device ref mei1 on end # Management Engine Interface 1 + device ref mei2 off end # Management Engine Interface 2 + device ref me_ide_r off end # Management Engine IDE-R + device ref me_kt off end # Management Engine KT + device ref gbe on end # Intel Gigabit Ethernet + device ref ehci2 on end # USB2 EHCI #2 + device ref hda on end # High Definition Audio # Disabling 1c.0 might break IRQ settings as it enables port coalescing # There are two mini PCIe x1 sockets, so one PCIe port is unrouted - device pci 1c.0 on end # PCIe Port #1 mini PCIe x1? - device pci 1c.1 on end # PCIe Port #2 mini PCIe x1? - device pci 1c.2 on end # PCIe Port #3 second Ethernet NIC - device pci 1c.3 on end # PCIe Port #4 third Ethernet NIC - device pci 1c.4 on end # PCIe Port #5 first Ethernet PHY - device pci 1c.5 on end # PCIe Port #6 FireWire - device pci 1c.6 on end # PCIe Port #7 PCIe x1 - device pci 1c.7 on end # PCIe Port #8 mini PCIe x1? + device ref rp1 on end # PCIe Port #1 mini PCIe x1? + device ref rp2 on end # PCIe Port #2 mini PCIe x1? + device ref rp3 on end # PCIe Port #3 second Ethernet NIC + device ref rp4 on end # PCIe Port #4 third Ethernet NIC + device ref rp5 on end # PCIe Port #5 first Ethernet PHY + device ref rp6 on end # PCIe Port #6 FireWire + device ref rp7 on end # PCIe Port #7 PCIe x1 + device ref rp8 on end # PCIe Port #8 mini PCIe x1? - device pci 1d.0 on end # USB2 EHCI #1 - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on #LPC bridge + device ref ehci1 on end # USB2 EHCI #1 + device ref pci_b off end # PCI bridge + device ref lpc on #LPC bridge chip superio/winbond/w83627dhg device pnp 2e.0 off # Floppy end @@ -134,10 +134,10 @@ end #ec/kontron/it8516e # TODO: TPM on 4e end # LPC bridge - device pci 1f.2 on end # SATA Controller 1 - device pci 1f.3 on end # SMBus - device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 off end # Thermal + device ref sata1 on end # SATA Controller 1 + device ref smbus on end # SMBus + device ref sata2 off end # SATA Controller 2 + device ref thermal off end # Thermal end end end diff --git a/src/mainboard/lenovo/l520/devicetree.cb b/src/mainboard/lenovo/l520/devicetree.cb index 9e56e79..72cf44a 100644 --- a/src/mainboard/lenovo/l520/devicetree.cb +++ b/src/mainboard/lenovo/l520/devicetree.cb @@ -15,9 +15,9 @@ device domain 0 on subsystemid 0x17aa 0x21dd inherit - device pci 00.0 on end # Host bridge - device pci 01.0 on end # PCIe Bridge for discrete graphics - device pci 02.0 on end # Internal graphics VGA controller + device ref hb on end # Host bridge + device ref peg10 on end # PCIe Bridge for discrete graphics + device ref igd on end # Internal graphics VGA controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "docking_supported" = "1" @@ -35,24 +35,24 @@ register "spi_uvscc" = "0" register "spi_lvscc" = "0x2005" - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 19.0 off end # Intel Gigabit Ethernet - device pci 1a.0 on end # USB2 EHCI #2 - device pci 1b.0 on end # High Definition Audio Audio controller - device pci 1c.0 on end # PCIe Port #1 - device pci 1c.1 on end # PCIe Port #2 - device pci 1c.2 on end # PCIe Port #3 - device pci 1c.3 on end # PCIe Port #4 - device pci 1c.4 on end # PCIe Port #5 - device pci 1c.5 on end # PCIe Port #6 - device pci 1c.6 off end # PCIe Port #7 - device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on end # USB2 EHCI #1 - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on # LPC bridge PCI-LPC bridge + device ref mei1 on end # Management Engine Interface 1 + device ref mei2 off end # Management Engine Interface 2 + device ref me_ide_r off end # Management Engine IDE-R + device ref me_kt off end # Management Engine KT + device ref gbe off end # Intel Gigabit Ethernet + device ref ehci2 on end # USB2 EHCI #2 + device ref hda on end # High Definition Audio Audio controller + device ref rp1 on end # PCIe Port #1 + device ref rp2 on end # PCIe Port #2 + device ref rp3 on end # PCIe Port #3 + device ref rp4 on end # PCIe Port #4 + device ref rp5 on end # PCIe Port #5 + device ref rp6 on end # PCIe Port #6 + device ref rp7 off end # PCIe Port #7 + device ref rp8 off end # PCIe Port #8 + device ref ehci1 on end # USB2 EHCI #1 + device ref pci_b off end # PCI bridge + device ref lpc on # LPC bridge PCI-LPC bridge chip ec/lenovo/pmh7 register "backlight_enable" = "0x01" register "dock_event_enable" = "0x01" @@ -89,8 +89,8 @@ end end end # LPC bridge - device pci 1f.2 on end # SATA Controller 1 - device pci 1f.3 on # SMBus + device ref sata1 on end # SATA Controller 1 + device ref smbus on # SMBus chip drivers/i2c/at24rf08c # eeprom, 8 virtual devices, same chip device i2c 54 on end device i2c 55 on end @@ -102,8 +102,8 @@ device i2c 5f on end end end # SMBus - device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 off end # Thermal + device ref sata2 off end # SATA Controller 2 + device ref thermal off end # Thermal end end end diff --git a/src/mainboard/lenovo/s230u/devicetree.cb b/src/mainboard/lenovo/s230u/devicetree.cb index 16e1004..0309284 100644 --- a/src/mainboard/lenovo/s230u/devicetree.cb +++ b/src/mainboard/lenovo/s230u/devicetree.cb @@ -15,9 +15,9 @@ device domain 0 on subsystemid 0x17aa 0x2205 inherit - device pci 00.0 on end # Host bridge Host bridge - device pci 01.0 off end # PCIe Bridge for discrete graphics - device pci 02.0 on end # Internal graphics VGA controller + device ref hb on end # Host bridge Host bridge + device ref peg10 off end # PCIe Bridge for discrete graphics + device ref igd on end # Internal graphics VGA controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "docking_supported" = "1" @@ -38,31 +38,31 @@ register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" - device pci 14.0 on end # USB 3.0 Controller - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 19.0 off end # Intel Gigabit Ethernet - device pci 1a.0 on end # USB2 EHCI #2 - device pci 1b.0 on end # High Definition Audio Audio controller - device pci 1c.0 on end # PCIe Port #1 - device pci 1c.1 on end # PCIe Port #2 - device pci 1c.2 off end # PCIe Port #3 - device pci 1c.3 on end # PCIe Port #4 - device pci 1c.4 off end # PCIe Port #5 - device pci 1c.5 off end # PCIe Port #6 - device pci 1c.6 off end # PCIe Port #7 - device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on end # USB2 EHCI #1 - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on # LPC bridge PCI-LPC bridge + device ref xhci on end # USB 3.0 Controller + device ref mei1 on end # Management Engine Interface 1 + device ref mei2 off end # Management Engine Interface 2 + device ref me_ide_r off end # Management Engine IDE-R + device ref me_kt off end # Management Engine KT + device ref gbe off end # Intel Gigabit Ethernet + device ref ehci2 on end # USB2 EHCI #2 + device ref hda on end # High Definition Audio Audio controller + device ref rp1 on end # PCIe Port #1 + device ref rp2 on end # PCIe Port #2 + device ref rp3 off end # PCIe Port #3 + device ref rp4 on end # PCIe Port #4 + device ref rp5 off end # PCIe Port #5 + device ref rp6 off end # PCIe Port #6 + device ref rp7 off end # PCIe Port #7 + device ref rp8 off end # PCIe Port #8 + device ref ehci1 on end # USB2 EHCI #1 + device ref pci_b off end # PCI bridge + device ref lpc on # LPC bridge PCI-LPC bridge chip drivers/pc80/tpm device pnp 0c31.0 on end end end - device pci 1f.2 on end # SATA Controller 1 - device pci 1f.3 on # SMBus + device ref sata1 on end # SATA Controller 1 + device ref smbus on # SMBus chip drivers/i2c/at24rf08c # eeprom, 8 virtual devices, same chip device i2c 54 on end device i2c 55 on end @@ -74,8 +74,8 @@ device i2c 5f on end end end - device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 off end # Thermal + device ref sata2 off end # SATA Controller 2 + device ref thermal off end # Thermal end end end diff --git a/src/mainboard/lenovo/t420/devicetree.cb b/src/mainboard/lenovo/t420/devicetree.cb index b764a83..6b768a7 100644 --- a/src/mainboard/lenovo/t420/devicetree.cb +++ b/src/mainboard/lenovo/t420/devicetree.cb @@ -18,9 +18,9 @@ device domain 0 on subsystemid 0x17aa 0x21ce inherit - device pci 00.0 on end # host bridge - device pci 01.0 on end # PCIe Bridge for discrete graphics - device pci 02.0 on end # Integrated Graphics Controller + device ref hb on end # host bridge + device ref peg10 on end # PCIe Bridge for discrete graphics + device ref igd on end # Integrated Graphics Controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH # GPI routing @@ -49,32 +49,32 @@ register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 19.0 on end # Intel Gigabit Ethernet - device pci 1a.0 on end # USB Enhanced Host Controller #2 - device pci 1b.0 on end # High Definition Audio Controller - device pci 1c.0 off end # PCIe Port #1 - device pci 1c.1 on end # PCIe Port #2 Integrated Wireless LAN - device pci 1c.2 off end # PCIe Port #3 - device pci 1c.3 on + device ref mei1 on end # Management Engine Interface 1 + device ref mei2 off end # Management Engine Interface 2 + device ref me_ide_r off end # Management Engine IDE-R + device ref me_kt off end # Management Engine KT + device ref gbe on end # Intel Gigabit Ethernet + device ref ehci2 on end # USB Enhanced Host Controller #2 + device ref hda on end # High Definition Audio Controller + device ref rp1 off end # PCIe Port #1 + device ref rp2 on end # PCIe Port #2 Integrated Wireless LAN + device ref rp3 off end # PCIe Port #3 + device ref rp4 on smbios_slot_desc "7" "3" "ExpressCard Slot" "8" end # PCIe Port #4 ExpressCard - device pci 1c.4 on + device ref rp5 on chip drivers/ricoh/rce822 register "sdwppol" = "1" register "disable_mask" = "0x87" device pci 00.0 on end end end # PCIe Port #5 (Ricoh SD & FW) - device pci 1c.5 off end # PCIe Port #6 Intel Gigabit Ethernet PHY (not PCIe) - device pci 1c.6 off end # PCIe Port #7 - device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on end # USB Enhanced Host Controller #1 - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on + device ref rp6 off end # PCIe Port #6 Intel Gigabit Ethernet PHY (not PCIe) + device ref rp7 off end # PCIe Port #7 + device ref rp8 off end # PCIe Port #8 + device ref ehci1 on end # USB Enhanced Host Controller #1 + device ref pci_b off end # PCI bridge + device ref lpc on chip ec/lenovo/pmh7 device pnp ff.1 on end # dummy register "backlight_enable" = "0x01" @@ -136,8 +136,8 @@ register "has_thinker1" = "1" end end # LPC Controller - device pci 1f.2 on end # 6 port SATA AHCI Controller - device pci 1f.3 on + device ref sata1 on end # 6 port SATA AHCI Controller + device ref smbus on # eeprom, 8 virtual devices, same chip chip drivers/i2c/at24rf08c device i2c 54 on end @@ -150,8 +150,8 @@ device i2c 5f on end end end # SMBus Controller - device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 on end # Thermal + device ref sata2 off end # SATA Controller 2 + device ref thermal on end # Thermal end end end diff --git a/src/mainboard/lenovo/t420s/devicetree.cb b/src/mainboard/lenovo/t420s/devicetree.cb index 92c9085..acfd228 100644 --- a/src/mainboard/lenovo/t420s/devicetree.cb +++ b/src/mainboard/lenovo/t420s/devicetree.cb @@ -18,9 +18,9 @@ device domain 0 on subsystemid 0x17aa 0x21d2 inherit - device pci 00.0 on end # host bridge - device pci 01.0 on end # NVIDIA Corporation GF119M [NVS 4200M] - device pci 02.0 on + device ref hb on end # host bridge + device ref peg10 on end # NVIDIA Corporation GF119M [NVS 4200M] + device ref igd on subsystemid 0x17aa 0x21d3 end # Integrated Graphics Controller @@ -51,28 +51,28 @@ register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 19.0 on + device ref mei1 on end # Management Engine Interface 1 + device ref mei2 off end # Management Engine Interface 2 + device ref me_ide_r off end # Management Engine IDE-R + device ref me_kt off end # Management Engine KT + device ref gbe on subsystemid 0x17aa 0x21ce end # Intel Gigabit Ethernet - device pci 1a.0 on end # USB Enhanced Host Controller #2 - device pci 1b.0 on end # High Definition Audio Controller - device pci 1c.0 off end # PCIe Port #1 - device pci 1c.1 on end # PCIe Port #2 Integrated Wireless LAN - device pci 1c.2 off end # PCIe Port #3 - device pci 1c.3 on + device ref ehci2 on end # USB Enhanced Host Controller #2 + device ref hda on end # High Definition Audio Controller + device ref rp1 off end # PCIe Port #1 + device ref rp2 on end # PCIe Port #2 Integrated Wireless LAN + device ref rp3 off end # PCIe Port #3 + device ref rp4 on smbios_slot_desc "7" "3" "ExpressCard Slot" "8" end # PCIe Port #4 ExpressCard - device pci 1c.4 on end # PCIe Port #5 NEC Corporation uPD720200A USB 3.0 Host Controller - device pci 1c.5 off end # PCIe Port #6 Intel Gigabit Ethernet PHY (not PCIe) - device pci 1c.6 off end # PCIe Port #7 - device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on end # USB Enhanced Host Controller #1 - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on + device ref rp5 on end # PCIe Port #5 NEC Corporation uPD720200A USB 3.0 Host Controller + device ref rp6 off end # PCIe Port #6 Intel Gigabit Ethernet PHY (not PCIe) + device ref rp7 off end # PCIe Port #7 + device ref rp8 off end # PCIe Port #8 + device ref ehci1 on end # USB Enhanced Host Controller #1 + device ref pci_b off end # PCI bridge + device ref lpc on chip ec/lenovo/pmh7 device pnp ff.1 on end # dummy register "backlight_enable" = "0x01" @@ -134,8 +134,8 @@ register "has_thinker1" = "1" end end # LPC Controller - device pci 1f.2 on end # 6 port SATA AHCI Controller - device pci 1f.3 on + device ref sata1 on end # 6 port SATA AHCI Controller + device ref smbus on # eeprom, 8 virtual devices, same chip chip drivers/i2c/at24rf08c device i2c 54 on end @@ -148,8 +148,8 @@ device i2c 5f on end end end # SMBus Controller - device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 on end # Thermal + device ref sata2 off end # SATA Controller 2 + device ref thermal on end # Thermal end end end diff --git a/src/mainboard/lenovo/t430/devicetree.cb b/src/mainboard/lenovo/t430/devicetree.cb index 8b15c84..9be2ec5 100644 --- a/src/mainboard/lenovo/t430/devicetree.cb +++ b/src/mainboard/lenovo/t430/devicetree.cb @@ -36,33 +36,33 @@ register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" - device pci 14.0 on end # USB 3.0 Controller - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 19.0 on end # Intel Gigabit Ethernet - device pci 1a.0 on end # USB2 EHCI #2 - device pci 1b.0 on end # High Definition Audio Audio controller - device pci 1c.0 on # PCIe Port #1 + device ref xhci on end # USB 3.0 Controller + device ref mei1 on end # Management Engine Interface 1 + device ref mei2 off end # Management Engine Interface 2 + device ref me_ide_r off end # Management Engine IDE-R + device ref me_kt off end # Management Engine KT + device ref gbe on end # Intel Gigabit Ethernet + device ref ehci2 on end # USB2 EHCI #2 + device ref hda on end # High Definition Audio Audio controller + device ref rp1 on # PCIe Port #1 chip drivers/ricoh/rce822 # Ricoh cardreader register "disable_mask" = "0x87" register "sdwppol" = "1" device pci 00.0 on end # Ricoh SD card reader end end - device pci 1c.1 on end # PCIe Port #2 - device pci 1c.2 on # PCIe Port #3 + device ref rp2 on end # PCIe Port #2 + device ref rp3 on # PCIe Port #3 smbios_slot_desc "7" "3" "ExpressCard Slot" "8" end - device pci 1c.3 off end # PCIe Port #4 - device pci 1c.4 off end # PCIe Port #5 - device pci 1c.5 off end # PCIe Port #6 - device pci 1c.6 off end # PCIe Port #7 - device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on end # USB2 EHCI #1 - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on # LPC bridge PCI-LPC bridge + device ref rp4 off end # PCIe Port #4 + device ref rp5 off end # PCIe Port #5 + device ref rp6 off end # PCIe Port #6 + device ref rp7 off end # PCIe Port #7 + device ref rp8 off end # PCIe Port #8 + device ref ehci1 on end # USB2 EHCI #1 + device ref pci_b off end # PCI bridge + device ref lpc on # LPC bridge PCI-LPC bridge chip ec/lenovo/pmh7 register "backlight_enable" = "0x01" register "dock_event_enable" = "0x01" @@ -125,8 +125,8 @@ device pnp 0c31.0 on end end end - device pci 1f.2 on end # SATA Controller 1 - device pci 1f.3 on # SMBus + device ref sata1 on end # SATA Controller 1 + device ref smbus on # SMBus chip drivers/i2c/at24rf08c # eeprom, 8 virtual devices, same chip device i2c 54 on end device i2c 55 on end @@ -138,12 +138,12 @@ device i2c 5f on end end end - device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 off end # Thermal + device ref sata2 off end # SATA Controller 2 + device ref thermal off end # Thermal end - device pci 00.0 on end # Host bridge Host bridge - device pci 01.0 on end # PCIe Bridge for discrete graphics - device pci 02.0 on end # Internal graphics VGA controller - device pci 04.0 off end # Signal processing controller + device ref hb on end # Host bridge Host bridge + device ref peg10 on end # PCIe Bridge for discrete graphics + device ref igd on end # Internal graphics VGA controller + device ref dev4 off end # Signal processing controller end end diff --git a/src/mainboard/lenovo/t430s/devicetree.cb b/src/mainboard/lenovo/t430s/devicetree.cb index 9148892..198c463 100644 --- a/src/mainboard/lenovo/t430s/devicetree.cb +++ b/src/mainboard/lenovo/t430s/devicetree.cb @@ -17,9 +17,9 @@ device domain 0 on subsystemid 0x17aa 0x21fb inherit - device pci 00.0 on end # host bridge - device pci 01.0 on end # PCIe Bridge for discrete graphics - device pci 02.0 on end # Integrated Graphics Controller + device ref hb on end # host bridge + device ref peg10 on end # PCIe Bridge for discrete graphics + device ref igd on end # Integrated Graphics Controller chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH # GPI routing @@ -52,29 +52,29 @@ register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" - device pci 14.0 on end # USB 3.0 Controller - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 19.0 on + device ref xhci on end # USB 3.0 Controller + device ref mei1 on end # Management Engine Interface 1 + device ref mei2 off end # Management Engine Interface 2 + device ref me_ide_r off end # Management Engine IDE-R + device ref me_kt off end # Management Engine KT + device ref gbe on subsystemid 0x17aa 0x21f3 end # Intel Gigabit Ethernet - device pci 1a.0 on end # USB Enhanced Host Controller #2 - device pci 1b.0 on end # High Definition Audio Controller - device pci 1c.0 off end # PCIe Port #1 - device pci 1c.1 on end # PCIe Port #2 Integrated Wireless LAN - device pci 1c.2 on + device ref ehci2 on end # USB Enhanced Host Controller #2 + device ref hda on end # High Definition Audio Controller + device ref rp1 off end # PCIe Port #1 + device ref rp2 on end # PCIe Port #2 Integrated Wireless LAN + device ref rp3 on smbios_slot_desc "7" "3" "ExpressCard Slot" "8" end # PCIe Port #3 ExpressCard - device pci 1c.3 off end # PCIe Port #4 - device pci 1c.4 off end # PCIe Port #5 - device pci 1c.5 off end # PCIe Port #6 Intel Gigabit Ethernet PHY (not PCIe) - device pci 1c.6 off end # PCIe Port #7 - device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on end # USB Enhanced Host Controller #1 - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on + device ref rp4 off end # PCIe Port #4 + device ref rp5 off end # PCIe Port #5 + device ref rp6 off end # PCIe Port #6 Intel Gigabit Ethernet PHY (not PCIe) + device ref rp7 off end # PCIe Port #7 + device ref rp8 off end # PCIe Port #8 + device ref ehci1 on end # USB Enhanced Host Controller #1 + device ref pci_b off end # PCI bridge + device ref lpc on chip ec/lenovo/pmh7 device pnp ff.1 on end # dummy register "backlight_enable" = "0x01" @@ -118,8 +118,8 @@ register "evente_enable" = "0x0d" end end # LPC Controller - device pci 1f.2 on end # 6 port SATA AHCI Controller - device pci 1f.3 on + device ref sata1 on end # 6 port SATA AHCI Controller + device ref smbus on # eeprom, 8 virtual devices, same chip chip drivers/i2c/at24rf08c device i2c 54 on end @@ -132,8 +132,8 @@ device i2c 5f on end end end # SMBus Controller - device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 on end # Thermal + device ref sata2 off end # SATA Controller 2 + device ref thermal on end # Thermal end end end diff --git a/src/mainboard/lenovo/t520/devicetree.cb b/src/mainboard/lenovo/t520/devicetree.cb index 9588af2..ed67657 100644 --- a/src/mainboard/lenovo/t520/devicetree.cb +++ b/src/mainboard/lenovo/t520/devicetree.cb @@ -18,9 +18,9 @@ device domain 0 on subsystemid 0x17aa 0x21cf inherit - device pci 00.0 on end # host bridge - device pci 01.0 on end # NVIDIA Corporation GF119M [NVS 4200M] - device pci 02.0 on + device ref hb on end # host bridge + device ref peg10 on end # NVIDIA Corporation GF119M [NVS 4200M] + device ref igd on subsystemid 0x17aa 0x21d1 end # vga controller @@ -50,28 +50,28 @@ register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end - device pci 16.2 off end - device pci 16.3 off end - device pci 19.0 on # Intel Gigabit Ethernet + device ref mei1 on end # Management Engine Interface 1 + device ref mei2 off end + device ref me_ide_r off end + device ref me_kt off end + device ref gbe on # Intel Gigabit Ethernet subsystemid 0x17aa 0x21ce end - device pci 1a.0 on end # USB2 EHCI #2 - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 off end # PCIe Port #1 - device pci 1c.1 on end # PCIe Port #2 Integrated Wireless LAN - device pci 1c.2 off end # PCIe Port #3 - device pci 1c.3 on + device ref ehci2 on end # USB2 EHCI #2 + device ref hda on end # High Definition Audio + device ref rp1 off end # PCIe Port #1 + device ref rp2 on end # PCIe Port #2 Integrated Wireless LAN + device ref rp3 off end # PCIe Port #3 + device ref rp4 on smbios_slot_desc "7" "3" "ExpressCard Slot" "8" end # PCIe Port #4 Express Card - device pci 1c.4 on end # PCIe Port #5 MMC/SDXC + IEEE1394 - device pci 1c.5 off end # PCIe Port #6 Intel Ethernet PHY - device pci 1c.6 off end # PCIe Port #7 - device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on end # USB2 EHCI #1 + device ref rp5 on end # PCIe Port #5 MMC/SDXC + IEEE1394 + device ref rp6 off end # PCIe Port #6 Intel Ethernet PHY + device ref rp7 off end # PCIe Port #7 + device ref rp8 off end # PCIe Port #8 + device ref ehci1 on end # USB2 EHCI #1 - device pci 1f.0 on #LPC bridge + device ref lpc on #LPC bridge chip ec/lenovo/pmh7 device pnp ff.1 on end # dummy register "backlight_enable" = "0x01" @@ -131,8 +131,8 @@ register "has_thinker1" = "1" end end # LPC bridge - device pci 1f.2 on end # SATA Controller 1 - device pci 1f.3 on # SMBUS controller + device ref sata1 on end # SATA Controller 1 + device ref smbus on # SMBUS controller # eeprom, 8 virtual devices, same chip chip drivers/i2c/at24rf08c device i2c 54 on end diff --git a/src/mainboard/lenovo/t530/devicetree.cb b/src/mainboard/lenovo/t530/devicetree.cb index a274a67..276ed70 100644 --- a/src/mainboard/lenovo/t530/devicetree.cb +++ b/src/mainboard/lenovo/t530/devicetree.cb @@ -18,9 +18,9 @@ device domain 0 on subsystemid 0x17aa 0x21f6 inherit - device pci 00.0 on end # Host bridge - device pci 01.0 on end # PCIe bridge for discrete graphics - device pci 02.0 on end # Internal graphics VGA controller + device ref hb on end # Host bridge + device ref peg10 on end # PCIe bridge for discrete graphics + device ref igd on end # Internal graphics VGA controller chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH # GPI routing @@ -53,29 +53,29 @@ register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" - device pci 14.0 on end # USB 3.0 Controller - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 19.0 on # Intel Gigabit Ethernet + device ref xhci on end # USB 3.0 Controller + device ref mei1 on end # Management Engine Interface 1 + device ref mei2 off end # Management Engine Interface 2 + device ref me_ide_r off end # Management Engine IDE-R + device ref me_kt off end # Management Engine KT + device ref gbe on # Intel Gigabit Ethernet subsystemid 0x17aa 0x21f3 end - device pci 1a.0 on end # USB2 EHCI #2 - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 on end # PCIe Port #1 - device pci 1c.1 on end # PCIe Port #2 - device pci 1c.2 on # PCIe Port #3 + device ref ehci2 on end # USB2 EHCI #2 + device ref hda on end # High Definition Audio + device ref rp1 on end # PCIe Port #1 + device ref rp2 on end # PCIe Port #2 + device ref rp3 on # PCIe Port #3 smbios_slot_desc "7" "3" "ExpressCard Slot" "8" end - device pci 1c.3 off end # PCIe Port #4 - device pci 1c.4 off end # PCIe Port #5 - device pci 1c.5 off end # PCIe Port #6 - device pci 1c.6 off end # PCIe Port #7 - device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on end # USB2 EHCI #1 - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on # PCI-LPC bridge + device ref rp4 off end # PCIe Port #4 + device ref rp5 off end # PCIe Port #5 + device ref rp6 off end # PCIe Port #6 + device ref rp7 off end # PCIe Port #7 + device ref rp8 off end # PCIe Port #8 + device ref ehci1 on end # USB2 EHCI #1 + device ref pci_b off end # PCI bridge + device ref lpc on # PCI-LPC bridge chip ec/lenovo/pmh7 device pnp ff.1 on end # dummy register "backlight_enable" = "0x01" @@ -137,8 +137,8 @@ register "has_thinker1" = "1" end end - device pci 1f.2 on end # SATA Controller 1 - device pci 1f.3 on # SMBus + device ref sata1 on end # SATA Controller 1 + device ref smbus on # SMBus # eeprom, 8 virtual devices, same chip chip drivers/i2c/at24rf08c device i2c 54 on end @@ -151,8 +151,8 @@ device i2c 5f on end end end - device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 on end # Thermal + device ref sata2 off end # SATA Controller 2 + device ref thermal on end # Thermal end end end diff --git a/src/mainboard/lenovo/x131e/devicetree.cb b/src/mainboard/lenovo/x131e/devicetree.cb index a0de163..456ed78 100644 --- a/src/mainboard/lenovo/x131e/devicetree.cb +++ b/src/mainboard/lenovo/x131e/devicetree.cb @@ -17,10 +17,10 @@ device domain 0 on subsystemid 0x17aa 0x21fe inherit - device pci 00.0 on end # Host bridge - device pci 01.0 off end # PCIe Bridge for discrete graphics - device pci 02.0 on end # Internal graphics VGA controller - device pci 04.0 off end # Signal processing controller + device ref hb on end # Host bridge + device ref peg10 off end # PCIe Bridge for discrete graphics + device ref igd on end # Internal graphics VGA controller + device ref dev4 off end # Signal processing controller chip southbridge/intel/bd82x6x # GPI routing @@ -48,25 +48,25 @@ register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" - device pci 14.0 on end # USB 3.0 Controller - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 19.0 off end # Intel Gigabit Ethernet - device pci 1a.0 on end # USB2 EHCI #2 - device pci 1b.0 on end # High Definition Audio Audio controller - device pci 1c.0 on end # PCIe Port #1 - device pci 1c.1 on end # PCIe Port #2 (WLAN card) - device pci 1c.2 on end # PCIe Port #3 (Card Reader) - device pci 1c.3 off end # PCIe Port #4 - device pci 1c.4 off end # PCIe Port #5 - device pci 1c.5 on end # PCIe Port #6 (Ethernet controller) - device pci 1c.6 off end # PCIe Port #7 - device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on end # USB2 EHCI #1 - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on # LPC bridge PCI-LPC bridge + device ref xhci on end # USB 3.0 Controller + device ref mei1 on end # Management Engine Interface 1 + device ref mei2 off end # Management Engine Interface 2 + device ref me_ide_r off end # Management Engine IDE-R + device ref me_kt off end # Management Engine KT + device ref gbe off end # Intel Gigabit Ethernet + device ref ehci2 on end # USB2 EHCI #2 + device ref hda on end # High Definition Audio Audio controller + device ref rp1 on end # PCIe Port #1 + device ref rp2 on end # PCIe Port #2 (WLAN card) + device ref rp3 on end # PCIe Port #3 (Card Reader) + device ref rp4 off end # PCIe Port #4 + device ref rp5 off end # PCIe Port #5 + device ref rp6 on end # PCIe Port #6 (Ethernet controller) + device ref rp7 off end # PCIe Port #7 + device ref rp8 off end # PCIe Port #8 + device ref ehci1 on end # USB2 EHCI #1 + device ref pci_b off end # PCI bridge + device ref lpc on # LPC bridge PCI-LPC bridge chip drivers/pc80/tpm device pnp 0c31.0 on end end @@ -108,8 +108,8 @@ register "eventf_enable" = "0xff" end end - device pci 1f.2 on end # SATA Controller 1 - device pci 1f.3 on # SMBus + device ref sata1 on end # SATA Controller 1 + device ref smbus on # SMBus # eeprom, 8 virtual devices, same chip chip drivers/i2c/at24rf08c device i2c 54 on end @@ -122,8 +122,8 @@ device i2c 5f on end end end - device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 off end # Thermal + device ref sata2 off end # SATA Controller 2 + device ref thermal off end # Thermal end end end diff --git a/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb b/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb index 0c69353..30ad6e7 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb +++ b/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb @@ -15,9 +15,9 @@ device domain 0 on subsystemid 0x17aa 0x21f9 inherit - device pci 00.0 on end # host bridge - device pci 01.0 off end # PCIe Bridge for discrete graphics - device pci 02.0 on end # vga controller + device ref hb on end # host bridge + device ref peg10 off end # PCIe Bridge for discrete graphics + device ref igd on end # vga controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH # GPI routing @@ -50,31 +50,31 @@ register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" - device pci 14.0 on end # USB 3.0 Controller - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 19.0 off end # Intel Gigabit Ethernet - device pci 1a.0 on end # USB2 EHCI #2 - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 on + device ref xhci on end # USB 3.0 Controller + device ref mei1 on end # Management Engine Interface 1 + device ref mei2 off end # Management Engine Interface 2 + device ref me_ide_r off end # Management Engine IDE-R + device ref me_kt off end # Management Engine KT + device ref gbe off end # Intel Gigabit Ethernet + device ref ehci2 on end # USB2 EHCI #2 + device ref hda on end # High Definition Audio + device ref rp1 on chip drivers/ricoh/rce822 register "sdwppol" = "0" register "disable_mask" = "0x87" device pci 00.0 on end end end # PCIe Port #1 - device pci 1c.1 on end # PCIe Port #2 - device pci 1c.2 off end # PCIe Port #3 - device pci 1c.3 off end # PCIe Port #4 - device pci 1c.4 off end # PCIe Port #5 - device pci 1c.5 off end # PCIe Port #6 - device pci 1c.6 off end # PCIe Port #7 - device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on end # USB2 EHCI #1 - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on #LPC bridge + device ref rp2 on end # PCIe Port #2 + device ref rp3 off end # PCIe Port #3 + device ref rp4 off end # PCIe Port #4 + device ref rp5 off end # PCIe Port #5 + device ref rp6 off end # PCIe Port #6 + device ref rp7 off end # PCIe Port #7 + device ref rp8 off end # PCIe Port #8 + device ref ehci1 on end # USB2 EHCI #1 + device ref pci_b off end # PCI bridge + device ref lpc on #LPC bridge chip ec/lenovo/pmh7 device pnp ff.1 on end # dummy register "backlight_enable" = "0x01" @@ -121,8 +121,8 @@ register "wwan_gpio_lvl" = "0" end end # LPC bridge - device pci 1f.2 on end # SATA Controller 1 - device pci 1f.3 on + device ref sata1 on end # SATA Controller 1 + device ref smbus on # eeprom, 8 virtual devices, same chip chip drivers/i2c/at24rf08c device i2c 54 on end @@ -135,8 +135,8 @@ device i2c 5f on end end end # SMBus - device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 on end # Thermal + device ref sata2 off end # SATA Controller 2 + device ref thermal on end # Thermal end end end diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb index 46459c5..d21ab22 100644 --- a/src/mainboard/lenovo/x220/devicetree.cb +++ b/src/mainboard/lenovo/x220/devicetree.cb @@ -18,9 +18,9 @@ device domain 0 on subsystemid 0x17aa 0x21db inherit - device pci 00.0 on end # host bridge - device pci 01.0 off end # PCIe Bridge for discrete graphics - device pci 02.0 on end # vga controller + device ref hb on end # host bridge + device ref peg10 off end # PCIe Bridge for discrete graphics + device ref igd on end # vga controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH # GPI routing @@ -48,34 +48,34 @@ register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 19.0 on + device ref mei1 on end # Management Engine Interface 1 + device ref mei2 off end # Management Engine Interface 2 + device ref me_ide_r off end # Management Engine IDE-R + device ref me_kt off end # Management Engine KT + device ref gbe on subsystemid 0x17aa 0x21ce end # Intel Gigabit Ethernet - device pci 1a.0 on end # USB2 EHCI #2 - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 on end # PCIe Port #1 - device pci 1c.1 on end # PCIe Port #2 (wlan) - device pci 1c.2 on end # PCIe Port #3 - device pci 1c.3 on + device ref ehci2 on end # USB2 EHCI #2 + device ref hda on end # High Definition Audio + device ref rp1 on end # PCIe Port #1 + device ref rp2 on end # PCIe Port #2 (wlan) + device ref rp3 on end # PCIe Port #3 + device ref rp4 on smbios_slot_desc "7" "3" "ExpressCard Slot" "8" end # PCIe Port #4 - device pci 1c.4 on + device ref rp5 on chip drivers/ricoh/rce822 register "sdwppol" = "1" register "disable_mask" = "0x87" device pci 00.0 on end end end # PCIe Port #5 (SD) - device pci 1c.5 off end # PCIe Port #6 - device pci 1c.6 on end # PCIe Port #7 - device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on end # USB2 EHCI #1 - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on #LPC bridge + device ref rp6 off end # PCIe Port #6 + device ref rp7 on end # PCIe Port #7 + device ref rp8 off end # PCIe Port #8 + device ref ehci1 on end # USB2 EHCI #1 + device ref pci_b off end # PCI bridge + device ref lpc on #LPC bridge chip ec/lenovo/pmh7 device pnp ff.1 on end # dummy register "backlight_enable" = "0x01" @@ -127,8 +127,8 @@ register "wwan_gpio_lvl" = "0" end end # LPC bridge - device pci 1f.2 on end # SATA Controller 1 - device pci 1f.3 on + device ref sata1 on end # SATA Controller 1 + device ref smbus on # eeprom, 8 virtual devices, same chip chip drivers/i2c/at24rf08c device i2c 54 on end @@ -141,8 +141,8 @@ device i2c 5f on end end end # SMBus - device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 on end # Thermal + device ref sata2 off end # SATA Controller 2 + device ref thermal on end # Thermal end end end diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb index 5c1c124..3f2703c 100644 --- a/src/mainboard/lenovo/x230/devicetree.cb +++ b/src/mainboard/lenovo/x230/devicetree.cb @@ -18,9 +18,9 @@ device domain 0 on subsystemid 0x17aa 0x21fa inherit - device pci 00.0 on end # host bridge - device pci 01.0 off end # PCIe Bridge for discrete graphics - device pci 02.0 on end # vga controller + device ref hb on end # host bridge + device ref peg10 off end # PCIe Bridge for discrete graphics + device ref igd on end # vga controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH # GPI routing @@ -51,33 +51,33 @@ register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" - device pci 14.0 on end # USB 3.0 Controller - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 19.0 on + device ref xhci on end # USB 3.0 Controller + device ref mei1 on end # Management Engine Interface 1 + device ref mei2 off end # Management Engine Interface 2 + device ref me_ide_r off end # Management Engine IDE-R + device ref me_kt off end # Management Engine KT + device ref gbe on subsystemid 0x17aa 0x21f3 end # Intel Gigabit Ethernet - device pci 1a.0 on end # USB2 EHCI #2 - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 on + device ref ehci2 on end # USB2 EHCI #2 + device ref hda on end # High Definition Audio + device ref rp1 on chip drivers/ricoh/rce822 register "sdwppol" = "1" register "disable_mask" = "0x87" device pci 00.0 on end end end # PCIe Port #1 - device pci 1c.1 on end # PCIe Port #2 - device pci 1c.2 off end # PCIe Port #3 - device pci 1c.3 off end # PCIe Port #4 - device pci 1c.4 off end # PCIe Port #5 - device pci 1c.5 off end # PCIe Port #6 - device pci 1c.6 off end # PCIe Port #7 - device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on end # USB2 EHCI #1 - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on #LPC bridge + device ref rp2 on end # PCIe Port #2 + device ref rp3 off end # PCIe Port #3 + device ref rp4 off end # PCIe Port #4 + device ref rp5 off end # PCIe Port #5 + device ref rp6 off end # PCIe Port #6 + device ref rp7 off end # PCIe Port #7 + device ref rp8 off end # PCIe Port #8 + device ref ehci1 on end # USB2 EHCI #1 + device ref pci_b off end # PCI bridge + device ref lpc on #LPC bridge chip ec/lenovo/pmh7 device pnp ff.1 on end # dummy register "backlight_enable" = "0x01" @@ -130,8 +130,8 @@ register "wwan_gpio_lvl" = "0" end end # LPC bridge - device pci 1f.2 on end # SATA Controller 1 - device pci 1f.3 on + device ref sata1 on end # SATA Controller 1 + device ref smbus on # eeprom, 8 virtual devices, same chip chip drivers/i2c/at24rf08c device i2c 54 on end @@ -144,8 +144,8 @@ device i2c 5f on end end end # SMBus - device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 on end # Thermal + device ref sata2 off end # SATA Controller 2 + device ref thermal on end # Thermal end end end diff --git a/src/mainboard/msi/ms7707/devicetree.cb b/src/mainboard/msi/ms7707/devicetree.cb index e0fbc1a..ee939e6 100644 --- a/src/mainboard/msi/ms7707/devicetree.cb +++ b/src/mainboard/msi/ms7707/devicetree.cb @@ -2,9 +2,9 @@ device domain 0 on subsystemid 0x1462 0x7707 inherit - device pci 00.0 on end # Host bridge - device pci 01.0 on end # PCIe Bridge for discrete graphics - device pci 02.0 off end # Internal graphics + device ref hb on end # Host bridge + device ref peg10 on end # PCIe Bridge for discrete graphics + device ref igd off end # Internal graphics chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "docking_supported" = "0" @@ -17,24 +17,24 @@ register "spi_uvscc" = "0x2005" register "gpe0_en" = "0x28000040" - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 19.0 on end # Intel Gigabit Ethernet - device pci 1a.0 on end # USB2 EHCI #2 - device pci 1b.0 on end # HD Audio controller - device pci 1c.0 on end # PCIe Port #1 - device pci 1c.1 off end # PCIe Port #2 - device pci 1c.2 off end # PCIe Port #3 - device pci 1c.3 off end # PCIe Port #4 - device pci 1c.4 off end # PCIe Port #5 - device pci 1c.5 off end # PCIe Port #6 - device pci 1c.6 on end # PCIe Port #7 - device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on end # USB2 EHCI #1 - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on # LPC bridge + device ref mei1 on end # Management Engine Interface 1 + device ref mei2 off end # Management Engine Interface 2 + device ref me_ide_r off end # Management Engine IDE-R + device ref me_kt off end # Management Engine KT + device ref gbe on end # Intel Gigabit Ethernet + device ref ehci2 on end # USB2 EHCI #2 + device ref hda on end # HD Audio controller + device ref rp1 on end # PCIe Port #1 + device ref rp2 off end # PCIe Port #2 + device ref rp3 off end # PCIe Port #3 + device ref rp4 off end # PCIe Port #4 + device ref rp5 off end # PCIe Port #5 + device ref rp6 off end # PCIe Port #6 + device ref rp7 on end # PCIe Port #7 + device ref rp8 off end # PCIe Port #8 + device ref ehci1 on end # USB2 EHCI #1 + device ref pci_b off end # PCI bridge + device ref lpc on # LPC bridge chip superio/fintek/f71808a register "multi_function_register_0" = "0x00" # 0x28 register "multi_function_register_1" = "0xc0" # 0x29 @@ -94,10 +94,10 @@ end end end - device pci 1f.2 on end # SATA Controller 1 - device pci 1f.3 on end # SMBus - device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 off end # Thermal + device ref sata1 on end # SATA Controller 1 + device ref smbus on end # SMBus + device ref sata2 off end # SATA Controller 2 + device ref thermal off end # Thermal end end end diff --git a/src/mainboard/roda/rv11/variants/rv11/devicetree.cb b/src/mainboard/roda/rv11/variants/rv11/devicetree.cb index 44e7372..936256a 100644 --- a/src/mainboard/roda/rv11/variants/rv11/devicetree.cb +++ b/src/mainboard/roda/rv11/variants/rv11/devicetree.cb @@ -25,8 +25,8 @@ end device domain 0 on - device pci 00.0 on end # host bridge - device pci 02.0 on end # vga controller + device ref hb on end # host bridge + device ref igd on end # vga controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH # Enable both SATA ports 0, 1 @@ -52,40 +52,40 @@ register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" - device pci 14.0 on end # USB 3.0 Controller - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 19.0 on end # Intel Gigabit Ethernet - device pci 1a.0 on end # USB2 EHCI #2 - device pci 1b.0 on # High Definition Audio + device ref xhci on end # USB 3.0 Controller + device ref mei1 on end # Management Engine Interface 1 + device ref mei2 off end # Management Engine Interface 2 + device ref me_ide_r off end # Management Engine IDE-R + device ref me_kt off end # Management Engine KT + device ref gbe on end # Intel Gigabit Ethernet + device ref ehci2 on end # USB2 EHCI #2 + device ref hda on # High Definition Audio subsystemid 0x1a86 0x4352 end # Disabling 1c.0 might break IRQ settings as it enables port coalescing - device pci 1c.0 on end # PCIe Port #1 - device pci 1c.1 on end # PCIe Port #2 - device pci 1c.2 off end # PCIe Port #3 - device pci 1c.3 on end # PCIe Port #4 - device pci 1c.4 on end # PCIe Port #5 - device pci 1c.5 off end # PCIe Port #6 - device pci 1c.6 on end # PCIe Port #7 - device pci 1c.7 on end # PCIe Port #8 + device ref rp1 on end # PCIe Port #1 + device ref rp2 on end # PCIe Port #2 + device ref rp3 off end # PCIe Port #3 + device ref rp4 on end # PCIe Port #4 + device ref rp5 on end # PCIe Port #5 + device ref rp6 off end # PCIe Port #6 + device ref rp7 on end # PCIe Port #7 + device ref rp8 on end # PCIe Port #8 - device pci 1d.0 on end # USB2 EHCI #1 - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on # LPC bridge + device ref ehci1 on end # USB2 EHCI #1 + device ref pci_b off end # PCI bridge + device ref lpc on # LPC bridge chip ec/roda/it8518 # 60h/64h KBC device pnp ff.0 on # dummy address end end end # LPC bridge - device pci 1f.2 on end # SATA Controller 1 - device pci 1f.3 on end # SMBus - device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 off end # Thermal + device ref sata1 on end # SATA Controller 1 + device ref smbus on end # SMBus + device ref sata2 off end # SATA Controller 2 + device ref thermal off end # Thermal end end end diff --git a/src/mainboard/roda/rv11/variants/rw11/devicetree.cb b/src/mainboard/roda/rv11/variants/rw11/devicetree.cb index c6aa44c..e3addf1 100644 --- a/src/mainboard/roda/rv11/variants/rw11/devicetree.cb +++ b/src/mainboard/roda/rv11/variants/rw11/devicetree.cb @@ -25,8 +25,8 @@ end device domain 0 on - device pci 00.0 on end # host bridge - device pci 02.0 on end # vga controller + device ref hb on end # host bridge + device ref igd on end # vga controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH # LPC i/o generic decodes @@ -57,30 +57,30 @@ register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" - device pci 14.0 on end # USB 3.0 Controller - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 19.0 on end # Intel Gigabit Ethernet - device pci 1a.0 on end # USB2 EHCI #2 - device pci 1b.0 on # High Definition Audio + device ref xhci on end # USB 3.0 Controller + device ref mei1 on end # Management Engine Interface 1 + device ref mei2 off end # Management Engine Interface 2 + device ref me_ide_r off end # Management Engine IDE-R + device ref me_kt off end # Management Engine KT + device ref gbe on end # Intel Gigabit Ethernet + device ref ehci2 on end # USB2 EHCI #2 + device ref hda on # High Definition Audio subsystemid 0x1a86 0x4352 end # Disabling 1c.0 might break IRQ settings as it enables port coalescing - device pci 1c.0 on end # PCIe Port #1 - device pci 1c.1 on end # PCIe Port #2 - device pci 1c.2 on end # PCIe Port #3 - device pci 1c.3 on end # PCIe Port #4 - device pci 1c.4 on end # PCIe Port #5 - device pci 1c.5 on end # PCIe Port #6 - device pci 1c.6 on end # PCIe Port #7 - device pci 1c.7 on end # PCIe Port #8 + device ref rp1 on end # PCIe Port #1 + device ref rp2 on end # PCIe Port #2 + device ref rp3 on end # PCIe Port #3 + device ref rp4 on end # PCIe Port #4 + device ref rp5 on end # PCIe Port #5 + device ref rp6 on end # PCIe Port #6 + device ref rp7 on end # PCIe Port #7 + device ref rp8 on end # PCIe Port #8 - device pci 1d.0 on end # USB2 EHCI #1 - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on # LPC bridge + device ref ehci1 on end # USB2 EHCI #1 + device ref pci_b off end # PCI bridge + device ref lpc on # LPC bridge chip ec/roda/it8518 register "cpuhot_limit" = "100" # 60h/64h KBC @@ -144,10 +144,10 @@ device pnp 2e.c off end # CIR end end # LPC bridge - device pci 1f.2 on end # SATA Controller 1 - device pci 1f.3 on end # SMBus - device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 off end # Thermal + device ref sata1 on end # SATA Controller 1 + device ref smbus on end # SMBus + device ref sata2 off end # SATA Controller 2 + device ref thermal off end # Thermal end end end diff --git a/src/mainboard/samsung/lumpy/devicetree.cb b/src/mainboard/samsung/lumpy/devicetree.cb index 48fd81a..91ef7c7 100644 --- a/src/mainboard/samsung/lumpy/devicetree.cb +++ b/src/mainboard/samsung/lumpy/devicetree.cb @@ -25,8 +25,8 @@ ioapic_irq 4 INTC 0x12 ioapic_irq 4 INTD 0x13 subsystemid 0x1ae0 0xc000 inherit - device pci 00.0 on end # host bridge - device pci 02.0 on end # vga controller + device ref hb on end # host bridge + device ref igd on end # vga controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH # GPI routing @@ -44,32 +44,32 @@ register "gen2_dec" = "0x003c0b01" register "gen3_dec" = "0x00fc1601" - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 19.0 off end # Intel Gigabit Ethernet - device pci 1a.0 on # USB2 EHCI #2 + device ref mei1 on end # Management Engine Interface 1 + device ref mei2 off end # Management Engine Interface 2 + device ref me_ide_r off end # Management Engine IDE-R + device ref me_kt off end # Management Engine KT + device ref gbe off end # Intel Gigabit Ethernet + device ref ehci2 on # USB2 EHCI #2 ioapic_irq 4 INTA 0x11 end - device pci 1b.0 on # High Definition Audio + device ref hda on # High Definition Audio ioapic_irq 4 INTA 0x16 end - device pci 1c.0 on end # PCIe Port #1 (WLAN) - device pci 1c.1 off end # PCIe Port #2 - device pci 1c.2 off end # PCIe Port #3 - device pci 1c.3 on # PCIe Port #4 (LAN) + device ref rp1 on end # PCIe Port #1 (WLAN) + device ref rp2 off end # PCIe Port #2 + device ref rp3 off end # PCIe Port #3 + device ref rp4 on # PCIe Port #4 (LAN) # ioapic_irq 4 INTA 0x13 end - device pci 1c.4 off end # PCIe Port #5 - device pci 1c.5 off end # PCIe Port #6 - device pci 1c.6 off end # PCIe Port #7 - device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on # USB2 EHCI #1 + device ref rp5 off end # PCIe Port #5 + device ref rp6 off end # PCIe Port #6 + device ref rp7 off end # PCIe Port #7 + device ref rp8 off end # PCIe Port #8 + device ref ehci1 on # USB2 EHCI #1 ioapic_irq 4 INTA 0x13 end - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on # LPC bridge + device ref pci_b off end # PCI bridge + device ref lpc on # LPC bridge ioapic_irq 4 INTA 0x10 chip superio/smsc/mec1308 device pnp 2e.1 on # PM1 @@ -102,14 +102,14 @@ device pnp 0c31.0 on end end end - device pci 1f.2 on # SATA Controller 1 + device ref sata1 on # SATA Controller 1 ioapic_irq 4 INTA 0x10 end - device pci 1f.3 on # SMBus + device ref smbus on # SMBus ioapic_irq 4 INTC 0x17 end - device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 on end # Thermal + device ref sata2 off end # SATA Controller 2 + device ref thermal on end # Thermal end end end diff --git a/src/mainboard/samsung/stumpy/devicetree.cb b/src/mainboard/samsung/stumpy/devicetree.cb index 10aeb44..c3154b8 100644 --- a/src/mainboard/samsung/stumpy/devicetree.cb +++ b/src/mainboard/samsung/stumpy/devicetree.cb @@ -20,8 +20,8 @@ device domain 0 on subsystemid 0x1ae0 0xc000 inherit - device pci 00.0 on end # host bridge - device pci 02.0 on end # vga controller + device ref hb on end # host bridge + device ref igd on end # vga controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH # GPI routing @@ -37,24 +37,24 @@ # SuperIO range is 0x700-0x73f register "gen2_dec" = "0x003c0701" - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 19.0 off end # Intel Gigabit Ethernet - device pci 1a.0 on end # USB2 EHCI #2 - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 on end # PCIe Port #1 (WLAN) - device pci 1c.1 off end # PCIe Port #2 - device pci 1c.2 on end # PCIe Port #3 (Debug) - device pci 1c.3 on end # PCIe Port #4 (LAN) - device pci 1c.4 off end # PCIe Port #5 - device pci 1c.5 off end # PCIe Port #6 - device pci 1c.6 off end # PCIe Port #7 - device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on end # USB2 EHCI #1 - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on # LPC bridge + device ref mei1 on end # Management Engine Interface 1 + device ref mei2 off end # Management Engine Interface 2 + device ref me_ide_r off end # Management Engine IDE-R + device ref me_kt off end # Management Engine KT + device ref gbe off end # Intel Gigabit Ethernet + device ref ehci2 on end # USB2 EHCI #2 + device ref hda on end # High Definition Audio + device ref rp1 on end # PCIe Port #1 (WLAN) + device ref rp2 off end # PCIe Port #2 + device ref rp3 on end # PCIe Port #3 (Debug) + device ref rp4 on end # PCIe Port #4 (LAN) + device ref rp5 off end # PCIe Port #5 + device ref rp6 off end # PCIe Port #6 + device ref rp7 off end # PCIe Port #7 + device ref rp8 off end # PCIe Port #8 + device ref ehci1 on end # USB2 EHCI #1 + device ref pci_b off end # PCI bridge + device ref lpc on # LPC bridge chip superio/ite/it8772f # Enable GPIO10 as USBPWRON12# # Enable GPIO12 as USBPWRON13# @@ -102,10 +102,10 @@ device pnp 0c31.0 on end end end - device pci 1f.2 on end # SATA Controller 1 - device pci 1f.3 on end # SMBus - device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 on end # Thermal + device ref sata1 on end # SATA Controller 1 + device ref smbus on end # SMBus + device ref sata2 off end # SATA Controller 2 + device ref thermal on end # Thermal end end end diff --git a/src/mainboard/sapphire/pureplatinumh61/devicetree.cb b/src/mainboard/sapphire/pureplatinumh61/devicetree.cb index b1beae0..e4458af 100644 --- a/src/mainboard/sapphire/pureplatinumh61/devicetree.cb +++ b/src/mainboard/sapphire/pureplatinumh61/devicetree.cb @@ -17,38 +17,38 @@ {0x9f, READ_NO_ADDR}, {0xad, WRITE_NO_ADDR}, {0x04, WRITE_NO_ADDR}}" - device pci 16.0 on # Management Engine Interface 1 + device ref mei1 on # Management Engine Interface 1 subsystemid 0x174b 0x1007 end - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 19.0 off end # Intel Gigabit Ethernet - device pci 1a.0 on # USB2 EHCI #2 + device ref mei2 off end # Management Engine Interface 2 + device ref me_ide_r off end # Management Engine IDE-R + device ref me_kt off end # Management Engine KT + device ref gbe off end # Intel Gigabit Ethernet + device ref ehci2 on # USB2 EHCI #2 subsystemid 0x174b 0x1007 end - device pci 1b.0 on # HD Audio Controller + device ref hda on # HD Audio Controller subsystemid 0x8086 0x1c20 end - device pci 1c.0 on # PCIe Port #1 + device ref rp1 on # PCIe Port #1 subsystemid 0x174b 0x1007 end - device pci 1c.1 off end # PCIe Port #2 - device pci 1c.2 off end # PCIe Port #3 - device pci 1c.3 off end # PCIe Port #4 - device pci 1c.4 on # PCIe Port #5 + device ref rp2 off end # PCIe Port #2 + device ref rp3 off end # PCIe Port #3 + device ref rp4 off end # PCIe Port #4 + device ref rp5 on # PCIe Port #5 subsystemid 0x174b 0x1007 end - device pci 1c.5 on # PCIe Port #6 + device ref rp6 on # PCIe Port #6 subsystemid 0x174b 0x1007 end - device pci 1c.6 off end # PCIe Port #7 - device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on # USB2 EHCI #1 + device ref rp7 off end # PCIe Port #7 + device ref rp8 off end # PCIe Port #8 + device ref ehci1 on # USB2 EHCI #1 subsystemid 0x174b 0x1007 end - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on # LPC bridge + device ref pci_b off end # PCI bridge + device ref lpc on # LPC bridge subsystemid 0x174b 0x1007 chip superio/fintek/f71808a register "multi_function_register_0" = "0x00" @@ -91,22 +91,22 @@ end end end - device pci 1f.2 on # SATA Controller 1 + device ref sata1 on # SATA Controller 1 subsystemid 0x174b 0x1007 end - device pci 1f.3 on # SMBus + device ref smbus on # SMBus subsystemid 0x174b 0x1007 end - device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 off end # Thermal + device ref sata2 off end # SATA Controller 2 + device ref thermal off end # Thermal end - device pci 00.0 on # Host bridge + device ref hb on # Host bridge subsystemid 0x174b 0x1007 end - device pci 01.0 on # PCIe Bridge for discrete graphics + device ref peg10 on # PCIe Bridge for discrete graphics subsystemid 0x174b 0x1007 end - device pci 02.0 on # Internal graphics VGA controller + device ref igd on # Internal graphics VGA controller subsystemid 0x8086 0x2010 end end diff --git a/src/mainboard/supermicro/x9sae/devicetree.cb b/src/mainboard/supermicro/x9sae/devicetree.cb index ed011c1..e4736cf 100644 --- a/src/mainboard/supermicro/x9sae/devicetree.cb +++ b/src/mainboard/supermicro/x9sae/devicetree.cb @@ -10,11 +10,11 @@ device domain 0 on subsystemid 0x15d9 0x0644 inherit - device pci 00.0 on end # Host bridge - device pci 01.0 on end # CPU1 SLOT6 (x8 or x16) - device pci 01.1 on end # CPU1 SLOT4 (electrical x8 in x16 if present) - device pci 02.0 on end # iGPU - device pci 06.0 on end # CPU1 SLOT7 (electrical x4 in x8) + device ref hb on end # Host bridge + device ref peg10 on end # CPU1 SLOT6 (x8 or x16) + device ref peg11 on end # CPU1 SLOT4 (electrical x8 in x16 if present) + device ref igd on end # iGPU + device ref peg60 on end # CPU1 SLOT7 (electrical x4 in x8) chip southbridge/intel/bd82x6x register "gen1_dec" = "0x00fc0a01" # NCT6776 SuperIO (0x0a00-0aff) @@ -26,29 +26,29 @@ register "xhci_overcurrent_mapping" = "0x00000c03" register "xhci_switchable_ports" = "0x0000000f" - device pci 14.0 on end # xHCI - device pci 16.0 on end # MEI #1 - device pci 16.1 off end # MEI #2 - device pci 16.2 off end # ME IDE-R - device pci 16.3 off end # ME KT - device pci 19.0 on end # Intel GbE LAN1 - device pci 1a.0 on end # EHCI #2 - device pci 1b.0 on end # HD Audio + device ref xhci on end # xHCI + device ref mei1 on end # MEI #1 + device ref mei2 off end # MEI #2 + device ref me_ide_r off end # ME IDE-R + device ref me_kt off end # ME KT + device ref gbe on end # Intel GbE LAN1 + device ref ehci2 on end # EHCI #2 + device ref hda on end # HD Audio - device pci 1c.0 on end # RP #1 PCH SLOT2 - device pci 1c.1 off end # RP #2 - device pci 1c.2 off end # RP #3 - device pci 1c.3 off end # RP #4 - device pci 1c.4 on end # RP #5 PCH SLOT3 - device pci 1c.5 off end # RP #6 - device pci 1c.6 on end # RP #7 PCH SLOT5 - device pci 1c.7 on # RP #8 + device ref rp1 on end # RP #1 PCH SLOT2 + device ref rp2 off end # RP #2 + device ref rp3 off end # RP #3 + device ref rp4 off end # RP #4 + device ref rp5 on end # RP #5 PCH SLOT3 + device ref rp6 off end # RP #6 + device ref rp7 on end # RP #7 PCH SLOT5 + device ref rp8 on # RP #8 device pci 00.0 on end # 574 GbE LAN2 end - device pci 1d.0 on end # EHCI #1 - device pci 1e.0 on end # PCI bridge - device pci 1f.0 on # LPC bridge + device ref ehci1 on end # EHCI #1 + device ref pci_b on end # PCI bridge + device ref lpc on # LPC bridge chip superio/nuvoton/nct6776 device pnp 2e.0 off end # Floppy device pnp 2e.1 off end # Parallel port @@ -108,10 +108,10 @@ device pnp c31.0 on end # TPM end end - device pci 1f.2 on end # SATA (AHCI) - device pci 1f.3 on end # SMBus - device pci 1f.5 off end # SATA (Legacy) - device pci 1f.6 off end # Thermal + device ref sata1 on end # SATA (AHCI) + device ref smbus on end # SMBus + device ref sata2 off end # SATA (Legacy) + device ref thermal off end # Thermal end end end diff --git a/src/mainboard/supermicro/x9scl/devicetree.cb b/src/mainboard/supermicro/x9scl/devicetree.cb index b0f3534..d5dbfad 100644 --- a/src/mainboard/supermicro/x9scl/devicetree.cb +++ b/src/mainboard/supermicro/x9scl/devicetree.cb @@ -1,11 +1,11 @@ chip northbridge/intel/sandybridge device domain 0 on subsystemid 0x15d9 0x0624 inherit - device pci 00.0 on end # Host bridge - device pci 01.0 on end # PEG - device pci 01.1 on end # PEG - device pci 02.0 off end # iGPU - device pci 06.0 on end # PEG + device ref hb on end # Host bridge + device ref peg10 on end # PEG + device ref peg11 on end # PEG + device ref igd off end # iGPU + device ref peg60 on end # PEG chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "gen1_dec" = "0x00fc0a01" # NCT6776 SuperIO (0x0a00-0aff) register "gen2_dec" = "0x00fc1641" # WPCM450 SuperIO (0x1600-16ff) @@ -16,32 +16,32 @@ register "sata_port_map" = "0x3f" register "spi_lvscc" = "0x2005" register "spi_uvscc" = "0x2005" - device pci 16.0 off end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 19.0 on # Intel Gigabit Ethernet (not for X9SCL+-F) + device ref mei1 off end # Management Engine Interface 1 + device ref mei2 off end # Management Engine Interface 2 + device ref me_ide_r off end # Management Engine IDE-R + device ref me_kt off end # Management Engine KT + device ref gbe on # Intel Gigabit Ethernet (not for X9SCL+-F) subsystemid 0x15d9 0x1502 end - device pci 1a.0 on end # USB2 EHCI #2 - device pci 1b.0 off end # High Definition Audio - device pci 1c.0 on end # PCIe Port #1 - device pci 1c.1 off end # PCIe Port #2 - device pci 1c.2 off end # PCIe Port #3 - device pci 1c.3 off end # PCIe Port #4 - device pci 1c.4 on # PCIe Port #5 + device ref ehci2 on end # USB2 EHCI #2 + device ref hda off end # High Definition Audio + device ref rp1 on end # PCIe Port #1 + device ref rp2 off end # PCIe Port #2 + device ref rp3 off end # PCIe Port #3 + device ref rp4 off end # PCIe Port #4 + device ref rp5 on # PCIe Port #5 device pci 00.0 on end # primary 574 GigE end - device pci 1c.5 off end # PCIe Port #6 - device pci 1c.6 on # PCIe Port #7 + device ref rp6 off end # PCIe Port #6 + device ref rp7 on # PCIe Port #7 device pci 00.0 on end # secondary 574 GigE on X9SCL+-F end - device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on end # USB2 EHCI #1 - device pci 1e.0 on # PCI bridge + device ref rp8 off end # PCIe Port #8 + device ref ehci1 on end # USB2 EHCI #1 + device ref pci_b on # PCI bridge device pci 03.0 on end # Matrox G200e in BMC end - device pci 1f.0 on # LPC bridge + device ref lpc on # LPC bridge chip superio/nuvoton/nct6776 device pnp 2e.0 off end # Floppy device pnp 2e.1 off end # Parallel port @@ -105,10 +105,10 @@ device pnp 164e.6 off end end end - device pci 1f.2 on end # SATA Controller 1 - device pci 1f.3 on end # SMBus - device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 off end # Thermal + device ref sata1 on end # SATA Controller 1 + device ref smbus on end # SMBus + device ref sata2 off end # SATA Controller 2 + device ref thermal off end # Thermal end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/69502 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I74c34a97ea4340fb11a0db422a48e1418221627e Gerrit-Change-Number: 69502 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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[L] Change in coreboot[master]: drivers/generic/ioapic: Drop poor implementation
by Kyösti Mälkki (Code Review) 12 Nov '22

12 Nov '22

Attention is currently required from: Stefan Ott, Nico Huber, Alexander Couzens. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69488 ) Change subject: drivers/generic/ioapic: Drop poor implementation ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > The preceding change is not needed then? We could squash these two, yes, if there is no resistance with dropping HAVE_MP_TABLE here. -- To view, visit https://review.coreboot.org/c/coreboot/+/69488 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I383d55ba2bc0800423617215e0bfdfad5136e9ac Gerrit-Change-Number: 69488 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Stefan Ott <coreboot(a)desire.ch> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Stefan Ott <coreboot(a)desire.ch> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Comment-Date: Sat, 12 Nov 2022 13:26:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/brya/var/marasov: Add touchscreen and touchpad for marasov
by Tarun Tuli (Code Review) 12 Nov '22

12 Nov '22

Attention is currently required from: Frank Chu. Tarun Tuli has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69467 ) Change subject: mb/google/brya/var/marasov: Add touchscreen and touchpad for marasov ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/69467/comment/81df0010_a7c91425 PS1, Line 13: TEST=Built successfully Do we have hardware yet to confirm functionality of the touchscreen/pad? -- To view, visit https://review.coreboot.org/c/coreboot/+/69467 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifc865fc0c0c42af0d74272289c562e347fac3a9e Gerrit-Change-Number: 69467 Gerrit-PatchSet: 1 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-Attention: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Comment-Date: Sat, 12 Nov 2022 12:43:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in coreboot[master]: drivers/generic/ioapic: Drop poor implementation
by Nico Huber (Code Review) 12 Nov '22

12 Nov '22

Attention is currently required from: Stefan Ott, Kyösti Mälkki, Alexander Couzens. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69488 ) Change subject: drivers/generic/ioapic: Drop poor implementation ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Patchset: PS1: The preceding change is not needed then? -- To view, visit https://review.coreboot.org/c/coreboot/+/69488 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I383d55ba2bc0800423617215e0bfdfad5136e9ac Gerrit-Change-Number: 69488 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Stefan Ott <coreboot(a)desire.ch> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Stefan Ott <coreboot(a)desire.ch> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Comment-Date: Sat, 12 Nov 2022 10:57:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: nb/intel/sandybridge: Hook up CPU bus and PCI domain ops to devicetree
by Arthur Heymans (Code Review) 12 Nov '22

12 Nov '22

Attention is currently required from: Angel Pons, Alexander Couzens, Evgeny Zinoviev. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69291 ) Change subject: nb/intel/sandybridge: Hook up CPU bus and PCI domain ops to devicetree ...................................................................... Patch Set 10: (1 comment) File src/mainboard/asus/h61-series/variants/p8h61-m_lx/overridetree.cb: https://review.coreboot.org/c/coreboot/+/69291/comment/99648091_aededb37 PS9, Line 5: ops sandybridge_pci_domain_ops > should not be needed in overridetree. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/69291 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I718d9dbc184c8bca38f452efea3202901018cb04 Gerrit-Change-Number: 69291 Gerrit-PatchSet: 10 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Comment-Date: Sat, 12 Nov 2022 10:51:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: util/autoport: Update devicetree generation
by Arthur Heymans (Code Review) 12 Nov '22

12 Nov '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69501 ) Change subject: util/autoport: Update devicetree generation ...................................................................... util/autoport: Update devicetree generation CPU nodes are now declared in a common chipset.cb. TESTED: generates a proper devicetree for x220 based on logs. Change-Id: Ic1f2d3d611aa3979b846706b6f743f79a3c4e54d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M util/autoport/sandybridge.go 1 file changed, 14 insertions(+), 28 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/69501/1 diff --git a/util/autoport/sandybridge.go b/util/autoport/sandybridge.go index 950286c..a60018e 100644 --- a/util/autoport/sandybridge.go +++ b/util/autoport/sandybridge.go @@ -36,34 +36,6 @@ }, Children: []DevTreeNode{ { - Chip: "cpu_cluster", - Dev: 0, - Children: []DevTreeNode{ - { - Chip: "cpu/intel/model_206ax", - Comment: "FIXME: check all registers", - Registers: map[string]string{ - /* FIXME:XX hardcoded. */ - "acpi_c1": "1", - "acpi_c2": "3", - "acpi_c3": "5", - }, - Children: []DevTreeNode{ - { - Chip: "lapic", - Dev: 0, - }, - { - Chip: "lapic", - Dev: 0xacac, - Disabled: true, - }, - }, - }, - }, - }, - - { Chip: "domain", Dev: 0, PCIController: true, -- To view, visit https://review.coreboot.org/c/coreboot/+/69501 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic1f2d3d611aa3979b846706b6f743f79a3c4e54d Gerrit-Change-Number: 69501 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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