coreboot-gerrit November 2022

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[M] Change in coreboot[master]: cpu/intel/model_206ax: Remove fake lapic device
by Arthur Heymans (Code Review) 12 Nov '22

12 Nov '22

Attention is currently required from: Arthur Heymans, Tristan Corrick, Angel Pons, Alexander Couzens, Evgeny Zinoviev, Patrick Rudolph. Arthur Heymans has uploaded a new patch set (#14) to the change originally created by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/59316 ) Change subject: cpu/intel/model_206ax: Remove fake lapic device ...................................................................... cpu/intel/model_206ax: Remove fake lapic device Instead of using a fake lapic device hook up the cpu cluster to chip cpu/intel/model_206ax. The lapic deive is also not needed as the mp init will allocate it for the BSP at runtime. Change-Id: Id3b1c4ca027e2905535e137691c3e3e60417dbf3 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/model_206ax/acpi.c M src/cpu/intel/model_206ax/chip.h M src/cpu/intel/model_206ax/model_206ax_init.c M src/mainboard/intel/emeraldlake2/devicetree.cb M src/mainboard/kontron/ktqm77/devicetree.cb M src/mainboard/roda/rv11/variants/rv11/devicetree.cb M src/mainboard/roda/rv11/variants/rw11/devicetree.cb M src/mainboard/samsung/stumpy/devicetree.cb M src/northbridge/intel/sandybridge/chipset.cb M src/northbridge/intel/sandybridge/northbridge.c 10 files changed, 49 insertions(+), 77 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/59316/14 -- To view, visit https://review.coreboot.org/c/coreboot/+/59316 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id3b1c4ca027e2905535e137691c3e3e60417dbf3 Gerrit-Change-Number: 59316 Gerrit-PatchSet: 14 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: cpu/intel/sandybridge: Use enum for ACPI C states
by Arthur Heymans (Code Review) 12 Nov '22

12 Nov '22

Attention is currently required from: Angel Pons, Alexander Couzens, Evgeny Zinoviev. Hello build bot (Jenkins), Angel Pons, Alexander Couzens, Evgeny Zinoviev, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69292 to look at the new patch set (#10). Change subject: cpu/intel/sandybridge: Use enum for ACPI C states ...................................................................... cpu/intel/sandybridge: Use enum for ACPI C states Also remove the now unnecessary comments from the devicetree. Change-Id: Iebbe12fd413b7a2eb1078a579e194eba821ada7c Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/model_206ax/chip.h M src/mainboard/intel/emeraldlake2/devicetree.cb M src/mainboard/kontron/ktqm77/devicetree.cb M src/mainboard/roda/rv11/variants/rv11/devicetree.cb M src/mainboard/roda/rv11/variants/rw11/devicetree.cb M src/mainboard/samsung/stumpy/devicetree.cb M src/northbridge/intel/sandybridge/chipset.cb 7 files changed, 38 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/69292/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/69292 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iebbe12fd413b7a2eb1078a579e194eba821ada7c Gerrit-Change-Number: 69292 Gerrit-PatchSet: 10 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: nb/intel/sandybridge: Hook up CPU bus and PCI domain ops to devicetree
by Arthur Heymans (Code Review) 12 Nov '22

12 Nov '22

Attention is currently required from: Angel Pons, Alexander Couzens, Evgeny Zinoviev. Hello build bot (Jenkins), Angel Pons, Alexander Couzens, Evgeny Zinoviev, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69291 to look at the new patch set (#10). Change subject: nb/intel/sandybridge: Hook up CPU bus and PCI domain ops to devicetree ...................................................................... nb/intel/sandybridge: Hook up CPU bus and PCI domain ops to devicetree Change-Id: I718d9dbc184c8bca38f452efea3202901018cb04 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/sandybridge/chipset.cb M src/northbridge/intel/sandybridge/northbridge.c 2 files changed, 14 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/69291/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/69291 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I718d9dbc184c8bca38f452efea3202901018cb04 Gerrit-Change-Number: 69291 Gerrit-PatchSet: 10 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[master]: nb/intel/sandybridge: Add a chipset devicetree
by Arthur Heymans (Code Review) 12 Nov '22

12 Nov '22

Attention is currently required from: Angel Pons, Arthur Heymans, Evgeny Zinoviev, Alexander Couzens, Patrick Rudolph. Arthur Heymans has uploaded a new patch set (#2) to the change originally created by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/56912 ) Change subject: nb/intel/sandybridge: Add a chipset devicetree ...................................................................... nb/intel/sandybridge: Add a chipset devicetree This only moves CPU configuration to a common place. Other PCI devices can be done in follow-ups. Change-Id: I9c5b6f25b779e28b6719cf70455ff0f1a916ad87 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/apple/macbookair4_2/devicetree.cb M src/mainboard/asrock/b75pro3-m/devicetree.cb M src/mainboard/asrock/h77pro4-m/devicetree.cb M src/mainboard/asus/h61-series/devicetree.cb M src/mainboard/asus/maximus_iv_gene-z/devicetree.cb M src/mainboard/asus/p8x7x-series/devicetree.cb M src/mainboard/biostar/th61-itx/devicetree.cb M src/mainboard/compulab/intense_pc/devicetree.cb M src/mainboard/dell/snb_ivb_workstations/variants/baseboard/devicetree.cb M src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb M src/mainboard/gigabyte/ga-h61m-series/devicetree.cb M src/mainboard/google/butterfly/devicetree.cb M src/mainboard/google/link/devicetree.cb M src/mainboard/google/parrot/devicetree.cb M src/mainboard/google/stout/devicetree.cb M src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb M src/mainboard/hp/snb_ivb_laptops/devicetree.cb M src/mainboard/hp/z220_series/devicetree.cb M src/mainboard/intel/dcp847ske/devicetree.cb M src/mainboard/intel/emeraldlake2/devicetree.cb M src/mainboard/kontron/ktqm77/devicetree.cb M src/mainboard/lenovo/l520/devicetree.cb M src/mainboard/lenovo/s230u/devicetree.cb M src/mainboard/lenovo/t420/devicetree.cb M src/mainboard/lenovo/t420s/devicetree.cb M src/mainboard/lenovo/t430/devicetree.cb M src/mainboard/lenovo/t430s/devicetree.cb M src/mainboard/lenovo/t520/devicetree.cb M src/mainboard/lenovo/t530/devicetree.cb M src/mainboard/lenovo/x131e/devicetree.cb M src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb M src/mainboard/lenovo/x220/devicetree.cb M src/mainboard/lenovo/x230/devicetree.cb M src/mainboard/msi/ms7707/devicetree.cb M src/mainboard/roda/rv11/variants/rv11/devicetree.cb M src/mainboard/roda/rv11/variants/rw11/devicetree.cb M src/mainboard/samsung/lumpy/devicetree.cb M src/mainboard/samsung/stumpy/devicetree.cb M src/mainboard/sapphire/pureplatinumh61/devicetree.cb M src/mainboard/supermicro/x9sae/devicetree.cb M src/mainboard/supermicro/x9scl/devicetree.cb M src/northbridge/intel/sandybridge/Kconfig A src/northbridge/intel/sandybridge/chipset.cb 43 files changed, 74 insertions(+), 384 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/56912/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56912 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c5b6f25b779e28b6719cf70455ff0f1a916ad87 Gerrit-Change-Number: 56912 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: cpu/intel/haswell: Move chip_ops to cpu cluster
by Arthur Heymans (Code Review) 12 Nov '22

12 Nov '22

Attention is currently required from: Arthur Heymans, Raul Rangel, Tristan Corrick, Tim Wawrzynczak, Angel Pons, Alexander Couzens, Patrick Rudolph. Arthur Heymans has uploaded a new patch set (#13) to the change originally created by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/59314 ) Change subject: cpu/intel/haswell: Move chip_ops to cpu cluster ...................................................................... cpu/intel/haswell: Move chip_ops to cpu cluster The cpu cluster is always present and it's the proper device to contain the settings that need to be applied to all cpus. This makes it possible to remove the fake lapic from devicetrees. Change-Id: Ic449b2df8036e8c02b5559cca6b2e7479a70a786 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/haswell/acpi.c M src/cpu/intel/haswell/chip.h M src/cpu/intel/haswell/haswell_init.c M src/mainboard/asrock/b85m_pro4/devicetree.cb M src/mainboard/asrock/h81m-hds/devicetree.cb M src/mainboard/google/auron/devicetree.cb M src/mainboard/google/auron/variants/buddy/overridetree.cb M src/mainboard/google/auron/variants/samus/overridetree.cb M src/mainboard/google/beltino/devicetree.cb M src/mainboard/google/jecht/devicetree.cb M src/mainboard/google/slippy/devicetree.cb M src/mainboard/hp/folio_9480m/devicetree.cb M src/mainboard/intel/baskingridge/devicetree.cb M src/mainboard/intel/wtm2/devicetree.cb M src/mainboard/lenovo/haswell/variants/t440p/devicetree.cb M src/mainboard/lenovo/haswell/variants/w541/devicetree.cb M src/mainboard/msi/h81m-p33/devicetree.cb M src/mainboard/purism/librem_bdw/devicetree.cb M src/mainboard/supermicro/x10slm-f/devicetree.cb M src/northbridge/intel/haswell/northbridge.c M src/soc/intel/broadwell/northbridge.c 21 files changed, 72 insertions(+), 138 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/59314/13 -- To view, visit https://review.coreboot.org/c/coreboot/+/59314 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic449b2df8036e8c02b5559cca6b2e7479a70a786 Gerrit-Change-Number: 59314 Gerrit-PatchSet: 13 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: mb/emulation/qemu-q35: Fix running qemu-i386 with SMM
by Kyösti Mälkki (Code Review) 12 Nov '22

12 Nov '22

Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55138 ) Change subject: mb/emulation/qemu-q35: Fix running qemu-i386 with SMM ...................................................................... mb/emulation/qemu-q35: Fix running qemu-i386 with SMM Depending on whether qemu emulates an amd64 or i386 machine the SMM save state will differ. The smbase offsets are incompatible between those save states. TESTED: Both qemu-system-i386 and qemu-system-x86_64 (v7.0.50) have a working smihandler, ASEG and TSEG. Change-Id: Ic6994c8d6e10fd06655129dbd801f1f9d5fd639f Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55138 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/emulation/qemu-q35/cpu.c 1 file changed, 57 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Kyösti Mälkki: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/src/mainboard/emulation/qemu-q35/cpu.c b/src/mainboard/emulation/qemu-q35/cpu.c index fe3a571..2a2707a 100644 --- a/src/mainboard/emulation/qemu-q35/cpu.c +++ b/src/mainboard/emulation/qemu-q35/cpu.c @@ -2,9 +2,11 @@ #include <console/console.h> #include <cpu/x86/mp.h> +#include <stddef.h> #include <stdint.h> #include <cpu/intel/smm_reloc.h> #include <cpu/amd/amd64_save_state.h> +#include <cpu/x86/legacy_save_state.h> #include <mainboard/emulation/qemu-i440fx/fw_cfg.h> static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, @@ -31,19 +33,47 @@ * resides in the ramstage module. This occurs by trampolining from the default * SMRAM entry point to here. */ + +__packed union save_state { + amd64_smm_state_save_area_t amd64; + struct { + char _reserved[sizeof(amd64_smm_state_save_area_t) + - sizeof(legacy_smm_state_save_area_t)]; + legacy_smm_state_save_area_t legacy; + }; +}; + +_Static_assert(sizeof(union save_state) == sizeof(amd64_smm_state_save_area_t), + "Incorrect save state union size"); + +_Static_assert(offsetof(union save_state, amd64.smm_revision) + == offsetof(union save_state, legacy.smm_revision), + "Incompatible SMM save state revision offset"); + static void relocation_handler(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase) { - /* The em64t101 save state is sufficiently compatible with older - save states with regards of smbase, smm_revision. */ - amd64_smm_state_save_area_t *save_state; + union save_state *save_state = + (void *)(curr_smbase + SMM_DEFAULT_SIZE - sizeof(*save_state)); + u32 smbase = staggered_smbase; - save_state = (void *)(curr_smbase + SMM_DEFAULT_SIZE - sizeof(*save_state)); - save_state->smbase = smbase; + /* The SMM save state revision is always at a compatible offset */ + const u32 revision = save_state->legacy.smm_revision; + switch (revision) { + case 0x00020000: + save_state->legacy.smbase = smbase; + break; + case 0x00020064: + save_state->amd64.smbase = smbase; + break; + default: + printk(BIOS_ERR, "Unknown SMM revision 0x%x, not relocating SMM\n", revision); + return; + }; printk(BIOS_DEBUG, "In relocation handler: cpu %d\n", cpu); - printk(BIOS_DEBUG, "SMM revision: 0x%08x\n", save_state->smm_revision); + printk(BIOS_DEBUG, "SMM revision: 0x%08x\n", revision); printk(BIOS_DEBUG, "New SMBASE=0x%08x\n", smbase); } -- To view, visit https://review.coreboot.org/c/coreboot/+/55138 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6994c8d6e10fd06655129dbd801f1f9d5fd639f Gerrit-Change-Number: 55138 Gerrit-PatchSet: 9 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: arch/x86/mpspec.c: Drop weak write_smp_table()
by Kyösti Mälkki (Code Review) 12 Nov '22

12 Nov '22

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69489 ) Change subject: arch/x86/mpspec.c: Drop weak write_smp_table() ...................................................................... arch/x86/mpspec.c: Drop weak write_smp_table() Creating MP table is not useful when it does not include the interrupt routing entries. Change-Id: I1f38fb32a9436de64dfaf82e426cbd64b220ffa7 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/x86/mpspec.c 1 file changed, 13 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/69489/1 diff --git a/src/arch/x86/mpspec.c b/src/arch/x86/mpspec.c index 15b64b3..cbf6743 100644 --- a/src/arch/x86/mpspec.c +++ b/src/arch/x86/mpspec.c @@ -507,25 +507,3 @@ mc, smp_next_mpe_entry(mc)); return smp_next_mpe_entry(mc); } - -unsigned long __weak write_smp_table(unsigned long addr) -{ - struct mp_config_table *mc; - int isa_bus; - void *tmp, *v; - - v = smp_write_floating_table(addr, 0); - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc); - - smp_write_processors(mc); - - mptable_write_buses(mc, NULL, &isa_bus); - - mptable_lintsrc(mc, isa_bus); - tmp = mptable_finalize(mc); - printk(BIOS_INFO, "MPTABLE len: %d\n", (unsigned int)((uintptr_t)tmp - - (uintptr_t)v)); - return (unsigned long)tmp; -} -- To view, visit https://review.coreboot.org/c/coreboot/+/69489 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1f38fb32a9436de64dfaf82e426cbd64b220ffa7 Gerrit-Change-Number: 69489 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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[L] Change in coreboot[master]: drivers/generic/ioapic: Drop poor implementation
by Kyösti Mälkki (Code Review) 12 Nov '22

12 Nov '22

Attention is currently required from: Stefan Ott, Alexander Couzens. Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69488 ) Change subject: drivers/generic/ioapic: Drop poor implementation ...................................................................... drivers/generic/ioapic: Drop poor implementation This disables MP table generation for the affected boards since interrupt routing entries would now be completely missing. For integrated devices, routing information does not need to be defined in devicetree.cb since it can be derived from configuration registers. The write_smp_table implementation would skip writing any entry delivering to destination IOAPIC ID 0. This does not follow MP table specification. There were duplicate calls to register_new_ioapic_gsi0(), with another present under southbridge LPC device. Change-Id: I383d55ba2bc0800423617215e0bfdfad5136e9ac Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/Kconfig M src/arch/x86/mpspec.c D src/drivers/generic/ioapic/Kconfig D src/drivers/generic/ioapic/Makefile.inc D src/drivers/generic/ioapic/chip.h D src/drivers/generic/ioapic/ioapic.c M src/mainboard/lenovo/t400/Kconfig M src/mainboard/lenovo/t400/devicetree.cb M src/mainboard/lenovo/x200/Kconfig M src/mainboard/lenovo/x200/devicetree.cb M src/mainboard/roda/rk9/Kconfig M src/mainboard/roda/rk9/devicetree.cb M src/mainboard/samsung/lumpy/Kconfig M src/mainboard/samsung/lumpy/devicetree.cb 14 files changed, 27 insertions(+), 261 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/69488/1 diff --git a/src/Kconfig b/src/Kconfig index 08b2437..f30a1bb 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -795,9 +795,9 @@ menu "System tables" config GENERATE_MP_TABLE - prompt "Generate an MP table" if HAVE_MP_TABLE || DRIVERS_GENERIC_IOAPIC + prompt "Generate an MP table" if HAVE_MP_TABLE bool - default HAVE_MP_TABLE || DRIVERS_GENERIC_IOAPIC + default HAVE_MP_TABLE help Generate an MP table (conforming to the Intel MultiProcessor specification 1.4) for this board. diff --git a/src/arch/x86/mpspec.c b/src/arch/x86/mpspec.c index d94308e..15b64b3 100644 --- a/src/arch/x86/mpspec.c +++ b/src/arch/x86/mpspec.c @@ -9,7 +9,6 @@ #include <device/device.h> #include <device/path.h> #include <device/pci_ids.h> -#include <drivers/generic/ioapic/chip.h> #include <stdint.h> #include <string.h> @@ -509,34 +508,11 @@ return smp_next_mpe_entry(mc); } -static const struct device *find_next_ioapic(unsigned int last_ioapic_id) -{ - const struct device *dev; - const struct device *result = NULL; - unsigned int ioapic_id = MAX_APICS; - - for (dev = all_devices; dev; dev = dev->next) { - if (dev->path.type == DEVICE_PATH_IOAPIC && - dev->path.ioapic.ioapic_id > last_ioapic_id && - dev->path.ioapic.ioapic_id <= ioapic_id) { - result = dev; - } - } - return result; -} - unsigned long __weak write_smp_table(unsigned long addr) { - struct drivers_generic_ioapic_config *ioapic_config; struct mp_config_table *mc; - int isa_bus, pin, parentpin; - const struct device *dev; - const struct device *parent; - const struct device *oldparent; + int isa_bus; void *tmp, *v; - int isaioapic = -1, have_fixed_entries; - const struct pci_irq_info *pci_irq_info; - unsigned int ioapic_id = 0; v = smp_write_floating_table(addr, 0); mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); @@ -547,99 +523,6 @@ mptable_write_buses(mc, NULL, &isa_bus); - while ((dev = find_next_ioapic(ioapic_id))) { - ioapic_config = dev->chip_info; - if (!ioapic_config) { - printk(BIOS_ERR, "%s has no config, ignoring\n", - dev_path(dev)); - ioapic_id++; - continue; - } - - ioapic_id = dev->path.ioapic.ioapic_id; - smp_write_ioapic(mc, ioapic_id, - ioapic_config->version, - ioapic_config->base); - - if (ioapic_config->have_isa_interrupts) { - if (isaioapic >= 0) - printk(BIOS_ERR, - "More than one IOAPIC with ISA interrupts?\n"); - else - isaioapic = dev->path.ioapic.ioapic_id; - } - } - - if (isaioapic >= 0) { - /* Legacy Interrupts */ - printk(BIOS_DEBUG, "Writing ISA IRQs\n"); - mptable_add_isa_interrupts(mc, isa_bus, isaioapic, 0); - } - - for (dev = all_devices; dev; dev = dev->next) { - - if (!is_enabled_pci(dev)) - continue; - - have_fixed_entries = 0; - for (pin = 0; pin < 4; pin++) { - if (dev->pci_irq_info[pin].ioapic_dst_id) { - printk(BIOS_DEBUG, - "fixed IRQ entry for: %s: INT%c# -> IOAPIC %d PIN %d\n", - dev_path(dev), - pin + 'A', - dev->pci_irq_info[pin].ioapic_dst_id, - dev->pci_irq_info[pin].ioapic_irq_pin); - smp_write_intsrc(mc, mp_INT, - dev->pci_irq_info[pin].ioapic_flags, - dev->bus->secondary, - ((dev->path.pci.devfn & 0xf8) >> 1) - | pin, - dev->pci_irq_info[pin].ioapic_dst_id, - dev->pci_irq_info[pin].ioapic_irq_pin); - have_fixed_entries = 1; - } - } - - if (!have_fixed_entries) { - pin = (dev->path.pci.devfn & 7) % 4; - oldparent = parent = dev; - while ((parent = parent->bus->dev)) { - parentpin = (oldparent->path.pci.devfn >> 3) - + (oldparent->path.pci.devfn & 7); - parentpin += dev->path.pci.devfn & 7; - parentpin += dev->path.pci.devfn >> 3; - parentpin %= 4; - - pci_irq_info = &parent->pci_irq_info[parentpin]; - if (pci_irq_info->ioapic_dst_id) { - printk(BIOS_DEBUG, - "automatic IRQ entry for %s: INT%c# -> IOAPIC %d PIN %d\n", - dev_path(dev), pin + 'A', - pci_irq_info->ioapic_dst_id, - pci_irq_info->ioapic_irq_pin); - smp_write_intsrc(mc, mp_INT, - pci_irq_info->ioapic_flags, - dev->bus->secondary, - ((dev->path.pci.devfn & 0xf8) - >> 1) | pin, - pci_irq_info->ioapic_dst_id, - pci_irq_info->ioapic_irq_pin); - - break; - } - - if (parent->path.type == DEVICE_PATH_DOMAIN) { - printk(BIOS_WARNING, - "no IRQ found for %s\n", - dev_path(dev)); - break; - } - oldparent = parent; - } - } - } - mptable_lintsrc(mc, isa_bus); tmp = mptable_finalize(mc); printk(BIOS_INFO, "MPTABLE len: %d\n", (unsigned int)((uintptr_t)tmp - diff --git a/src/drivers/generic/ioapic/Kconfig b/src/drivers/generic/ioapic/Kconfig deleted file mode 100644 index f8b46cb..0000000 --- a/src/drivers/generic/ioapic/Kconfig +++ /dev/null @@ -1,2 +0,0 @@ -config DRIVERS_GENERIC_IOAPIC - bool diff --git a/src/drivers/generic/ioapic/Makefile.inc b/src/drivers/generic/ioapic/Makefile.inc deleted file mode 100644 index d34542b..0000000 --- a/src/drivers/generic/ioapic/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -ramstage-$(CONFIG_DRIVERS_GENERIC_IOAPIC) += ioapic.c diff --git a/src/drivers/generic/ioapic/chip.h b/src/drivers/generic/ioapic/chip.h deleted file mode 100644 index b59080a..0000000 --- a/src/drivers/generic/ioapic/chip.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef DRIVERS_GENERIC_IOAPIC_CHIP_H -#define DRIVERS_GENERIC_IOAPIC_CHIP_H - -typedef struct drivers_generic_ioapic_config { - u32 version; - u8 apicid; /* ignored */ - u8 have_isa_interrupts; - void *base; -} ioapic_config_t; - -#endif diff --git a/src/drivers/generic/ioapic/ioapic.c b/src/drivers/generic/ioapic/ioapic.c deleted file mode 100644 index 6abdff3..0000000 --- a/src/drivers/generic/ioapic/ioapic.c +++ /dev/null @@ -1,42 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <device/device.h> -#include "chip.h" -#include <arch/ioapic.h> - -static void ioapic_init(struct device *dev) -{ - struct drivers_generic_ioapic_config *config = dev->chip_info; - - if (!dev->enabled || !config) - return; - - register_new_ioapic_gsi0(config->base); -} - -static void ioapic_read_resources(struct device *dev) -{ - struct drivers_generic_ioapic_config *config = (struct drivers_generic_ioapic_config *)dev->chip_info; - struct resource *res; - - res = new_resource(dev, 0); - res->base = (resource_t)(uintptr_t)config->base; - res->size = 0x1000; - res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; -} - -static struct device_operations ioapic_operations = { - .read_resources = ioapic_read_resources, - .set_resources = noop_set_resources, - .init = ioapic_init, -}; - -static void enable_dev(struct device *dev) -{ - dev->ops = &ioapic_operations; -} - -struct chip_operations drivers_generic_ioapic_ops = { - CHIP_NAME("IOAPIC") - .enable_dev = enable_dev, -}; diff --git a/src/mainboard/lenovo/t400/Kconfig b/src/mainboard/lenovo/t400/Kconfig index f90ed53..7854bbf 100644 --- a/src/mainboard/lenovo/t400/Kconfig +++ b/src/mainboard/lenovo/t400/Kconfig @@ -12,8 +12,6 @@ select H8_HAS_BAT_THRESHOLDS_IMPL select BOARD_ROMSIZE_KB_8192 if !BOARD_LENOVO_R500 select BOARD_ROMSIZE_KB_4096 if BOARD_LENOVO_R500 - select DRIVERS_GENERIC_IOAPIC - select HAVE_MP_TABLE select HAVE_ACPI_TABLES select EC_ACPI select HAVE_OPTION_TABLE diff --git a/src/mainboard/lenovo/t400/devicetree.cb b/src/mainboard/lenovo/t400/devicetree.cb index 26fc899..57f1f37 100644 --- a/src/mainboard/lenovo/t400/devicetree.cb +++ b/src/mainboard/lenovo/t400/devicetree.cb @@ -34,7 +34,6 @@ device pci 01.0 on end # PCIe Bridge for discrete graphics device pci 02.0 on # VGA subsystemid 0x17aa 0x20e4 - ioapic_irq 0 INTA 0x10 end device pci 02.1 on subsystemid 0x17aa 0x20e4 @@ -85,27 +84,21 @@ device pci 19.0 on end # LAN device pci 1a.0 on # UHCI subsystemid 0x17aa 0x20f0 - ioapic_irq 0 INTA 0x10 end device pci 1a.1 on # UHCI subsystemid 0x17aa 0x20f0 - ioapic_irq 0 INTB 0x11 end device pci 1a.2 on # UHCI subsystemid 0x17aa 0x20f0 - ioapic_irq 0 INTC 0x12 end device pci 1a.7 on # EHCI subsystemid 0x17aa 0x20f1 - ioapic_irq 0 INTC 0x12 end device pci 1b.0 on # HD Audio subsystemid 0x17aa 0x20f2 - ioapic_irq 0 INTA 0x10 end device pci 1c.0 on # PCIe Port #1 subsystemid 0x17aa 0x20f3 # WWAN - ioapic_irq 0 INTA 0x10 end device pci 1c.1 on subsystemid 0x17aa 0x20f3 # WLAN @@ -121,19 +114,15 @@ device pci 1c.5 off end # PCIe Port #6 device pci 1d.0 on # UHCI subsystemid 0x17aa 0x20f0 - ioapic_irq 0 INTA 0x10 end device pci 1d.1 on # UHCI subsystemid 0x17aa 0x20f0 - ioapic_irq 0 INTB 0x11 end device pci 1d.2 on # UHCI subsystemid 0x17aa 0x20f0 - ioapic_irq 0 INTC 0x12 end device pci 1d.7 on # EHCI subsystemid 0x17aa 0x20f1 - ioapic_irq 0 INTA 0x10 end device pci 1e.0 on # PCI subsystemid 0x17aa 0x20f4 @@ -141,12 +130,6 @@ device pci 1f.0 on # LPC bridge subsystemid 0x17aa 0x20f5 - chip drivers/generic/ioapic - register "have_isa_interrupts" = "1" - register "base" = "(void *)0xfec00000" - device ioapic 0 on end - end - chip ec/lenovo/pmh7 device pnp ff.1 on end # dummy register "backlight_enable" = "0x01" @@ -217,7 +200,6 @@ end device pci 1f.2 on # SATA/IDE 1 subsystemid 0x17aa 0x20f8 - ioapic_irq 0 INTB 0x11 end device pci 1f.3 on end # SMBus device pci 1f.5 off end # SATA/IDE 2 diff --git a/src/mainboard/lenovo/x200/Kconfig b/src/mainboard/lenovo/x200/Kconfig index 812ceee..8669300 100644 --- a/src/mainboard/lenovo/x200/Kconfig +++ b/src/mainboard/lenovo/x200/Kconfig @@ -11,8 +11,6 @@ select H8_HAS_BAT_THRESHOLDS_IMPL select NO_UART_ON_SUPERIO select BOARD_ROMSIZE_KB_8192 - select DRIVERS_GENERIC_IOAPIC - select HAVE_MP_TABLE select HAVE_ACPI_TABLES select EC_ACPI select HAVE_OPTION_TABLE diff --git a/src/mainboard/lenovo/x200/devicetree.cb b/src/mainboard/lenovo/x200/devicetree.cb index ce183a7..059dc00 100644 --- a/src/mainboard/lenovo/x200/devicetree.cb +++ b/src/mainboard/lenovo/x200/devicetree.cb @@ -33,7 +33,6 @@ end # host bridge device pci 02.0 on # VGA subsystemid 0x17aa 0x20e4 - ioapic_irq 0 INTA 0x10 end device pci 02.1 on subsystemid 0x17aa 0x20e4 @@ -78,27 +77,21 @@ device pci 19.0 on end # LAN device pci 1a.0 on # UHCI subsystemid 0x17aa 0x20f0 - ioapic_irq 0 INTA 0x10 end device pci 1a.1 on # UHCI subsystemid 0x17aa 0x20f0 - ioapic_irq 0 INTB 0x11 end device pci 1a.2 on # UHCI subsystemid 0x17aa 0x20f0 - ioapic_irq 0 INTC 0x12 end device pci 1a.7 on # EHCI subsystemid 0x17aa 0x20f1 - ioapic_irq 0 INTC 0x12 end device pci 1b.0 on # HD Audio subsystemid 0x17aa 0x20f2 - ioapic_irq 0 INTA 0x10 end device pci 1c.0 on # PCIe Port #1 subsystemid 0x17aa 0x20f3 # WWAN - ioapic_irq 0 INTA 0x10 end device pci 1c.1 on subsystemid 0x17aa 0x20f3 # WLAN @@ -111,19 +104,15 @@ device pci 1c.5 off end # PCIe Port #6 device pci 1d.0 on # UHCI subsystemid 0x17aa 0x20f0 - ioapic_irq 0 INTA 0x10 end device pci 1d.1 on # UHCI subsystemid 0x17aa 0x20f0 - ioapic_irq 0 INTB 0x11 end device pci 1d.2 on # UHCI subsystemid 0x17aa 0x20f0 - ioapic_irq 0 INTC 0x12 end device pci 1d.7 on # EHCI subsystemid 0x17aa 0x20f1 - ioapic_irq 0 INTA 0x10 end device pci 1e.0 on # PCI subsystemid 0x17aa 0x20f4 @@ -131,12 +120,6 @@ device pci 1f.0 on # LPC bridge subsystemid 0x17aa 0x20f5 - chip drivers/generic/ioapic - register "have_isa_interrupts" = "1" - register "base" = "(void *)0xfec00000" - device ioapic 0 on end - end - chip ec/lenovo/pmh7 device pnp ff.1 on end # dummy register "backlight_enable" = "0x01" @@ -180,11 +163,9 @@ end device pci 1f.2 on # SATA/IDE 1 subsystemid 0x17aa 0x20f8 - ioapic_irq 0 INTB 0x11 end device pci 1f.3 on # SMBus subsystemid 0x17aa 0x20f9 - ioapic_irq 0 INTC 0x12 # eeprom, 8 virtual devices, same chip chip drivers/i2c/at24rf08c device i2c 54 on end diff --git a/src/mainboard/roda/rk9/Kconfig b/src/mainboard/roda/rk9/Kconfig index 7ce5e5e..ca0a369 100644 --- a/src/mainboard/roda/rk9/Kconfig +++ b/src/mainboard/roda/rk9/Kconfig @@ -8,8 +8,6 @@ select SOUTHBRIDGE_INTEL_I82801IX select SUPERIO_SMSC_LPC47N227 select BOARD_ROMSIZE_KB_4096 - select DRIVERS_GENERIC_IOAPIC - select HAVE_MP_TABLE select CARDBUS_PLUGIN_SUPPORT select HAVE_ACPI_TABLES select HAVE_ACPI_RESUME diff --git a/src/mainboard/roda/rk9/devicetree.cb b/src/mainboard/roda/rk9/devicetree.cb index cbbd4dd..fc3e636 100644 --- a/src/mainboard/roda/rk9/devicetree.cb +++ b/src/mainboard/roda/rk9/devicetree.cb @@ -24,7 +24,6 @@ subsystemid 0x4352 0x8986 device pci 00.0 on end # host bridge device pci 02.0 on # VGA - ioapic_irq 0 INTA 0x10 end device pci 02.1 on end # Display device pci 03.0 off end # ME @@ -70,61 +69,42 @@ device pci 19.0 off end # LAN device pci 1a.0 on # UHCI - ioapic_irq 0 INTA 0x10 end device pci 1a.1 on # UHCI - ioapic_irq 0 INTB 0x11 end device pci 1a.2 on # UHCI - ioapic_irq 0 INTC 0x12 end device pci 1a.7 on # EHCI - ioapic_irq 0 INTC 0x12 end device pci 1b.0 on # HD Audio - ioapic_irq 0 INTA 0x10 end device pci 1c.0 on # PCIe Port #1 - ioapic_irq 0 INTA 0x10 end device pci 1c.1 off end # PCIe Port #2 device pci 1c.2 off end # PCIe Port #3 device pci 1c.3 off end # PCIe Port #4 device pci 1c.4 on # PCIe Port #5 - ioapic_irq 0 INTA 0x10 device pci 00.0 on end # Realtek 8168B end device pci 1c.5 off end # PCIe Port #6 device pci 1d.0 on # UHCI - ioapic_irq 0 INTA 0x10 end device pci 1d.1 on # UHCI - ioapic_irq 0 INTB 0x11 end device pci 1d.2 on # UHCI - ioapic_irq 0 INTC 0x12 end device pci 1d.7 on # EHCI - ioapic_irq 0 INTA 0x10 end device pci 1e.0 on # PCI device pci 03.0 on # TI Cardbus - ioapic_irq 0 INTA 0x10 end device pci 03.1 on # TI Cardbus - ioapic_irq 0 INTB 0x11 end device pci 03.2 off end # TI FireWire OHC device pci 03.3 off end # unconnected FlashMedia device pci 03.4 off end # unconnected SD-Card end device pci 1f.0 on # LPC bridge - chip drivers/generic/ioapic - register "have_isa_interrupts" = "1" - register "base" = "(void *)0xfec00000" - device ioapic 0 on end - end - chip superio/smsc/lpc47n227 device pnp 2e.1 on # Parallel port io 0x60 = 0x378 @@ -143,10 +123,8 @@ end end device pci 1f.2 on # SATA/IDE 1 - ioapic_irq 0 INTB 0x11 end device pci 1f.3 on # SMBus - ioapic_irq 0 INTC 0x12 end device pci 1f.5 off end # SATA/IDE 2 device pci 1f.6 off end # Thermal diff --git a/src/mainboard/samsung/lumpy/Kconfig b/src/mainboard/samsung/lumpy/Kconfig index eb8643e..8d8f625 100644 --- a/src/mainboard/samsung/lumpy/Kconfig +++ b/src/mainboard/samsung/lumpy/Kconfig @@ -21,7 +21,6 @@ # LPC47N207 selected for external LPC card # not on board, should be made selectable. select SUPERIO_SMSC_LPC47N207 - select DRIVERS_GENERIC_IOAPIC select INTEL_INT15 select SANDYBRIDGE_VBOOT_IN_ROMSTAGE select HAVE_SPD_IN_CBFS diff --git a/src/mainboard/samsung/lumpy/devicetree.cb b/src/mainboard/samsung/lumpy/devicetree.cb index db25266..3ac73f2 100644 --- a/src/mainboard/samsung/lumpy/devicetree.cb +++ b/src/mainboard/samsung/lumpy/devicetree.cb @@ -32,10 +32,6 @@ end device domain 0 on - ioapic_irq 0 INTA 0x10 - ioapic_irq 0 INTB 0x11 - ioapic_irq 0 INTC 0x12 - ioapic_irq 0 INTD 0x13 subsystemid 0x1ae0 0xc000 inherit device pci 00.0 on end # host bridge device pci 02.0 on end # vga controller @@ -62,27 +58,22 @@ device pci 16.3 off end # Management Engine KT device pci 19.0 off end # Intel Gigabit Ethernet device pci 1a.0 on # USB2 EHCI #2 - ioapic_irq 0 INTA 0x11 end device pci 1b.0 on # High Definition Audio - ioapic_irq 0 INTA 0x16 end device pci 1c.0 on end # PCIe Port #1 (WLAN) device pci 1c.1 off end # PCIe Port #2 device pci 1c.2 off end # PCIe Port #3 device pci 1c.3 on # PCIe Port #4 (LAN) - # ioapic_irq 0 INTA 0x13 end device pci 1c.4 off end # PCIe Port #5 device pci 1c.5 off end # PCIe Port #6 device pci 1c.6 off end # PCIe Port #7 device pci 1c.7 off end # PCIe Port #8 device pci 1d.0 on # USB2 EHCI #1 - ioapic_irq 0 INTA 0x13 end device pci 1e.0 off end # PCI bridge device pci 1f.0 on # LPC bridge - ioapic_irq 0 INTA 0x10 chip superio/smsc/mec1308 device pnp 2e.1 on # PM1 io 0x60 = 0xb00 @@ -104,21 +95,13 @@ register "mailbox_port" = "0xa00" device pnp ff.1 off end end - - chip drivers/generic/ioapic - register "have_isa_interrupts" = "1" - register "base" = "(void *)0xfec00000" - device ioapic 0 on end - end chip drivers/pc80/tpm device pnp 0c31.0 on end end end device pci 1f.2 on # SATA Controller 1 - ioapic_irq 0 INTA 0x10 end device pci 1f.3 on # SMBus - ioapic_irq 0 INTC 0x17 end device pci 1f.5 off end # SATA Controller 2 device pci 1f.6 on end # Thermal -- To view, visit https://review.coreboot.org/c/coreboot/+/69488 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I383d55ba2bc0800423617215e0bfdfad5136e9ac Gerrit-Change-Number: 69488 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Stefan Ott <coreboot(a)desire.ch> Gerrit-Attention: Stefan Ott <coreboot(a)desire.ch> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[master]: mb/asus/p5gc-mx: Drop HAVE_MP_TABLE
by Kyösti Mälkki (Code Review) 12 Nov '22

12 Nov '22

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69487 ) Change subject: mb/asus/p5gc-mx: Drop HAVE_MP_TABLE ...................................................................... mb/asus/p5gc-mx: Drop HAVE_MP_TABLE The weak implementation of write_smp_table() is not useful without DRIVERS_GENERIC_IOAPIC and related entries in devicetree.cb. No interrupt routing entries are present in the generated MP table. Change-Id: Ib50a7656cef40d0d3ffcc408cc0858c1dae7b9e5 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/asus/p5gc-mx/Kconfig 1 file changed, 15 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/69487/1 diff --git a/src/mainboard/asus/p5gc-mx/Kconfig b/src/mainboard/asus/p5gc-mx/Kconfig index bbf72fc..4f49dbb 100644 --- a/src/mainboard/asus/p5gc-mx/Kconfig +++ b/src/mainboard/asus/p5gc-mx/Kconfig @@ -11,7 +11,6 @@ select SUPERIO_WINBOND_W83627DHG select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT - select HAVE_MP_TABLE select HAVE_ACPI_TABLES select HAVE_ACPI_RESUME select BOARD_ROMSIZE_KB_512 -- To view, visit https://review.coreboot.org/c/coreboot/+/69487 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib50a7656cef40d0d3ffcc408cc0858c1dae7b9e5 Gerrit-Change-Number: 69487 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

1 0

[M] Change in coreboot[master]: drivers/generic/ioapic: Use register_new_ioapic_gsi0()
by Kyösti Mälkki (Code Review) 12 Nov '22

12 Nov '22

Attention is currently required from: Stefan Ott, Alexander Couzens, Patrick Rudolph. Hello Stefan Ott, build bot (Jenkins), Arthur Heymans, Alexander Couzens, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55315 to look at the new patch set (#11). Change subject: drivers/generic/ioapic: Use register_new_ioapic_gsi0() ...................................................................... drivers/generic/ioapic: Use register_new_ioapic_gsi0() The only IOAPIC in the system will have IOAPIC ID 0. The mechanism itself is flawed and redundant. The mapping of integrated PCI devices' INTx pins to IOAPIC pins is dependent of configuration registers and needs not appear in the devicetree.cb files at all. Change-Id: I4b03d32fa16fb9eb8a035e58bb7e3e027904f076 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/drivers/generic/ioapic/chip.h M src/drivers/generic/ioapic/ioapic.c M src/mainboard/lenovo/t400/devicetree.cb M src/mainboard/lenovo/x200/devicetree.cb M src/mainboard/roda/rk9/devicetree.cb M src/mainboard/samsung/lumpy/devicetree.cb 6 files changed, 75 insertions(+), 58 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/55315/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/55315 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4b03d32fa16fb9eb8a035e58bb7e3e027904f076 Gerrit-Change-Number: 55315 Gerrit-PatchSet: 11 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Stefan Ott <coreboot(a)desire.ch> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Stefan Ott <coreboot(a)desire.ch> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit November 2022