coreboot-gerrit November 2022

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: soc/intel/cmn/block/acpi: enable BERT table without crashlog
by Arthur Heymans (Code Review) 12 Nov '22

12 Nov '22

Attention is currently required from: Jonathan Zhang, Tim Chu. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68878 ) Change subject: soc/intel/cmn/block/acpi: enable BERT table without crashlog ...................................................................... Patch Set 2: Code-Review-1 (1 comment) File src/soc/intel/common/block/acpi/acpi_bert.c: https://review.coreboot.org/c/coreboot/+/68878/comment/e0e1d7da_565ef6f3 PS2, Line 9: : #if (CONFIG(SOC_INTEL_CRASHLOG)) This should not be needed. Split off things that are only needed for crashlog in a separate function and use C instead of CPP to guard it. The compiler will optimize it out it will still be build. -- To view, visit https://review.coreboot.org/c/coreboot/+/68878 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I323ca889eef2b246fc4e062582d2d11b4213316f Gerrit-Change-Number: 68878 Gerrit-PatchSet: 2 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Sat, 12 Nov 2022 08:03:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/xeon_sp: lockdown LPC configuration
by Arthur Heymans (Code Review) 12 Nov '22

12 Nov '22

Attention is currently required from: Marc Jones, Anjaneya "Reddy" Chagam, Jonathan Zhang, Johnny Lin, Christian Walter, Tim Chu. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68876 ) Change subject: soc/intel/xeon_sp: lockdown LPC configuration ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68876 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3e3edc63c0d43b11b0999239ea49304772a05275 Gerrit-Change-Number: 68876 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Sat, 12 Nov 2022 08:00:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: drivers/ocp: add VPD processing framework
by Arthur Heymans (Code Review) 12 Nov '22

12 Nov '22

Attention is currently required from: Marc Jones, Jonathan Zhang, Johnny Lin, Paul Menzel, Johnny Li, Shuming Chu (Shuming), Angel Pons, Tim Chu. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68784 ) Change subject: drivers/ocp: add VPD processing framework ...................................................................... Patch Set 2: (1 comment) File src/drivers/ocp/vpd/Makefile.inc: https://review.coreboot.org/c/coreboot/+/68784/comment/e43993e2_e8746d1e PS2, Line 3: smm-$(C It's not a good idea to fetch VPD in the smihandler. Do you really need this? Also where is this Kconfig option defined? I don't see it in this patch. -- To view, visit https://review.coreboot.org/c/coreboot/+/68784 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I705bea348b1611f25ccbd798b77cfee22ec30f0f Gerrit-Change-Number: 68784 Gerrit-PatchSet: 2 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Johnny Li <johnny_li(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Attention: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Johnny Li <johnny_li(a)wistron.corp-partner.google.com> Gerrit-Attention: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Sat, 12 Nov 2022 08:00:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: cpu/x86/smm: Enable setting SMM console log level from mainboard
by Arthur Heymans (Code Review) 12 Nov '22

12 Nov '22

Attention is currently required from: Marc Jones, Patrick Rudolph, Johnny Lin, Rocky Phagura, Jingle Hsu, Angel Pons, Morgan Jang, Kyösti Mälkki. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49460 ) Change subject: cpu/x86/smm: Enable setting SMM console log level from mainboard ...................................................................... Patch Set 21: (2 comments) File src/cpu/x86/smm/smm_module_handler.c: https://review.coreboot.org/c/coreboot/+/49460/comment/3be69463_ecfc4c2e PS21, Line 19: u32 smm_log_level; This adds a global variable without using it. File src/cpu/x86/smm/smm_module_loader.c: https://review.coreboot.org/c/coreboot/+/49460/comment/03ea5357_ea8215ba PS21, Line 389: u32 __weak mainboard_set_smm_log_level(void) { return 0; } This is guarded behind CONSOLE_OVERRIDE_LOGLEVEL. Is a weak function needed? -- To view, visit https://review.coreboot.org/c/coreboot/+/49460 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I81722a4f1bf75ec942cc06e403ad702dfe938e71 Gerrit-Change-Number: 49460 Gerrit-PatchSet: 21 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Rocky Phagura Gerrit-Reviewer: Rocky Phagura <rphagura(a)fb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Rocky Phagura <rphagura(a)fb.com> Gerrit-Attention: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Sat, 12 Nov 2022 07:49:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: include/cper.h: Add CPER Memory Error Section definitions
by Arthur Heymans (Code Review) 12 Nov '22

12 Nov '22

Attention is currently required from: Johnny Lin, Angel Pons, Shuming Chu (Shuming), Tim Chu. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69198 ) Change subject: include/cper.h: Add CPER Memory Error Section definitions ...................................................................... Patch Set 3: Code-Review-1 (2 comments) File src/include/cper.h: https://review.coreboot.org/c/coreboot/+/69198/comment/8b5b143b_ae3e3646 PS3, Line 400: enum cper_err_code mem_err_type; > Will this work properly? Not sure if the size of enum types is well-defined. It won't. This needs to be u8 according to the spec. sizeof(enum) == sizeof(int). https://review.coreboot.org/c/coreboot/+/69198/comment/6aefb1af_fa959efd PS3, Line 405: __packed This is not needed. All entries seem aligned. -- To view, visit https://review.coreboot.org/c/coreboot/+/69198 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0a165350a16a4cbe4033a3e7c43fa23a5b27c44b Gerrit-Change-Number: 69198 Gerrit-PatchSet: 3 Gerrit-Owner: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Sat, 12 Nov 2022 07:43:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: cpu/intel/socket_*: Clean up Kconfig files
by Elyes Haouas (Code Review) 12 Nov '22

12 Nov '22

Attention is currently required from: Stefan Ott, Nico Huber, Angel Pons, Arthur Heymans, Kyösti Mälkki, Alexander Couzens. Hello Stefan Ott, build bot (Jenkins), Angel Pons, Arthur Heymans, Kyösti Mälkki, Alexander Couzens, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69447 to look at the new patch set (#4). Change subject: cpu/intel/socket_*: Clean up Kconfig files ...................................................................... cpu/intel/socket_*: Clean up Kconfig files Remove SSE when SSE is already selected by supported CPUs. Add "config SOCKET_SPECIFIC_OPTIONS" section to socket_p/Kconfig. Change-Id: If2265ac716e90720e7ccc550239737d40c2f7a0a Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/cpu/intel/socket_441/Kconfig M src/cpu/intel/socket_BGA956/Kconfig M src/cpu/intel/socket_p/Kconfig 3 files changed, 23 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/69447/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/69447 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If2265ac716e90720e7ccc550239737d40c2f7a0a Gerrit-Change-Number: 69447 Gerrit-PatchSet: 4 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Stefan Ott <coreboot(a)desire.ch> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Stefan Ott <coreboot(a)desire.ch> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: cpu/intel/socket_*: Clean up Kconfig files
by Elyes Haouas (Code Review) 12 Nov '22

12 Nov '22

Attention is currently required from: Stefan Ott, Nico Huber, Angel Pons, Arthur Heymans, Kyösti Mälkki, Alexander Couzens. Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69447 ) Change subject: cpu/intel/socket_*: Clean up Kconfig files ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/69447/comment/14424e28_5849d034 PS3, Line 10: Move MAX_CPUS to mainboards. > > Set the max CPUs in socket Kconfig doesn't make sense! > > Why? The sockets you changed in this patch are well-defined: > > * BGA956 is for low-power soldered-down Core 2 CPUs, which are paired with a GS45 northbridge (low-power variant of GM45). There are no quad-core CPUs in this package, so MAX_CPUS=2 > * FCBGA559 is Pineview, but the CPU model is shared with Diamondville. These CPUs are dual-core with HyperThreading, so MAX_CPUS=4 > * Socket P supports Core 2 Duo and (sometimes) Core 2 Quad CPUs, so MAX_CPUS=4 > > For sockets like LGA775, the northbridges specify MAX_CPUS. Ironically enough, MAX_CPUS=4 for both of them. > > > Each socket can support only one CPU , however, a mainboard can have more than 1 socket (when the northbridge support it). > > Mainboards with more than 1 socket? None of the platforms affected by this change support more than 1 socket. It's also that can be addressed with a MAX_SOCKET Kconfig. So the right place for MAX_CPUS should be at cpu/intel/model_*, isn't it? -- To view, visit https://review.coreboot.org/c/coreboot/+/69447 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If2265ac716e90720e7ccc550239737d40c2f7a0a Gerrit-Change-Number: 69447 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Stefan Ott <coreboot(a)desire.ch> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Stefan Ott <coreboot(a)desire.ch> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Comment-Date: Sat, 12 Nov 2022 07:04:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: cpu/intel/socket_mPGA604: Drop non-working SSE2 disablement
by Kyösti Mälkki (Code Review) 12 Nov '22

12 Nov '22

Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69443 ) Change subject: cpu/intel/socket_mPGA604: Drop non-working SSE2 disablement ...................................................................... cpu/intel/socket_mPGA604: Drop non-working SSE2 disablement The disablement of SSE2 was not honoured since there is explicit select under CPU_INTEL_MODEL_F2X. The removed commentary originates probably from ROMCC romstage implementation. Change-Id: I7d9ac007406a82c498f3ed23568e2ff064504983 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69443 Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/socket_mPGA604/Kconfig 1 file changed, 20 insertions(+), 8 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Elyes Haouas: Looks good to me, approved Arthur Heymans: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/src/cpu/intel/socket_mPGA604/Kconfig b/src/cpu/intel/socket_mPGA604/Kconfig index 7b08699..12c8e37 100644 --- a/src/cpu/intel/socket_mPGA604/Kconfig +++ b/src/cpu/intel/socket_mPGA604/Kconfig @@ -7,20 +7,12 @@ def_bool y select CPU_INTEL_MODEL_F2X select MMX - select SSE select UDELAY_TSC select TSC_MONOTONIC_TIMER select SIPI_VECTOR_IN_ROM select CPU_INTEL_COMMON select CPU_INTEL_COMMON_TIMEBASE -# mPGA604 are usually Intel Netburst CPUs which should have SSE2 -# but the ramtest.c code on the Dell S1850 seems to choke on -# enabling it, so disable it for now. -config SSE2 - bool - default n - config DCACHE_RAM_BASE hex default 0xfefc0000 -- To view, visit https://review.coreboot.org/c/coreboot/+/69443 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7d9ac007406a82c498f3ed23568e2ff064504983 Gerrit-Change-Number: 69443 Gerrit-PatchSet: 3 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: util/amdfwtool: Remove duplicate ALIGN and ARRAY_SIZE definition
by Elyes Haouas (Code Review) 12 Nov '22

12 Nov '22

Attention is currently required from: Martin Roth, Karthik Ramasubramanian. Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69439 ) Change subject: util/amdfwtool: Remove duplicate ALIGN and ARRAY_SIZE definition ...................................................................... Patch Set 1: -Code-Review -- To view, visit https://review.coreboot.org/c/coreboot/+/69439 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iabff06fa47a1badb0ce9815261117916664f3e03 Gerrit-Change-Number: 69439 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Sat, 12 Nov 2022 05:06:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: lib/fmap.c: Show error on fmd flash size mismatch with Kconfig
by Martin L Roth (Code Review) 12 Nov '22

12 Nov '22

Martin L Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69486 ) Change subject: lib/fmap.c: Show error on fmd flash size mismatch with Kconfig ...................................................................... lib/fmap.c: Show error on fmd flash size mismatch with Kconfig It's quite surprising to change the rom size in Kconfig and not have it change the ROM size of the output, but if an fmap file is present, the output size depends on the fmap, not the Kconfig file size. It seems like more needs to be done, but this is at least a first step in helping to eliminate the confusion. Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: I5ed8e09125567f7c04baca292f102dacee974144 --- M src/lib/fmap.c 1 file changed, 23 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/69486/1 diff --git a/src/lib/fmap.c b/src/lib/fmap.c index 3889dd5..fbbd92f 100644 --- a/src/lib/fmap.c +++ b/src/lib/fmap.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <assert.h> #include <boot_device.h> #include <cbmem.h> #include <console/console.h> @@ -19,6 +20,11 @@ static int fmap_print_once; static struct region_device fmap_cache; +#ifdef FMAP_SECTION_FLASH_SIZE +_Static_assert(CONFIG_ROM_SIZE == FMAP_SECTION_FLASH_SIZE, + "Kconfig ROM size != FMAP rom size. Check your FMD file."); +#endif + #define print_once(...) do { \ if (!fmap_print_once) \ printk(__VA_ARGS__); \ -- To view, visit https://review.coreboot.org/c/coreboot/+/69486 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ed8e09125567f7c04baca292f102dacee974144 Gerrit-Change-Number: 69486 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit November 2022