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Change subject: mb/google/brya/var/gaelin: Configure devicetree settings
......................................................................
Patch Set 5: -Code-Review
(1 comment)
Patchset:
PS5:
still issue with code indentation and alignment
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HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32882
Change subject: src/Kconfig: Move DRAM section to 'Devices' menu
......................................................................
src/Kconfig: Move DRAM section to 'Devices' menu
This moves DRAM to 'Devices' menu and allow to change default
DIMM_MAX value if needed.
Change-Id: I7aa5436c6ff5fef53fde2081e902d793f3581c1e
Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr>
---
M src/Kconfig
M src/device/Kconfig
2 files changed, 24 insertions(+), 25 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/32882/1
diff --git a/src/Kconfig b/src/Kconfig
index 2c9dc4a..d30aa99 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -1158,31 +1158,6 @@
implies configurability usually found on SoCs, particularly the
ability to control internal pull resistors.
-config GENERIC_SPD_BIN
- bool
- help
- If enabled, add support for adding spd.hex files in cbfs as spd.bin
- and locating it runtime to load SPD. Additionally provide provision to
- fetch SPD over SMBus.
-
-config DIMM_MAX
- int
- default 4
- help
- Total number of memory DIMM slots available on motherboard.
- It is multiplication of number of channel to number of DIMMs per
- channel
-
-config DIMM_SPD_SIZE
- int
- default 256
- help
- Total SPD size that will be used for DIMM.
- Ex: DDR3 256, DDR4 512.
-
-config SPD_READ_BY_WORD
- bool
-
config BOOTBLOCK_CUSTOM
# To be selected by arch, SoC or mainboard if it does not want use the normal
# src/lib/bootblock.c#main() C entry point.
diff --git a/src/device/Kconfig b/src/device/Kconfig
index 0539062..d4cacec 100644
--- a/src/device/Kconfig
+++ b/src/device/Kconfig
@@ -681,5 +681,29 @@
be useful for debugging or on platforms where a driver for the real
I2C controller is not (yet) available. The platform code needs to
provide bindings to manually toggle I2C lines.
+config GENERIC_SPD_BIN
+ bool
+ help
+ If enabled, add support for adding spd.hex files in cbfs as spd.bin
+ and locating it runtime to load SPD. Additionally provide provision to
+ fetch SPD over SMBus.
+
+config DIMM_MAX
+ int "Total number of memory DIMM slots"
+ default 4
+ help
+ Total number of memory DIMM slots available on motherboard.
+ It is multiplication of number of channel to number of DIMMs per
+ channel
+
+config DIMM_SPD_SIZE
+ int
+ default 256
+ help
+ Total SPD size that will be used for DIMM.
+ Ex: DDR3 256, DDR4 512.
+
+config SPD_READ_BY_WORD
+ bool
endmenu
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Change subject: mb/google/brya/var/gaelin: Configure devicetree settings
......................................................................
Patch Set 5: Code-Review+2
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Change subject: testing/Makefile.inc: Fix removing clang builds
......................................................................
Patch Set 1:
(1 comment)
File util/testing/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/69568/comment/9f0ce78b_4a139145
PS1, Line 126: chromeos-clang
maybe this one ?
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Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69023 )
Change subject: drivers/pc80/tpm: probe for TPM family of a device
......................................................................
Patch Set 3:
(1 comment)
File src/drivers/pc80/tpm/tis.c:
https://review.coreboot.org/c/coreboot/+/69023/comment/cdf5512b_a4b189ab
PS2, Line 435: return TPM_DRIVER_ERR;
> It is a big change and I might have got it wrong. Michał wrote in https://ticket.coreboot. […]
Indeed, I said there would be ambiguity with the probe function as it is now in upstream as it merely probes VID/DID and checks with the vendor/device list. E.g. we have Infineon chips with the same IDs in TPM2 and TPM1.2 table, so interface detection was simply done by Kconfig selection (TPM1 or TPM2) which is very wrong. The probe function should probe the interface capability register. Matching VID/DID should be done only for informational purposes to report the TPM vendor and model in human-readable form, and that's it, nothing more, nothing less. As long as a specification-conforming TPM is detected (i.e. TPM returns valid data in interface capability registers, by valid one should understand values anticipated by the specification) coreboot should try to use it. IMO if TPM Startup command fails, only then coreboot should not try to use the TPM.
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Change subject: testing/Makefile.inc: Fix removing clang builds
......................................................................
Patch Set 1: Code-Review+2
(1 comment)
Patchset:
PS1:
Assuming it works
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Change subject: drivers/vpd, cpu/x86/smm: Add VPD support for SMM
......................................................................
Patch Set 4:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/67092/comment/c5d0f334_897b4ef9
PS4, Line 9: The main purpose is to be able to dynamically configure system during
: SMM boot time via VPD.
> > It's safer to pass each config variable ex. […]
There is one RAS related config in our private repo https://review.coreboot.org/c/coreboot-spr-sp/+/66858
Besides that config, so far no other variables needed for SMM runtime config yet.
On the other hand, since RAS SMM codes won't be upstreamed, I feel that we can keep such kinds of customizations in the private repo.
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Change subject: util/testing: Buildtest with clang
......................................................................
Patch Set 47:
(1 comment)
File util/testing/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/62173/comment/e097b9c6_c926509c
PS39, Line 86: chromeos-clang $(COREBOOT_BUILD_DIR)/default-clang
> Aw these are not right. I guess that's why the builders overflow...
CB:69568
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