coreboot-gerrit November 2022

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[S] Change in coreboot[master]: testing/Makefile.inc: Fix removing clang builds
by Arthur Heymans (Code Review) 14 Nov '22

14 Nov '22

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69568 ) Change subject: testing/Makefile.inc: Fix removing clang builds ...................................................................... Patch Set 1: -Code-Review -- To view, visit https://review.coreboot.org/c/coreboot/+/69568 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia52ca92f22f02a3b91244093ac6a769e6b3b2eb3 Gerrit-Change-Number: 69568 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Mon, 14 Nov 2022 11:17:06 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: testing/Makefile.inc: Fix removing clang builds
by Arthur Heymans (Code Review) 14 Nov '22

14 Nov '22

Hello Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69568 to look at the new patch set (#2). Change subject: testing/Makefile.inc: Fix removing clang builds ...................................................................... testing/Makefile.inc: Fix removing clang builds The directory names were wrong. Change-Id: Ia52ca92f22f02a3b91244093ac6a769e6b3b2eb3 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M util/testing/Makefile.inc 1 file changed, 14 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/69568/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69568 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia52ca92f22f02a3b91244093ac6a769e6b3b2eb3 Gerrit-Change-Number: 69568 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: testing/Makefile.inc: Fix removing clang builds
by Arthur Heymans (Code Review) 14 Nov '22

14 Nov '22

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69568 ) Change subject: testing/Makefile.inc: Fix removing clang builds ...................................................................... Patch Set 1: Code-Review-2 (1 comment) File util/testing/Makefile.inc: https://review.coreboot.org/c/coreboot/+/69568/comment/bce25bc5_0fd57186 PS1, Line 100: chromeos_clang This needs to be synced with L126 -- To view, visit https://review.coreboot.org/c/coreboot/+/69568 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia52ca92f22f02a3b91244093ac6a769e6b3b2eb3 Gerrit-Change-Number: 69568 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Mon, 14 Nov 2022 11:11:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: cbmem_top_chipset: Change the return value to uintptr_t
by Jakub Czapiga (Code Review) 14 Nov '22

14 Nov '22

Attention is currently required from: Philipp Hug, Matt DeVillier, Angel Pons, Andrey Petrov, ron minnich, Elyes Haouas, Felix Held. Jakub Czapiga has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69078 ) Change subject: cbmem_top_chipset: Change the return value to uintptr_t ...................................................................... Patch Set 10: (2 comments) File src/soc/qualcomm/qcs405/cbmem.c: https://review.coreboot.org/c/coreboot/+/69078/comment/cf0427a7_ab0e911f PS10, Line 7: (uintptr_t) nit: Is this cast really requires here? Also in other files? File src/soc/samsung/exynos5250/cbmem.c: https://review.coreboot.org/c/coreboot/+/69078/comment/038feee8_8be07476 PS10, Line 8: (uintptr_t) nit: same as in case of previous literal casts. Also applies to other returns like this one. -- To view, visit https://review.coreboot.org/c/coreboot/+/69078 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I93645ef5dd270905ce421e68e342aff4c331eae6 Gerrit-Change-Number: 69078 Gerrit-PatchSet: 10 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 14 Nov 2022 11:10:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/meteorlake: Log CSE RO write protection info for MTL
by build bot (Jenkins) (Code Review) 14 Nov '22

14 Nov '22

Attention is currently required from: Tarun Tuli, Subrata Banik. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69571 ) Change subject: soc/intel/meteorlake: Log CSE RO write protection info for MTL ...................................................................... Patch Set 1: (2 comments) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-163612): https://review.coreboot.org/c/coreboot/+/69571/comment/399027d1_c5ce9603 PS1, Line 14: Port of commit abe0d81 (soc/intel/alderlake: Log CSE RO write protection info for ADL) Possible unwrapped commit description (prefer a maximum 72 chars per line) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-163612): https://review.coreboot.org/c/coreboot/+/69571/comment/4c57bdfc_831e4013 PS1, Line 14: Port of commit abe0d81 (soc/intel/alderlake: Log CSE RO write protection info for ADL) Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'commit abe0d810f009 ("soc/intel/alderlake: Log CSE RO write protection info for ADL")' -- To view, visit https://review.coreboot.org/c/coreboot/+/69571 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idb072a873a8b8323532799f5fc64f995c9f0a604 Gerrit-Change-Number: 69571 Gerrit-PatchSet: 1 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Mon, 14 Nov 2022 11:06:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/meteorlake: Log CSE RO write protection info for MTL
by Kapil Porwal (Code Review) 14 Nov '22

14 Nov '22

Kapil Porwal has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69571 ) Change subject: soc/intel/meteorlake: Log CSE RO write protection info for MTL ...................................................................... soc/intel/meteorlake: Log CSE RO write protection info for MTL The patch logs CSE RO's write protection information for Alder Lake platform. As part of write protection information, coreboot logs status on CSE RO write protection and range. Also, logs error message if EOM is disabled, and write protection for CSE RO is not enabled. Port of commit abe0d81 (soc/intel/alderlake: Log CSE RO write protection info for ADL) BUG=none TEST=Verify the write protection details on google/rex. Excerpt from google/rex coreboot log: [DEBUG] ME: WP for RO is enabled : YES [DEBUG] ME: RO write protection scope - Start=0x4000, End=0x396FFF Signed-off-by: Kapil Porwal <kapilporwal(a)google.com> Change-Id: Idb072a873a8b8323532799f5fc64f995c9f0a604 --- M src/soc/intel/meteorlake/me.c 1 file changed, 47 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/69571/1 diff --git a/src/soc/intel/meteorlake/me.c b/src/soc/intel/meteorlake/me.c index ea94902..31b09da 100644 --- a/src/soc/intel/meteorlake/me.c +++ b/src/soc/intel/meteorlake/me.c @@ -2,6 +2,7 @@ #include <bootstate.h> #include <intelblocks/cse.h> +#include <intelblocks/spi.h> #include <console/console.h> #include <soc/me.h> #include <stdint.h> @@ -90,6 +91,25 @@ } __packed fields; }; +static void log_me_ro_write_protection_info(bool mfg_mode) +{ + bool cse_ro_wp_en = is_spi_wp_cse_ro_en(); + + printk(BIOS_DEBUG, "ME: WP for RO is enabled : %s\n", + cse_ro_wp_en ? "YES" : "NO"); + + if (cse_ro_wp_en) { + uint32_t base, limit; + spi_get_wp_cse_ro_range(&base, &limit); + printk(BIOS_DEBUG, "ME: RO write protection scope - Start=0x%X, End=0x%X\n", + base, limit); + } + + /* If EOM is disabled, but CSE RO is not write protected, log error */ + if (!mfg_mode && !cse_ro_wp_en) + printk(BIOS_ERR, "ME: Write protection for CSE RO is not enabled\n"); +} + static void dump_me_status(void *unused) { union me_hfsts1 hfsts1; @@ -161,6 +181,9 @@ hfsts6.fields.cpu_debug_disable ? "YES" : "NO"); printk(BIOS_DEBUG, "ME: TXT Support : %s\n", hfsts6.fields.txt_support ? "YES" : "NO"); + + if (CONFIG(SOC_INTEL_CSE_LITE_SKU)) + log_me_ro_write_protection_info(!!hfsts1.fields.mfg_mode); } BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_EXIT, print_me_fw_version, NULL); -- To view, visit https://review.coreboot.org/c/coreboot/+/69571 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idb072a873a8b8323532799f5fc64f995c9f0a604 Gerrit-Change-Number: 69571 Gerrit-PatchSet: 1 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/intel/meteorlake: Add Meteor Lake MCH device ID
by Subrata Banik (Code Review) 14 Nov '22

14 Nov '22

Attention is currently required from: Tarun Tuli, Jamie Ryu, Ravishankar Sarawadi, Kapil Porwal, Sridhar Siricilla. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69560 ) Change subject: soc/intel/meteorlake: Add Meteor Lake MCH device ID ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/69560/comment/ae87519e_e8fdb255 PS1, Line 9: Add Meteor Lake MCH device ID 0x7d15. may be add the doc number and don't need to say the ID again. -- To view, visit https://review.coreboot.org/c/coreboot/+/69560 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If46b01910239173cd74bf6eebc69a81291b6e15a Gerrit-Change-Number: 69560 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Comment-Date: Mon, 14 Nov 2022 11:06:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/common/block/pcr: Remove unneded 'esle'
by HAOUAS Elyes (Code Review) 14 Nov '22

14 Nov '22

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33336 Change subject: soc/intel/common/block/pcr: Remove unneded 'esle' ...................................................................... soc/intel/common/block/pcr: Remove unneded 'esle' 'else' is not needed after a 'break' or 'return'. Change-Id: Ib3371ef6edb85a47ed734dd2ff9ce94008aa4e65 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/intel/common/block/pcr/pcr.c 1 file changed, 3 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/33336/1 diff --git a/src/soc/intel/common/block/pcr/pcr.c b/src/soc/intel/common/block/pcr/pcr.c index 4a35a03..f3971c2 100644 --- a/src/soc/intel/common/block/pcr/pcr.c +++ b/src/soc/intel/common/block/pcr/pcr.c @@ -394,10 +394,9 @@ break; } return 0; - } else { - printk(BIOS_ERR, "SBI Failure: Transaction Status = %x\n", - *response); - return -1; } + printk(BIOS_ERR, "SBI Failure: Transaction Status = %x\n", + *response); + return -1; } #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/33336 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib3371ef6edb85a47ed734dd2ff9ce94008aa4e65 Gerrit-Change-Number: 33336 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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[L] Change in coreboot[master]: src: Move common IA-32 MSRs to <cpu/x86/msr.h>
by Elyes Haouas (Code Review) 14 Nov '22

14 Nov '22

Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28752 ) Change subject: src: Move common IA-32 MSRs to <cpu/x86/msr.h> ...................................................................... Patch Set 13: (3 comments) File src/cpu/intel/model_6fx/model_6fx_init.c: https://review.coreboot.org/c/coreboot/+/28752/comment/aac6ebf0_b89352fe PS2, Line 62: #define IA32_PECI_CTL 0x5a0 > This MSR is not documented, so I don't know if it is specific to 6fx or not. Done File src/include/cpu/x86/msr.h: https://review.coreboot.org/c/coreboot/+/28752/comment/d97f9db1_79318543 PS11, Line 25: #define IA32_BIOS_UPDT_TRIG 0x79 : #define IA32_BIOS_SIGN_ID 0x8b > sounds good to me. Ack File src/include/cpu/x86/msr.h: https://review.coreboot.org/c/coreboot/+/28752/comment/99aa5b31_f2affafd PS2, Line 126: #endif > Done Done -- To view, visit https://review.coreboot.org/c/coreboot/+/28752 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ida7f2d608c55796abf9452f190a58802e498302d Gerrit-Change-Number: 28752 Gerrit-PatchSet: 13 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Mon, 14 Nov 2022 11:04:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com> Comment-In-Reply-To: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: cbmem_top: Change the return value to uintptr_t
by Jakub Czapiga (Code Review) 14 Nov '22

14 Nov '22

Attention is currently required from: Raul Rangel, Jeff Daly, Jonathan Zhang, Matt DeVillier, Julius Werner, Angel Pons, Arthur Heymans, Andrey Petrov, Lance Zhao, Jason Glenesk, Johnny Lin, Tim Wawrzynczak, Christian Walter, Vanessa Eusebio, Fred Reitberger, Elyes Haouas, Tim Chu, Felix Held. Jakub Czapiga has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69163 ) Change subject: cbmem_top: Change the return value to uintptr_t ...................................................................... Patch Set 7: (7 comments) Patchset: PS7: I do not see what this patch aims to achieve. Casts are removed from platform code, but are introduced in common (src/lib/) code. CB:69078 makes sense to me, but this patch not so much. File src/drivers/mrc_cache/mrc_cache.c: https://review.coreboot.org/c/coreboot/+/69163/comment/899ae2b6_457ecd0b PS5, Line 663: (void *)cbmem_entry_start(to_be_updated) + Misaligned code File src/include/imd.h: https://review.coreboot.org/c/coreboot/+/69163/comment/b6707dbc_73514df2 PS7, Line 112: uintptr_t imd_entry_at(const struct imd *imd, const struct imd_entry *entry); It should not be changed as it returns `pointer`. `uintptr_t` is not appropriate here. File src/lib/imd.c: https://review.coreboot.org/c/coreboot/+/69163/comment/99ca385b_32f980a1 PS7, Line 14: uintptr_t relative_pointer(void *base, ssize_t offset) I think it should remain `void *`. This function has `pointer` in it's name. https://review.coreboot.org/c/coreboot/+/69163/comment/5c6f3c97_08b81734 PS7, Line 267: relative_pointer(imdr_root(imdr), e->start_offset); `(uintptr_t)` will be needed here after reverting above. https://review.coreboot.org/c/coreboot/+/69163/comment/89657e34_7e32b7a6 PS7, Line 568: uintptr_t imd_entry_at(const struct imd *imd, const struct imd_entry *entry) As in header file File src/lib/imd_cbmem.c: https://review.coreboot.org/c/coreboot/+/69163/comment/6ef7b49f_e5268d81 PS7, Line 143: uintptr_t cbmem_add(u32 id, u64 size) This also should remain `void *` -- To view, visit https://review.coreboot.org/c/coreboot/+/69163 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib757c0548f6f643747ba8d70228b3d6dfa5182cd Gerrit-Change-Number: 69163 Gerrit-PatchSet: 7 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Lance Zhao Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 14 Nov 2022 11:04:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit November 2022