coreboot-gerrit November 2022

coreboot-gerrit@coreboot.org

1 participants
7286 discussions

[M] Change in coreboot[master]: drivers/i2c/rv3028c7: Add ACPI generation callbacks
by Jan Samek (Code Review) 14 Nov '22

14 Nov '22

Attention is currently required from: Werner Zeh. Jan Samek has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69543 ) Change subject: drivers/i2c/rv3028c7: Add ACPI generation callbacks ...................................................................... Patch Set 1: (1 comment) File src/drivers/i2c/rv3028c7/chip.h: https://review.coreboot.org/c/coreboot/+/69543/comment/f759c6f0_913f6f99 PS1, Line 38: unsigned int bus_speed; /* Bus clock in Hz (default 400 kHz) */ I'm in doubt here whether this default is the "datasheet default" or the default in rv3028c7.c, which is 100 kHz. The same situation as in the RX6110 RTC driver. Seems confusing. -- To view, visit https://review.coreboot.org/c/coreboot/+/69543 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3b8cf5c8dc551439755992ff05b6693e91cc3f21 Gerrit-Change-Number: 69543 Gerrit-PatchSet: 1 Gerrit-Owner: Jan Samek <jan.samek(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Mon, 14 Nov 2022 12:45:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: soc/intel/ehl: Add EHL MDIO operation
by Arthur Heymans (Code Review) 14 Nov '22

14 Nov '22

Attention is currently required from: Mario Scheithauer, Angel Pons, Lean Sheng Tan, Werner Zeh. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69383 ) Change subject: soc/intel/ehl: Add EHL MDIO operation ...................................................................... Patch Set 7: (2 comments) File src/soc/intel/elkhartlake/mdio.c: https://review.coreboot.org/c/coreboot/+/69383/comment/6b87c28c_44d5d4a3 PS7, Line 68: == CB_ERR nit: != CB_SUCCESS is preferable as it handles the other options in enum cb_err (even though they are not used in this case) https://review.coreboot.org/c/coreboot/+/69383/comment/b4054528_b2cc3780 PS7, Line 82: .read_resources = noop_read_resources, : .set_resources = noop_set_resources, > > This should not be a PCI device, it's a mdio device. Are you sure that this will overwrite PCI device_operations? > > It is, you are even finding PCI BARs to get bases for MDIO ops. > > void mdio_dev_enable(struct device *dev) > { > dev->ops = &mdio_dev_ops; > } > > will override the PCI driver ops. See my suggestion in tsn_gbe.c file -- To view, visit https://review.coreboot.org/c/coreboot/+/69383 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5d1b9dd2f2ba8c18291fff314c13f0c3851784aa Gerrit-Change-Number: 69383 Gerrit-PatchSet: 7 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Mon, 14 Nov 2022 12:43:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Mario Scheithauer <mario.scheithauer(a)siemens.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: util/cbfstool: Add a new mechanism to provide a memory mapped
by Paul Menzel (Code Review) 14 Nov '22

14 Nov '22

Attention is currently required from: Nico Huber, Maximilian Brune, Julius Werner, Arthur Heymans. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68160 ) Change subject: util/cbfstool: Add a new mechanism to provide a memory mapped ...................................................................... Patch Set 6: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/68160/comment/6eb85bad_ff8cee83 PS6, Line 7: mapped map -- To view, visit https://review.coreboot.org/c/coreboot/+/68160 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I38ab4c369704497f711e14ecda3ff3a8cdc0d089 Gerrit-Change-Number: 68160 Gerrit-PatchSet: 6 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Mon, 14 Nov 2022 12:43:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: soc/intel/ehl: Add EHL MDIO operation
by Arthur Heymans (Code Review) 14 Nov '22

14 Nov '22

Attention is currently required from: Mario Scheithauer, Angel Pons, Lean Sheng Tan, Werner Zeh. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69383 ) Change subject: soc/intel/ehl: Add EHL MDIO operation ...................................................................... Patch Set 7: (2 comments) File src/soc/intel/elkhartlake/mdio.c: https://review.coreboot.org/c/coreboot/+/69383/comment/ba336400_354c0a5e PS7, Line 82: .read_resources = noop_read_resources, : .set_resources = noop_set_resources, > This should not be a PCI device, it's a mdio device. Are you sure that this will overwrite PCI device_operations? It is, you are even finding PCI BARs to get bases for MDIO ops. void mdio_dev_enable(struct device *dev) { dev->ops = &mdio_dev_ops; } will override the PCI driver ops. File src/soc/intel/elkhartlake/tsn_gbe.c: https://review.coreboot.org/c/coreboot/+/69383/comment/fa192634_6b8df15c PS7, Line 93: .init = gbe_tsn_init, : }; maybe add .mdio_ops here? -- To view, visit https://review.coreboot.org/c/coreboot/+/69383 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5d1b9dd2f2ba8c18291fff314c13f0c3851784aa Gerrit-Change-Number: 69383 Gerrit-PatchSet: 7 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Mon, 14 Nov 2022 12:40:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Mario Scheithauer <mario.scheithauer(a)siemens.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: drivers/i2c/rv3028c7: Add ACPI generation callbacks
by Jan Samek (Code Review) 14 Nov '22

14 Nov '22

Jan Samek has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69543 ) Change subject: drivers/i2c/rv3028c7: Add ACPI generation callbacks ...................................................................... drivers/i2c/rv3028c7: Add ACPI generation callbacks Added ACPI generation callback to the driver after obtaining the ACPI HID "MCRY3028" for this device from Microcrystal AG (VID: "MCRY"). Also added I2C bus speed field to the device config structure, which is a required ACPI entry. BUG=none TEST=Disassemble the SSDT table and see whether the device entry "MC28" is generated correctly. Also check whether the RV3028 driver in Linux (drivers/rtc/rtc-rv-3028.c) is bound correctly after adding an ACPI match table to it containing the HID (kernel patch is pending). Change-Id: I3b8cf5c8dc551439755992ff05b6693e91cc3f21 Signed-off-by: Jan Samek <jan.samek(a)siemens.com> --- M src/drivers/i2c/rv3028c7/chip.h M src/drivers/i2c/rv3028c7/rv3028c7.c M src/drivers/i2c/rv3028c7/rv3028c7.h 3 files changed, 89 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/69543/1 diff --git a/src/drivers/i2c/rv3028c7/chip.h b/src/drivers/i2c/rv3028c7/chip.h index 0ac4005..f55a108 100644 --- a/src/drivers/i2c/rv3028c7/chip.h +++ b/src/drivers/i2c/rv3028c7/chip.h @@ -35,6 +35,7 @@ }; struct drivers_i2c_rv3028c7_config { + unsigned int bus_speed; /* Bus clock in Hz (default 400 kHz) */ unsigned char user_weekday; /* User day of the week to set */ unsigned char user_day; /* User day to set */ unsigned char user_month; /* User month to set */ diff --git a/src/drivers/i2c/rv3028c7/rv3028c7.c b/src/drivers/i2c/rv3028c7/rv3028c7.c index e7e3b47..49c7bc2 100644 --- a/src/drivers/i2c/rv3028c7/rv3028c7.c +++ b/src/drivers/i2c/rv3028c7/rv3028c7.c @@ -1,5 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpi_device.h> +#include <acpi/acpigen.h> #include <commonlib/bsd/bcd.h> #include <console/console.h> #include <delay.h> @@ -176,11 +178,71 @@ } } +#if CONFIG(HAVE_ACPI_TABLES) +static void rv3028c7_fill_ssdt(const struct device *dev) +{ + const char *scope = acpi_device_scope(dev); + struct drivers_i2c_rv3028c7_config *config = dev->chip_info; + enum i2c_speed bus_speed; + + if (!scope) + return; + + switch (config->bus_speed) { + case I2C_SPEED_STANDARD: + case I2C_SPEED_FAST: + bus_speed = config->bus_speed; + break; + default: + bus_speed = I2C_SPEED_STANDARD; + printk(BIOS_INFO, "%s: Bus speed unsupported, fall back to %d kHz!\n", + dev_path(dev), bus_speed / 1000); + break; + } + + struct acpi_i2c i2c = { + .address = dev->path.i2c.device, + .mode_10bit = dev->path.i2c.mode_10bit, + .speed = bus_speed, + .resource = scope, + }; + + /* Device */ + acpigen_write_scope(scope); + acpigen_write_device(acpi_device_name(dev)); + acpigen_write_name_string("_HID", RV3028C7_HID_NAME); + acpigen_write_name_string("_DDN", RV3028C7_HID_DESC); + acpigen_write_STA(acpi_device_status(dev)); + + /* Resources */ + acpigen_write_name("_CRS"); + + acpigen_write_resourcetemplate_header(); + acpi_device_write_i2c(&i2c); + acpigen_write_resourcetemplate_footer(); + + acpigen_pop_len(); /* Device */ + acpigen_pop_len(); /* Scope */ + + printk(BIOS_INFO, "%s: %s at %s\n", acpi_device_path(dev), dev->chip_ops->name, + dev_path(dev)); +} + +static const char *rv3028c7_acpi_name(const struct device *dev) +{ + return RV3028C7_ACPI_NAME; +} +#endif + static struct device_operations rv3028c7_ops = { .read_resources = noop_read_resources, .set_resources = noop_set_resources, .init = rtc_init, .final = rtc_final, +#if CONFIG(HAVE_ACPI_TABLES) + .acpi_name = rv3028c7_acpi_name, + .acpi_fill_ssdt = rv3028c7_fill_ssdt, +#endif }; static void rtc_enable(struct device *dev) diff --git a/src/drivers/i2c/rv3028c7/rv3028c7.h b/src/drivers/i2c/rv3028c7/rv3028c7.h index 55617a7..b1f9971 100644 --- a/src/drivers/i2c/rv3028c7/rv3028c7.h +++ b/src/drivers/i2c/rv3028c7/rv3028c7.h @@ -3,6 +3,10 @@ #ifndef _I2C_RV3028C7_H_ #define _I2C_RV3028C7_H_ +#define RV3028C7_ACPI_NAME "MC28" +#define RV3028C7_HID_NAME "MCRY3028" +#define RV3028C7_HID_DESC "Real Time Clock" + /* Register layout */ #define SECOND_REG 0x00 #define MINUTE_REG 0x01 -- To view, visit https://review.coreboot.org/c/coreboot/+/69543 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3b8cf5c8dc551439755992ff05b6693e91cc3f21 Gerrit-Change-Number: 69543 Gerrit-PatchSet: 1 Gerrit-Owner: Jan Samek <jan.samek(a)siemens.com> Gerrit-MessageType: newchange

1 0

[M] Change in coreboot[master]: soc/intel/ehl: Add EHL MDIO operation
by Mario Scheithauer (Code Review) 14 Nov '22

14 Nov '22

Attention is currently required from: Angel Pons, Arthur Heymans, Lean Sheng Tan, Werner Zeh. Mario Scheithauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69383 ) Change subject: soc/intel/ehl: Add EHL MDIO operation ...................................................................... Patch Set 7: (1 comment) File src/soc/intel/elkhartlake/mdio.c: https://review.coreboot.org/c/coreboot/+/69383/comment/a89e5e04_df328b5d PS7, Line 82: .read_resources = noop_read_resources, : .set_resources = noop_set_resources, > This will override the PCI device_operations? Would it make sense to export mdio_ops (give it better […] This should not be a PCI device, it's a mdio device. Are you sure that this will overwrite PCI device_operations? -- To view, visit https://review.coreboot.org/c/coreboot/+/69383 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5d1b9dd2f2ba8c18291fff314c13f0c3851784aa Gerrit-Change-Number: 69383 Gerrit-PatchSet: 7 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Mon, 14 Nov 2022 12:33:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: soc/intel/meteorlake: Log CSE RO write protection info for MTL
by Subrata Banik (Code Review) 14 Nov '22

14 Nov '22

Attention is currently required from: Tarun Tuli, Kapil Porwal, Sridhar Siricilla. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69571 ) Change subject: soc/intel/meteorlake: Log CSE RO write protection info for MTL ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/meteorlake/me.c: https://review.coreboot.org/c/coreboot/+/69571/comment/fdb328d5_62dc72f2 PS2, Line 186: hfsts1.fields.mfg_mode > I'm updating the EOM status code for MTL, kapil can bank on it. SG. Thanks. -- To view, visit https://review.coreboot.org/c/coreboot/+/69571 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idb072a873a8b8323532799f5fc64f995c9f0a604 Gerrit-Change-Number: 69571 Gerrit-PatchSet: 2 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Comment-Date: Mon, 14 Nov 2022 12:29:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: soc/intel/meteorlake: Log CSE RO write protection info for MTL
by Sridhar Siricilla (Code Review) 14 Nov '22

14 Nov '22

Attention is currently required from: Tarun Tuli, Subrata Banik, Kapil Porwal. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69571 ) Change subject: soc/intel/meteorlake: Log CSE RO write protection info for MTL ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/meteorlake/me.c: https://review.coreboot.org/c/coreboot/+/69571/comment/6625c316_4f02a7d6 PS2, Line 186: hfsts1.fields.mfg_mode > > mfg_mode alone doesn't represent the end of manufacturing status. […] I'm updating the EOM status code for MTL, kapil can bank on it. -- To view, visit https://review.coreboot.org/c/coreboot/+/69571 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idb072a873a8b8323532799f5fc64f995c9f0a604 Gerrit-Change-Number: 69571 Gerrit-PatchSet: 2 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Mon, 14 Nov 2022 12:26:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: soc/intel/meteorlake: Log CSE RO write protection info for MTL
by Subrata Banik (Code Review) 14 Nov '22

14 Nov '22

Attention is currently required from: Tarun Tuli, Kapil Porwal, Sridhar Siricilla. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69571 ) Change subject: soc/intel/meteorlake: Log CSE RO write protection info for MTL ...................................................................... Patch Set 2: (2 comments) Patchset: PS2: @Kapil, can u please add a topic as in `backporting_from_adl` File src/soc/intel/meteorlake/me.c: https://review.coreboot.org/c/coreboot/+/69571/comment/9b21367c_bd33ab64 PS2, Line 186: hfsts1.fields.mfg_mode > mfg_mode alone doesn't represent the end of manufacturing status. Please refer patch:https://review.coreboot.org/c/coreboot/+/69324 for reference I guess this is just the backport of the ADL CL as mentioned in the commit msg and we might need to again intercept the CB:69324 once done. -- To view, visit https://review.coreboot.org/c/coreboot/+/69571 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idb072a873a8b8323532799f5fc64f995c9f0a604 Gerrit-Change-Number: 69571 Gerrit-PatchSet: 2 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Comment-Date: Mon, 14 Nov 2022 12:18:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: soc/intel/meteorlake: Log CSE RO write protection info for MTL
by Subrata Banik (Code Review) 14 Nov '22

14 Nov '22

Attention is currently required from: Tarun Tuli, Kapil Porwal. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69571 ) Change subject: soc/intel/meteorlake: Log CSE RO write protection info for MTL ...................................................................... Patch Set 1: Code-Review+2 (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/69571/comment/d4e37653_fce19f0a PS1, Line 9: Alder Meteor Lake https://review.coreboot.org/c/coreboot/+/69571/comment/2c56141a_12aeb7e8 PS1, Line 14: abe0d81 use longer (12+ digit ) -- To view, visit https://review.coreboot.org/c/coreboot/+/69571 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idb072a873a8b8323532799f5fc64f995c9f0a604 Gerrit-Change-Number: 69571 Gerrit-PatchSet: 1 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Mon, 14 Nov 2022 12:15:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2022