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Change subject: soc/intel/ehl: Add EHL MDIO operation
......................................................................
Patch Set 7:
(1 comment)
File src/soc/intel/elkhartlake/mdio.c:
https://review.coreboot.org/c/coreboot/+/69383/comment/d8481af4_9e3b853a
PS7, Line 82: .read_resources = noop_read_resources,
: .set_resources = noop_set_resources,
This will override the PCI device_operations? Would it make sense to export mdio_ops (give it better name like ehl_mdio_ops) and hook it up statically in ehl code instead of setting the full ops pointer at runtime?
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Change subject: src/device + util/sconfig: Introduce new device 'mdio'
......................................................................
Patch Set 5:
(1 comment)
File src/include/device/path.h:
https://review.coreboot.org/c/coreboot/+/69382/comment/444be0a0_c7152492
PS5, Line 117: struct mdio_path {
: unsigned int addr;
: };
> Indeed gcc checks for the vaid range and complains if it does not fir:
>
> build/mainboard/siemens/mc_ehl/static.c:1021:51: error: unsigned conversion from 'int' to 'unsigned char:5' changes value from '33' to '1' [-Werror=overflow]
> .path = {.type=DEVICE_PATH_MDIO,{.mdio={ .addr = 0x21 }}},
>
> I can push a follow-up patch once this train is in.
Cool! A follow-up is fine.
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Change subject: testing/Makefile.inc: Fix removing clang builds
......................................................................
Patch Set 2: Code-Review+2
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Change subject: soc/intel/meteorlake: Log CSE RO write protection info for MTL
......................................................................
Patch Set 2:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/69571/comment/f161bfcd_0495405c
PS2, Line 9: The patch logs CSE RO's write protection information for Alder Lake
Meteor
https://review.coreboot.org/c/coreboot/+/69571/comment/88d58fd2_720fc4ba
PS2, Line 21: YES
How did you test this? Did you enable SPI protection through MFIT and test the coreboot on Rex?
File src/soc/intel/meteorlake/me.c:
https://review.coreboot.org/c/coreboot/+/69571/comment/c685a5b6_a0b5ae79
PS2, Line 186: hfsts1.fields.mfg_mode
mfg_mode alone doesn't represent the end of manufacturing status. Please refer patch:https://review.coreboot.org/c/coreboot/+/69324 for reference
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Change subject: src/device + util/sconfig: Introduce new device 'mdio'
......................................................................
Patch Set 5:
(1 comment)
File src/include/device/path.h:
https://review.coreboot.org/c/coreboot/+/69382/comment/9d4ef38c_c6213fe6
PS5, Line 117: struct mdio_path {
: unsigned int addr;
: };
> I will give it a try and let you know.
Indeed gcc checks for the vaid range and complains if it does not fir:
build/mainboard/siemens/mc_ehl/static.c:1021:51: error: unsigned conversion from 'int' to 'unsigned char:5' changes value from '33' to '1' [-Werror=overflow]
.path = {.type=DEVICE_PATH_MDIO,{.mdio={ .addr = 0x21 }}},
I can push a follow-up patch once this train is in.
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Hello Hung-Te Lin, build bot (Jenkins), Philipp Hug, Jakub Czapiga, Matt DeVillier, Julius Werner, Angel Pons, Andrey Petrov, ron minnich, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/69078
to look at the new patch set (#11).
Change subject: cbmem_top_chipset: Change the return value to uintptr_t
......................................................................
cbmem_top_chipset: Change the return value to uintptr_t
Get rid of a lot of casts.
Change-Id: I93645ef5dd270905ce421e68e342aff4c331eae6
Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr>
---
M src/drivers/amd/agesa/romstage.c
M src/drivers/intel/fsp2_0/cbmem.c
M src/include/cbmem.h
M src/lib/imd_cbmem.c
M src/mainboard/emulation/qemu-aarch64/cbmem.c
M src/mainboard/emulation/qemu-armv7/cbmem.c
M src/mainboard/emulation/qemu-i440fx/memmap.c
M src/mainboard/emulation/qemu-power8/cbmem.c
M src/mainboard/emulation/qemu-power9/cbmem.c
M src/northbridge/intel/e7505/memmap.c
M src/northbridge/intel/gm45/memmap.c
M src/northbridge/intel/haswell/memmap.c
M src/northbridge/intel/i440bx/memmap.c
M src/northbridge/intel/i945/memmap.c
M src/northbridge/intel/ironlake/memmap.c
M src/northbridge/intel/pineview/memmap.c
M src/northbridge/intel/sandybridge/memmap.c
M src/northbridge/intel/x4x/memmap.c
M src/soc/amd/stoneyridge/memmap.c
M src/soc/cavium/cn81xx/cbmem.c
M src/soc/intel/baytrail/memmap.c
M src/soc/intel/braswell/memmap.c
M src/soc/intel/broadwell/memmap.c
M src/soc/mediatek/common/cbmem.c
M src/soc/nvidia/tegra124/cbmem.c
M src/soc/nvidia/tegra210/cbmem.c
M src/soc/nvidia/tegra210/ramstage.c
M src/soc/qualcomm/ipq40xx/cbmem.c
M src/soc/qualcomm/ipq806x/cbmem.c
M src/soc/qualcomm/qcs405/cbmem.c
M src/soc/qualcomm/sc7180/cbmem.c
M src/soc/qualcomm/sc7280/cbmem.c
M src/soc/rockchip/common/cbmem.c
M src/soc/samsung/exynos5250/cbmem.c
M src/soc/samsung/exynos5420/cbmem.c
M src/soc/sifive/fu540/cbmem.c
M src/soc/ti/am335x/cbmem.c
M src/soc/ucb/riscv/cbmem.c
M tests/lib/coreboot_table-test.c
M tests/lib/imd_cbmem-test.c
40 files changed, 98 insertions(+), 90 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/69078/11
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Change subject: cbmem_top_chipset: Change the return value to uintptr_t
......................................................................
Patch Set 10:
(3 comments)
Patchset:
PS10:
Thank you
File src/soc/qualcomm/qcs405/cbmem.c:
https://review.coreboot.org/c/coreboot/+/69078/comment/821ef904_30b56301
PS10, Line 7: (uintptr_t)
> nit: Is this cast really requires here? Also in other files?
Done
File src/soc/samsung/exynos5250/cbmem.c:
https://review.coreboot.org/c/coreboot/+/69078/comment/b55cbf82_09cc1ebe
PS10, Line 8: (uintptr_t)
> nit: same as in case of previous literal casts. Also applies to other returns like this one.
Done
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Hello Tarun Tuli, Subrata Banik,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/69571
to look at the new patch set (#2).
Change subject: soc/intel/meteorlake: Log CSE RO write protection info for MTL
......................................................................
soc/intel/meteorlake: Log CSE RO write protection info for MTL
The patch logs CSE RO's write protection information for Alder Lake
platform. As part of write protection information, coreboot logs status
on CSE RO write protection and range. Also, logs error message if EOM
is disabled, and write protection for CSE RO is not enabled.
Port of commit abe0d810f009 ("soc/intel/alderlake: Log CSE RO write
protection info for ADL").
BUG=none
TEST=Verify the write protection details on google/rex.
Excerpt from google/rex coreboot log:
[DEBUG] ME: WP for RO is enabled : YES
[DEBUG] ME: RO write protection scope - Start=0x4000, End=0x396FFF
Signed-off-by: Kapil Porwal <kapilporwal(a)google.com>
Change-Id: Idb072a873a8b8323532799f5fc64f995c9f0a604
---
M src/soc/intel/meteorlake/me.c
1 file changed, 48 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/69571/2
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Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69568 )
Change subject: testing/Makefile.inc: Fix removing clang builds
......................................................................
Patch Set 2: Code-Review-2
(1 comment)
File util/testing/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/69568/comment/278448fa_35eee4d6
PS1, Line 100: chromeos_clang
> This needs to be synced with L126
Done
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