coreboot-gerrit November 2022

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[S] Change in coreboot[master]: soc/intel/meteorlake: Implement report_cache_info() function
by Dinesh Gehlot (Code Review) 15 Nov '22

15 Nov '22

Dinesh Gehlot has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69681 ) Change subject: soc/intel/meteorlake: Implement report_cache_info() function ...................................................................... soc/intel/meteorlake: Implement report_cache_info() function Make use of deterministic cache helper functions from Meteor Lake SoC code to print useful information during boot as below: Cache: Level 3: Associativity = 12 Partitions = 1 Line Size = 64 Sets = 32768 Cache size = 24 MiB Change-Id: I561658c8da0136d6c3d9578f22f5d320e542457d --- M src/soc/intel/meteorlake/bootblock/report_platform.c 1 file changed, 33 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/69681/1 diff --git a/src/soc/intel/meteorlake/bootblock/report_platform.c b/src/soc/intel/meteorlake/bootblock/report_platform.c index 63f1771..510e3b7 100644 --- a/src/soc/intel/meteorlake/bootblock/report_platform.c +++ b/src/soc/intel/meteorlake/bootblock/report_platform.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <commonlib/helpers.h> #include <console/console.h> #include <cpu/cpu.h> #include <cpu/intel/cpu_ids.h> @@ -64,6 +65,21 @@ return pci_read_config16(dev, PCI_DEVICE_ID); } +static void report_cache_info(void) +{ + int cache_level = CACHE_L3; + struct cpu_cache_info info; + + if (!fill_cpu_cache_info(cache_level, &info)) + return; + + printk(BIOS_INFO, "Cache: Level %d: ", cache_level); + printk(BIOS_INFO, "Associativity = %zd Partitions = %zd Line Size = %zd Sets = %zd\n", + info.num_ways, info.physical_partitions, info.line_size, info.num_sets); + + printk(BIOS_INFO, "Cache size = %zu MiB\n", get_cache_size(&info)/MiB); +} + static void report_cpu_info(void) { u32 i, cpu_id, cpu_feature_flag; @@ -94,6 +110,8 @@ printk(BIOS_DEBUG, "CPU: AES %ssupported, TXT %ssupported, VT %ssupported\n", mode[aes], mode[txt], mode[vt]); + + report_cache_info(); } static void report_mch_info(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/69681 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I561658c8da0136d6c3d9578f22f5d320e542457d Gerrit-Change-Number: 69681 Gerrit-PatchSet: 1 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/intel/meteorlake: Add Meteor Lake MCH device ID
by Subrata Banik (Code Review) 15 Nov '22

15 Nov '22

Attention is currently required from: Tarun Tuli, Jamie Ryu, Ravishankar Sarawadi, Kapil Porwal, Sridhar Siricilla. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69560 ) Change subject: soc/intel/meteorlake: Add Meteor Lake MCH device ID ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/69560/comment/70e04737_6dc8bfe0 PS1, Line 9: Add Meteor Lake MCH device ID 0x7d15. > I didn't find DCL indicating the "MCH device ID 0x7d15". I can share offline when it is out. […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/69560 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If46b01910239173cd74bf6eebc69a81291b6e15a Gerrit-Change-Number: 69560 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Comment-Date: Wed, 16 Nov 2022 06:07:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/meteorlake: Add Meteor Lake MCH device ID
by Subrata Banik (Code Review) 15 Nov '22

15 Nov '22

Attention is currently required from: Tarun Tuli, Jamie Ryu, Ravishankar Sarawadi, Kapil Porwal, Sridhar Siricilla. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69560 ) Change subject: soc/intel/meteorlake: Add Meteor Lake MCH device ID ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69560 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If46b01910239173cd74bf6eebc69a81291b6e15a Gerrit-Change-Number: 69560 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Comment-Date: Wed, 16 Nov 2022 06:06:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/meteorlake: Skip setting D0I3 bit for HECI devices
by Subrata Banik (Code Review) 15 Nov '22

15 Nov '22

Attention is currently required from: Tarun Tuli, Kapil Porwal. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69680 ) Change subject: soc/intel/meteorlake: Skip setting D0I3 bit for HECI devices ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69680 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1c3765ce41f192ab5f5ff176e0a2b49b312d18d2 Gerrit-Change-Number: 69680 Gerrit-PatchSet: 1 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Wed, 16 Nov 2022 06:06:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/meteorlake: Check MANUF_LOCK when logging manufacturing mode
by Subrata Banik (Code Review) 15 Nov '22

15 Nov '22

Attention is currently required from: Tarun Tuli, Jamie Ryu, Ravishankar Sarawadi, Sridhar Siricilla. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69578 ) Change subject: soc/intel/meteorlake: Check MANUF_LOCK when logging manufacturing mode ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69578 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I495a7d8730716fc92e8c57b2caef73e8bb44d30b Gerrit-Change-Number: 69578 Gerrit-PatchSet: 4 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Comment-Date: Wed, 16 Nov 2022 06:05:09 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[master]: [WIP]aopen/dxplplusu: Support SMM_ASEG and SMM_TSEG
by build bot (Jenkins) (Code Review) 15 Nov '22

15 Nov '22

Attention is currently required from: Angel Pons, Kyösti Mälkki, Patrick Rudolph, Elyes Haouas. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61517 ) Change subject: [WIP]aopen/dxplplusu: Support SMM_ASEG and SMM_TSEG ...................................................................... Patch Set 5: (2 comments) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-163755): https://review.coreboot.org/c/coreboot/+/61517/comment/e02f223e_ce74d1e9 PS5, Line 13: 'occuring' may be misspelled - perhaps 'occurring'? File src/northbridge/intel/e7505/memmap.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-163755): https://review.coreboot.org/c/coreboot/+/61517/comment/ac2e59bb_9782a277 PS5, Line 40: return 512 *KiB; need consistent spacing around '*' (ctx:WxV) -- To view, visit https://review.coreboot.org/c/coreboot/+/61517 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If20a7092117612a1a9e25eb6ac480e105acd57d7 Gerrit-Change-Number: 61517 Gerrit-PatchSet: 5 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Wed, 16 Nov 2022 05:15:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in coreboot[master]: [WIP]aopen/dxplplusu: Support SMM_ASEG and SMM_TSEG
by Kyösti Mälkki (Code Review) 15 Nov '22

15 Nov '22

Attention is currently required from: Angel Pons, Kyösti Mälkki, Patrick Rudolph, Elyes Haouas. Hello build bot (Jenkins), Angel Pons, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61517 to look at the new patch set (#5). Change subject: [WIP]aopen/dxplplusu: Support SMM_ASEG and SMM_TSEG ...................................................................... [WIP]aopen/dxplplusu: Support SMM_ASEG and SMM_TSEG Both SMM_ASEG and SMM_TSEG choices work. There is periodic TCO timeout occuring. At least with DEBUG_SMI kernel reports low memory corruption. Change-Id: If20a7092117612a1a9e25eb6ac480e105acd57d7 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/intel/model_f2x/Kconfig M src/cpu/intel/model_f2x/Makefile.inc M src/cpu/intel/model_f2x/model_f2x_init.c A src/cpu/intel/model_f2x/mp_init.c M src/northbridge/intel/e7505/Kconfig M src/northbridge/intel/e7505/e7505.h M src/northbridge/intel/e7505/memmap.c M src/northbridge/intel/e7505/northbridge.c M src/northbridge/intel/e7505/raminit.c M src/southbridge/intel/common/smi.c M src/southbridge/intel/i82801dx/Kconfig M src/southbridge/intel/i82801dx/Makefile.inc M src/southbridge/intel/i82801dx/fadt.c M src/southbridge/intel/i82801dx/i82801dx.h M src/southbridge/intel/i82801dx/lpc.c A src/southbridge/intel/i82801dx/smihandler.c 16 files changed, 258 insertions(+), 78 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/61517/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/61517 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If20a7092117612a1a9e25eb6ac480e105acd57d7 Gerrit-Change-Number: 61517 Gerrit-PatchSet: 5 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: sb/intel/i82801dx: Improve LPC device early init
by Kyösti Mälkki (Code Review) 15 Nov '22

15 Nov '22

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69671 to look at the new patch set (#2). Change subject: sb/intel/i82801dx: Improve LPC device early init ...................................................................... sb/intel/i82801dx: Improve LPC device early init Make the implementation more similar to i82801gx, enabling ACPI PM and GPIO register spaces already in bootblock. Change-Id: I41ad8622801dbbadafdc37359d521eed42256e63 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/northbridge/intel/e7505/romstage.c M src/southbridge/intel/i82801dx/Makefile.inc M src/southbridge/intel/i82801dx/bootblock.c A src/southbridge/intel/i82801dx/early_init.c D src/southbridge/intel/i82801dx/early_smbus.c M src/southbridge/intel/i82801dx/i82801dx.h M src/southbridge/intel/i82801dx/lpc.c 7 files changed, 60 insertions(+), 69 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/69671/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69671 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41ad8622801dbbadafdc37359d521eed42256e63 Gerrit-Change-Number: 69671 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: nb/intel/ironlake,sandybridge/gma: Fix out() parameter order
by Kyösti Mälkki (Code Review) 15 Nov '22

15 Nov '22

Attention is currently required from: Nico Huber, Kyösti Mälkki. Hello build bot (Jenkins), Nico Huber, Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69670 to look at the new patch set (#2). Change subject: nb/intel/ironlake,sandybridge/gma: Fix out() parameter order ...................................................................... nb/intel/ironlake,sandybridge/gma: Fix out() parameter order Change-Id: I4baa2e06d336736caf5505a05ed4353bcbfdb517 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/northbridge/intel/ironlake/gma.c M src/northbridge/intel/sandybridge/gma.c 2 files changed, 16 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/69670/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69670 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4baa2e06d336736caf5505a05ed4353bcbfdb517 Gerrit-Change-Number: 69670 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mb/google/nissa/var/craask: Correct G2 touchscreen HID
by Eric Lai (Code Review) 15 Nov '22

15 Nov '22

Eric Lai has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69600 ) Change subject: mb/google/nissa/var/craask: Correct G2 touchscreen HID ...................................................................... mb/google/nissa/var/craask: Correct G2 touchscreen HID Correct G2 touchscreen HID to GT75CH02. BUG=b:235919755 Test=Dump the SSDT on craask and check the HID had been modified. Signed-off-by: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Change-Id: Iad32e8cbd534dc43fca24d881092f3477ca1a4e5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69600 Reviewed-by: Kangheui Won <khwon(a)chromium.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brya/variants/craask/overridetree.cb 1 file changed, 20 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Kangheui Won: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/craask/overridetree.cb b/src/mainboard/google/brya/variants/craask/overridetree.cb index cd34d71..6db23d4 100644 --- a/src/mainboard/google/brya/variants/craask/overridetree.cb +++ b/src/mainboard/google/brya/variants/craask/overridetree.cb @@ -192,7 +192,7 @@ end device ref i2c1 on chip drivers/i2c/hid - register "generic.hid" = ""GTCH7503"" + register "generic.hid" = ""GTCH7502"" register "generic.desc" = ""G2 Touchscreen"" register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" register "generic.probed" = "1" -- To view, visit https://review.coreboot.org/c/coreboot/+/69600 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iad32e8cbd534dc43fca24d881092f3477ca1a4e5 Gerrit-Change-Number: 69600 Gerrit-PatchSet: 2 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Cathy Chen <cathy_chen(a)quanta.corp-partner.google.com> Gerrit-CC: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-CC: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-MessageType: merged

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coreboot-gerrit November 2022