coreboot-gerrit November 2022

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[S] Change in coreboot[master]: mb/google/octopus/variants/phaser: Implement variant_memory_sku()
by Derek Huang (Code Review) 24 Nov '22

24 Nov '22

Attention is currently required from: Jamie Chen, Stanley Wu, Marco Chen, Eric Lai. Derek Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69925 ) Change subject: mb/google/octopus/variants/phaser: Implement variant_memory_sku() ...................................................................... Patch Set 4: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/69925 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36ec6bad7096e5de666ac6500c8419fc6e383ae1 Gerrit-Change-Number: 69925 Gerrit-PatchSet: 4 Gerrit-Owner: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Jamie Chen <jamie.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Marco Chen <marcochen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-CC: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-Attention: Jamie Chen <jamie.chen(a)intel.corp-partner.google.com> Gerrit-Attention: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-Attention: Marco Chen <marcochen(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Thu, 24 Nov 2022 06:14:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: drivers/wwan/fm: Use correct GUID for DmaProperty in ACPI _DSD
by Eric Lai (Code Review) 24 Nov '22

24 Nov '22

Attention is currently required from: Tarun Tuli, Kapil Porwal, Elyes Haouas, Rajat Jain. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69932 ) Change subject: drivers/wwan/fm: Use correct GUID for DmaProperty in ACPI _DSD ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/69932 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I05b8c3bf23cc43863527bc514d9a96096d45003c Gerrit-Change-Number: 69932 Gerrit-PatchSet: 1 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Rajat Jain <rajatja(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Rajat Jain <rajatja(a)google.com> Gerrit-Comment-Date: Thu, 24 Nov 2022 06:07:35 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: {drivers/wifi, mb/google}: Rename `is_untrusted` to `add_acpi_dma_pro...
by Eric Lai (Code Review) 24 Nov '22

24 Nov '22

Attention is currently required from: Tarun Tuli, Subrata Banik, Kapil Porwal. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69937 ) Change subject: {drivers/wifi, mb/google}: Rename `is_untrusted` to `add_acpi_dma_property` ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69937 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4e0829a76a193b0a1e1e0f2b7ce2119bb00dd696 Gerrit-Change-Number: 69937 Gerrit-PatchSet: 2 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Thu, 24 Nov 2022 06:07:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: {drivers/wifi, mb/google}: Rename `is_untrusted` to `add_acpi_dma_pro...
by Eric Lai (Code Review) 24 Nov '22

24 Nov '22

Attention is currently required from: Tarun Tuli, Subrata Banik, Kapil Porwal. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69937 ) Change subject: {drivers/wifi, mb/google}: Rename `is_untrusted` to `add_acpi_dma_property` ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > I think it is okay to use only 1 GUID (i.e. […] ok, SG. -- To view, visit https://review.coreboot.org/c/coreboot/+/69937 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4e0829a76a193b0a1e1e0f2b7ce2119bb00dd696 Gerrit-Change-Number: 69937 Gerrit-PatchSet: 2 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Thu, 24 Nov 2022 06:07:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com> Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/brya/var/marasov: Add touchscreen and touchpad for marasov
by Martin L Roth (Code Review) 24 Nov '22

24 Nov '22

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69467 ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/brya/var/marasov: Add touchscreen and touchpad for marasov ...................................................................... mb/google/brya/var/marasov: Add touchscreen and touchpad for marasov Declare touchscreen and touchpad under I2C3 and I2C5 BUG=b:254365935 BRANCH=firmware-brya-14505.B TEST=Built successfully Signed-off-by: Frank Chu <Frank_Chu(a)pegatron.corp-partner.google.com> Change-Id: Ifc865fc0c0c42af0d74272289c562e347fac3a9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/69467 Reviewed-by: Nick Vaccaro <nvaccaro(a)google.com> Reviewed-by: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brya/variants/marasov/overridetree.cb 1 file changed, 52 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Nick Vaccaro: Looks good to me, approved Frank Chu: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/brya/variants/marasov/overridetree.cb b/src/mainboard/google/brya/variants/marasov/overridetree.cb index b09d2f3..cb77335 100644 --- a/src/mainboard/google/brya/variants/marasov/overridetree.cb +++ b/src/mainboard/google/brya/variants/marasov/overridetree.cb @@ -117,6 +117,38 @@ device i2c 50 on end end end #I2C1 + device ref i2c3 on + chip drivers/i2c/hid + register "generic.hid" = ""ELAN9008"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" + register "generic.reset_delay_ms" = "300" + register "generic.reset_off_delay_ms" = "1" + register "generic.enable_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" + register "generic.enable_delay_ms" = "6" + register "generic.stop_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" + register "generic.stop_off_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 10 on end + end + end #I2C3 + device ref i2c5 on + chip drivers/i2c/generic + register "hid" = ""PIXA2342"" + register "desc" = ""PIXART Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)" + register "wake" = "GPE0_DW2_14" + register "detect" = "1" + device i2c 15 on end + end + end #I2C5 device ref pcie_rp11 on # Enable NVMe SSD PCIe 11-12 using clk 1 register "pch_pcie_rp[PCH_RP(11)]" = "{ -- To view, visit https://review.coreboot.org/c/coreboot/+/69467 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifc865fc0c0c42af0d74272289c562e347fac3a9e Gerrit-Change-Number: 69467 Gerrit-PatchSet: 3 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Kyle Lin <kylelinck(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: lint/checkpatch: Add XA_STATE and XA_STATE_ORDER to the macro declara...
by Martin L Roth (Code Review) 24 Nov '22

24 Nov '22

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/67338 ) Change subject: lint/checkpatch: Add XA_STATE and XA_STATE_ORDER to the macro declaration ...................................................................... lint/checkpatch: Add XA_STATE and XA_STATE_ORDER to the macro declaration This reduce the difference with linux v6.0-rc3. Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Change-Id: Ica20264d744ea8f77b56c63d29e1fafc2e68a869 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67338 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin L Roth <gaumless(a)gmail.com> --- M util/lint/checkpatch.pl 1 file changed, 17 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Martin L Roth: Looks good to me, approved diff --git a/util/lint/checkpatch.pl b/util/lint/checkpatch.pl index d044d8d..e88461f 100755 --- a/util/lint/checkpatch.pl +++ b/util/lint/checkpatch.pl @@ -946,7 +946,8 @@ our $declaration_macros = qr{(?x: (?:$Storage\s+)?(?:[A-Z_][A-Z0-9]*_){0,2}(?:DEFINE|DECLARE)(?:_[A-Z0-9]+){1,6}\s*\(| (?:$Storage\s+)?[HLP]?LIST_HEAD\s*\(| - (?:SKCIPHER_REQUEST|SHASH_DESC|AHASH_REQUEST)_ON_STACK\s*\( + (?:SKCIPHER_REQUEST|SHASH_DESC|AHASH_REQUEST)_ON_STACK\s*\(| + (?:$Storage\s+)?(?:XA_STATE|XA_STATE_ORDER)\s*\( )}; our %allow_repeated_words = ( -- To view, visit https://review.coreboot.org/c/coreboot/+/67338 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica20264d744ea8f77b56c63d29e1fafc2e68a869 Gerrit-Change-Number: 67338 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: sb/intel/i82801gx: Move SPIBASE and SPIBARxx to i82801gx.h
by Martin L Roth (Code Review) 24 Nov '22

24 Nov '22

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69899 ) Change subject: sb/intel/i82801gx: Move SPIBASE and SPIBARxx to i82801gx.h ...................................................................... sb/intel/i82801gx: Move SPIBASE and SPIBARxx to i82801gx.h Also remove unused DEBUG_PERIODIC_SMIS macro. Change-Id: Ieb8487c7757b89a09c1cee4a83f94b9077dac87e Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69899 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin L Roth <gaumless(a)gmail.com> --- M src/southbridge/intel/i82801gx/i82801gx.h M src/southbridge/intel/i82801gx/lpc.c 2 files changed, 20 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Martin L Roth: Looks good to me, approved diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index cf76a40..0625db0 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -9,10 +9,13 @@ #include <southbridge/intel/common/rcba.h> /* IWYU pragma: export */ -#ifndef __ACPI__ -#define DEBUG_PERIODIC_SMIS 0 +#define SPIBASE 0x3020 +#define SPIBAR16(x) RCBA16(SPIBASE + x) +#define SPIBAR32(x) RCBA32(SPIBASE + x) +#ifndef __ACPI__ #include <device/device.h> + void i82801gx_enable(struct device *dev); void i82801gx_lpc_setup(void); diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 37095e84..62ff757 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -285,7 +285,6 @@ } } -#define SPIBASE 0x3020 static void i82801gx_spi_init(void) { u16 spicontrol; @@ -418,9 +417,6 @@ } } -#define SPIBAR16(x) RCBA16(0x3020 + x) -#define SPIBAR32(x) RCBA32(0x3020 + x) - static void lpc_final(struct device *dev) { u16 tco1_cnt; -- To view, visit https://review.coreboot.org/c/coreboot/+/69899 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieb8487c7757b89a09c1cee4a83f94b9077dac87e Gerrit-Change-Number: 69899 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: sb/intel/i82801gx: Use "sb/intel/common/tco.h" macros
by Martin L Roth (Code Review) 24 Nov '22

24 Nov '22

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69878 ) ( 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: sb/intel/i82801gx: Use "sb/intel/common/tco.h" macros ...................................................................... sb/intel/i82801gx: Use "sb/intel/common/tco.h" macros Also, use {read,write}_pmbase16() in lpc.c file instead of inw/out. Change-Id: Id281a3478051c4876ccbe26452d8744769c86654 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69878 Reviewed-by: Martin L Roth <gaumless(a)gmail.com> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/southbridge/intel/i82801gx/early_init.c M src/southbridge/intel/i82801gx/i82801gx.h M src/southbridge/intel/i82801gx/lpc.c 3 files changed, 23 insertions(+), 8 deletions(-) Approvals: build bot (Jenkins): Verified Martin L Roth: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/southbridge/intel/i82801gx/early_init.c b/src/southbridge/intel/i82801gx/early_init.c index deb3deb..dda5c00 100644 --- a/src/southbridge/intel/i82801gx/early_init.c +++ b/src/southbridge/intel/i82801gx/early_init.c @@ -6,6 +6,7 @@ #include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/pmbase.h> #include <southbridge/intel/common/rcba.h> +#include <southbridge/intel/common/tco.h> #include "chip.h" #include "i82801gx.h" @@ -57,8 +58,6 @@ pci_write_config8(d31f0, GPIO_CNTL, GPIO_EN); } -#define TCO_BASE 0x60 - #if ENV_RAMINIT void i82801gx_early_init(void) { @@ -72,9 +71,9 @@ printk(BIOS_DEBUG, "Disabling Watchdog reboot..."); RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */ - write_pmbase16(TCO_BASE + 0x8, (1 << 11)); /* halt timer */ - write_pmbase16(TCO_BASE + 0x4, (1 << 3)); /* clear timeout */ - write_pmbase16(TCO_BASE + 0x6, (1 << 1)); /* clear 2nd timeout */ + write_pmbase16(PMBASE_TCO_OFFSET + TCO1_CNT, TCO_TMR_HLT); + write_pmbase16(PMBASE_TCO_OFFSET + TCO1_STS, TCO1_TIMEOUT); + write_pmbase16(PMBASE_TCO_OFFSET + TCO2_STS, SECOND_TO_STS); printk(BIOS_DEBUG, " done.\n"); /* program secondary mlt XXX byte? */ diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index 68a32df..cf76a40 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -320,7 +320,6 @@ #define DEVACT_STS 0x44 #define SS_CNT 0x50 #define C3_RES 0x54 -#define TCO1_CNT 0x68 #endif /* __ACPI__ */ #endif /* SOUTHBRIDGE_INTEL_I82801GX_I82801GX_H */ diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index d8c9776..37095e84 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -20,6 +20,7 @@ #include <southbridge/intel/common/hpet.h> #include <southbridge/intel/common/pmbase.h> #include <southbridge/intel/common/spi.h> +#include <southbridge/intel/common/tco.h> #include "chip.h" #include "i82801gx.h" @@ -440,9 +441,9 @@ pci_or_config16(dev, GEN_PMCON_1, 1 << 4); /* TCO_Lock */ - tco1_cnt = inw(DEFAULT_PMBASE + 0x60 + TCO1_CNT); + tco1_cnt = read_pmbase16(PMBASE_TCO_OFFSET + TCO1_CNT); tco1_cnt |= (1 << 12); /* TCO lock */ - outw(tco1_cnt, DEFAULT_PMBASE + 0x60 + TCO1_CNT); + write_pmbase16(PMBASE_TCO_OFFSET + TCO1_CNT, tco1_cnt); /* Indicate finalize step with post code */ post_code(POST_OS_BOOT); -- To view, visit https://review.coreboot.org/c/coreboot/+/69878 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id281a3478051c4876ccbe26452d8744769c86654 Gerrit-Change-Number: 69878 Gerrit-PatchSet: 4 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/siemens/mc_ehl2: Enable downshift for Marvell PHYs
by Martin L Roth (Code Review) 24 Nov '22

24 Nov '22

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69887 ) ( 3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/siemens/mc_ehl2: Enable downshift for Marvell PHYs ...................................................................... mb/siemens/mc_ehl2: Enable downshift for Marvell PHYs Set downshift counter to 2 for all Marvell PHYs on this mainboard before the PHY downshifts to the next highest speed. Change-Id: I32b5f25a3e1e0f962dff3110143e236992ef8e7d Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69887 Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb 1 file changed, 19 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb index 8090927..e1c2972 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb @@ -191,6 +191,7 @@ register "led_1_ctrl" = "1" # INTn is routed to LED[2] pin register "enable_int" = "true" + register "downshift_cnt" = "2" device mdio 0 on # PHY address ops m88e1512_ops end @@ -206,6 +207,7 @@ register "led_1_ctrl" = "1" # INTn is routed to LED[2] pin register "enable_int" = "true" + register "downshift_cnt" = "2" device mdio 1 on # PHY address ops m88e1512_ops end @@ -224,6 +226,7 @@ register "led_1_ctrl" = "1" # INTn is routed to LED[2] pin register "enable_int" = "true" + register "downshift_cnt" = "2" device mdio 1 on # PHY address ops m88e1512_ops end -- To view, visit https://review.coreboot.org/c/coreboot/+/69887 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I32b5f25a3e1e0f962dff3110143e236992ef8e7d Gerrit-Change-Number: 69887 Gerrit-PatchSet: 5 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: [WIP] mb/google/nissa/var/craask: Add support for NVMe GPIOs
by Ren Kuo (Code Review) 24 Nov '22

24 Nov '22

Attention is currently required from: David Wu, Tarun Tuli, Kangheui Won, Reka Norman, Tyler Wang. Ren Kuo has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69958 ) Change subject: [WIP] mb/google/nissa/var/craask: Add support for NVMe GPIOs ...................................................................... Patch Set 1: (1 comment) File src/mainboard/google/brya/variants/craask/gpio.c: https://review.coreboot.org/c/coreboot/+/69958/comment/fefd79b7_46dfe0f4 PS1, Line 15: GPP_D6 > If you want to use a shared firmware target, then the pins should be kept as similar as possible bet […] Hi Reka, verify the firmware on craask DUT, the LTE and WCAM functions are all well. -- To view, visit https://review.coreboot.org/c/coreboot/+/69958 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I76a056cddff2246cfb5bb26ddbdfc333b49d9aaf Gerrit-Change-Number: 69958 Gerrit-PatchSet: 1 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Reka Norman <rekanorman(a)google.com> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Thu, 24 Nov 2022 06:03:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Reka Norman <rekanorman(a)chromium.org> Comment-In-Reply-To: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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coreboot-gerrit November 2022