coreboot-gerrit November 2022

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[S] Change in coreboot[master]: Revert "sb/intel/i82801gx: Use "sb/intel/common/tco.h" macros"
by Kyösti Mälkki (Code Review) 26 Nov '22

26 Nov '22

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/70042 ) Change subject: Revert "sb/intel/i82801gx: Use "sb/intel/common/tco.h" macros" ...................................................................... Revert "sb/intel/i82801gx: Use "sb/intel/common/tco.h" macros" This reverts commit 9f0e21a4dae864809e9651403ab5bad48e784bee. It should be allowed for i82801gx/early_init.c to have #include <southbridge/intel/common/pmutil.h> But there is a conflict: src/southbridge/intel/common/pmutil.h: #define TCO1_CNT 0x68 src/southbridge/intel/common/tco.h: #define TCO1_CNT 0x08 Followup works resolve the difficulties around the offset 0x60 used for TCO register bank, tree-wide. Change-Id: I827558a0e0ef1c4d1f866756df51cd1b2abfc7a0 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/southbridge/intel/i82801gx/early_init.c M src/southbridge/intel/i82801gx/i82801gx.h M src/southbridge/intel/i82801gx/lpc.c 3 files changed, 33 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/70042/1 diff --git a/src/southbridge/intel/i82801gx/early_init.c b/src/southbridge/intel/i82801gx/early_init.c index dda5c00..deb3deb 100644 --- a/src/southbridge/intel/i82801gx/early_init.c +++ b/src/southbridge/intel/i82801gx/early_init.c @@ -6,7 +6,6 @@ #include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/pmbase.h> #include <southbridge/intel/common/rcba.h> -#include <southbridge/intel/common/tco.h> #include "chip.h" #include "i82801gx.h" @@ -58,6 +57,8 @@ pci_write_config8(d31f0, GPIO_CNTL, GPIO_EN); } +#define TCO_BASE 0x60 + #if ENV_RAMINIT void i82801gx_early_init(void) { @@ -71,9 +72,9 @@ printk(BIOS_DEBUG, "Disabling Watchdog reboot..."); RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */ - write_pmbase16(PMBASE_TCO_OFFSET + TCO1_CNT, TCO_TMR_HLT); - write_pmbase16(PMBASE_TCO_OFFSET + TCO1_STS, TCO1_TIMEOUT); - write_pmbase16(PMBASE_TCO_OFFSET + TCO2_STS, SECOND_TO_STS); + write_pmbase16(TCO_BASE + 0x8, (1 << 11)); /* halt timer */ + write_pmbase16(TCO_BASE + 0x4, (1 << 3)); /* clear timeout */ + write_pmbase16(TCO_BASE + 0x6, (1 << 1)); /* clear 2nd timeout */ printk(BIOS_DEBUG, " done.\n"); /* program secondary mlt XXX byte? */ diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index 0625db0..ee34f74 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -323,6 +323,7 @@ #define DEVACT_STS 0x44 #define SS_CNT 0x50 #define C3_RES 0x54 +#define TCO1_CNT 0x68 #endif /* __ACPI__ */ #endif /* SOUTHBRIDGE_INTEL_I82801GX_I82801GX_H */ diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index f8a2dac8..fd0a203 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -20,7 +20,6 @@ #include <southbridge/intel/common/hpet.h> #include <southbridge/intel/common/pmbase.h> #include <southbridge/intel/common/spi.h> -#include <southbridge/intel/common/tco.h> #include "chip.h" #include "i82801gx.h" @@ -428,9 +427,9 @@ pci_or_config16(dev, GEN_PMCON_1, 1 << 4); /* TCO_Lock */ - tco1_cnt = read_pmbase16(PMBASE_TCO_OFFSET + TCO1_CNT); + tco1_cnt = inw(DEFAULT_PMBASE + 0x60 + TCO1_CNT); tco1_cnt |= (1 << 12); /* TCO lock */ - write_pmbase16(PMBASE_TCO_OFFSET + TCO1_CNT, tco1_cnt); + outw(tco1_cnt, DEFAULT_PMBASE + 0x60 + TCO1_CNT); /* Indicate finalize step with post code */ post_code(POST_OS_BOOT); -- To view, visit https://review.coreboot.org/c/coreboot/+/70042 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I827558a0e0ef1c4d1f866756df51cd1b2abfc7a0 Gerrit-Change-Number: 70042 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: arch/x86: Add bitwise operations for IO space
by Kyösti Mälkki (Code Review) 26 Nov '22

26 Nov '22

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/70041 ) Change subject: arch/x86: Add bitwise operations for IO space ...................................................................... arch/x86: Add bitwise operations for IO space Change-Id: Ia3e1146f062dced1b75195846ea65a44e2bd4482 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- A src/arch/x86/include/arch/io_bitops.h 1 file changed, 93 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/70041/1 diff --git a/src/arch/x86/include/arch/io_bitops.h b/src/arch/x86/include/arch/io_bitops.h new file mode 100644 index 0000000..d18cbcc --- /dev/null +++ b/src/arch/x86/include/arch/io_bitops.h @@ -0,0 +1,83 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __ARCH_IO_BITOPS__ +#define __ARCH_IO_BITOPS__ + +#include <arch/io.h> +#include <types.h> + +static inline u32 io_read32(const u16 addr) +{ + return inl(addr); +} + +static inline u16 io_read16(const u16 addr) +{ + return inw(addr); +} + +static inline u8 io_read8(const u16 addr) +{ + return inb(addr); +} + +static inline void io_write32(const u16 addr, const u32 value) +{ + outl(value, addr); +} + +static inline void io_write16(const u16 addr, const u16 value) +{ + outw(value, addr); +} + +static inline void io_write8(const u16 addr, const u8 value) +{ + outb(value, addr); +} + +static inline u32 io_rwc32(const u16 addr) +{ + u32 reg = io_read32(addr); + io_write32(reg, addr); + return reg; +} + +static inline u16 io_rwc16(const u16 addr) +{ + u16 reg = io_read16(addr); + io_write16(addr, reg); + return reg; +} + +static inline u8 io_rwc8(const u16 addr) +{ + u8 reg = io_read8(addr); + io_write8(addr, reg); + return reg; +} + +static inline void io_clrsetbits32(const u16 addr, const u32 clr, const u32 set) +{ + io_write32(addr, (io_read32(addr) & ~clr) | set); +} + +static inline void io_clrsetbits16(const u16 addr, const u16 clr, const u16 set) +{ + io_write16(addr, (io_read16(addr) & ~clr) | set); +} + +static inline void io_clrsetbits8(const u16 addr, const u8 clr, const u8 set) +{ + io_write8(addr, (io_read8(addr) & ~clr) | set); +} + +#define io_setbits32(addr, set) io_clrsetbits32(addr, 0, set) +#define io_setbits16(addr, set) io_clrsetbits16(addr, 0, set) +#define io_setbits8(addr, set) io_clrsetbits8(addr, 0, set) + +#define io_clrbits32(addr, clr) io_clrsetbits32(addr, clr, 0) +#define io_clrbits16(addr, clr) io_clrsetbits16(addr, clr, 0) +#define io_clrbits8(addr, clr) io_clrsetbits8(addr, clr, 0) + +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/70041 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia3e1146f062dced1b75195846ea65a44e2bd4482 Gerrit-Change-Number: 70041 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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[L] Change in coreboot[master]: aopen/dxplplusu: Support SMM_ASEG and SMM_TSEG
by Kyösti Mälkki (Code Review) 26 Nov '22

26 Nov '22

Attention is currently required from: Angel Pons, Patrick Rudolph, Elyes Haouas. Hello build bot (Jenkins), Angel Pons, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61517 to look at the new patch set (#7). Change subject: aopen/dxplplusu: Support SMM_ASEG and SMM_TSEG ...................................................................... aopen/dxplplusu: Support SMM_ASEG and SMM_TSEG Both SMM_ASEG and SMM_TSEG choices work. There is periodic TCO timeout occuring. At least with DEBUG_SMI kernel reports low memory corruption. Change-Id: If20a7092117612a1a9e25eb6ac480e105acd57d7 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/intel/model_f2x/Kconfig M src/cpu/intel/model_f2x/Makefile.inc M src/cpu/intel/model_f2x/model_f2x_init.c A src/cpu/intel/model_f2x/mp_init.c M src/northbridge/intel/e7505/Kconfig M src/northbridge/intel/e7505/e7505.h M src/northbridge/intel/e7505/memmap.c M src/northbridge/intel/e7505/northbridge.c M src/northbridge/intel/e7505/raminit.c M src/southbridge/intel/i82801dx/Kconfig M src/southbridge/intel/i82801dx/Makefile.inc M src/southbridge/intel/i82801dx/fadt.c M src/southbridge/intel/i82801dx/i82801dx.h M src/southbridge/intel/i82801dx/lpc.c A src/southbridge/intel/i82801dx/smihandler.c 15 files changed, 256 insertions(+), 76 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/61517/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/61517 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If20a7092117612a1a9e25eb6ac480e105acd57d7 Gerrit-Change-Number: 61517 Gerrit-PatchSet: 7 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: arch/arm64/Makefile.inc: --no-warn-rwx-segments
by Felix Singer (Code Review) 26 Nov '22

26 Nov '22

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/70024 ) Change subject: arch/arm64/Makefile.inc: --no-warn-rwx-segments ...................................................................... arch/arm64/Makefile.inc: --no-warn-rwx-segments TODO Change-Id: I56757365559a3f910c59c16df22565d0b9740805 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/arch/arm64/Makefile.inc 1 file changed, 20 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/70024/1 diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc index 6b49743..1185577 100644 --- a/src/arch/arm64/Makefile.inc +++ b/src/arch/arm64/Makefile.inc @@ -173,6 +173,14 @@ BL31_CFLAGS := -fno-pic -fno-stack-protector -Wno-deprecated-declarations -Wno-unused-function BL31_LDFLAGS := --emit-relocs +# With binutils 2.39 it is required to build BL31 with the linker flag +# from below. For backwards compatibility to the current stable +# toolchain (4.18), check if that flag is supported by the linker. +# TODO: Remove the check after 4.19 got released. +ifneq (\$(shell "{LD_${TARCH}}" --no-warn-rwx-segments --version >/dev/null 2>&1),) + BL31_LDFLAGS += --no-warn-rwx-segments +endif + BL31 := $(obj)/bl31.elf $(BL31): $(obj)/build.h -- To view, visit https://review.coreboot.org/c/coreboot/+/70024 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I56757365559a3f910c59c16df22565d0b9740805 Gerrit-Change-Number: 70024 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: soc/amd/common/xhci: Add support for logging XHCI wake events
by Angel Pons (Code Review) 26 Nov '22

26 Nov '22

Attention is currently required from: Robert Zieba, Jason Glenesk, Raul Rangel, Matt DeVillier, Martin Roth, Fred Reitberger, Karthik Ramasubramanian, Felix Held. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67936 ) Change subject: soc/amd/common/xhci: Add support for logging XHCI wake events ...................................................................... Patch Set 10: (7 comments) File src/soc/amd/common/block/include/amdblocks/xhci.h: https://review.coreboot.org/c/coreboot/+/67936/comment/bd680bf3_a36f2003 PS10, Line 11: <stdint.h> Isn't `size_t` in `<stddef.h>`? You can simply include `<types.h>` for convenience. https://review.coreboot.org/c/coreboot/+/67936/comment/833b4243_05fa334e PS10, Line 13: #define XHCI_GEVENT GEVENT_31 Hmmm, what does this indirection achieve? File src/soc/amd/common/block/xhci/elog.c: https://review.coreboot.org/c/coreboot/+/67936/comment/4af5829c_e8932855 PS10, Line 20: base Instead of incrementing the value of `base`, would it be clearer to write this as `base + i * PORTSC_STRIDE`? You could also make a parametrized macro: #define PORTSC_ADDR(port) (PORTSC_OFFSET + (port) * PORTSC_STRIDE) https://review.coreboot.org/c/coreboot/+/67936/comment/8cac42ae_09e2aa29 PS10, Line 66: %d nit: %u for unsigned types https://review.coreboot.org/c/coreboot/+/67936/comment/e88b76e4_969be4d9 PS10, Line 67: context->controller reuse `controller` local variable? https://review.coreboot.org/c/coreboot/+/67936/comment/3d10f471_497c7003 PS10, Line 93: %d nit: %u for unsigned types https://review.coreboot.org/c/coreboot/+/67936/comment/78c0a430_7cf55a42 PS10, Line 93: %#lx Hmmm, one would use `PRIxPTR` to display `uintptr_t` values -- To view, visit https://review.coreboot.org/c/coreboot/+/67936 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic0489e1df55c4e63cb8a306099e3f31c82eebd58 Gerrit-Change-Number: 67936 Gerrit-PatchSet: 10 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Robert Zieba <robertzieba(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sat, 26 Nov 2022 14:52:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: drivers/{wifi,wwan}: Use helper function to add DmaProperty in _DSD
by Kapil Porwal (Code Review) 26 Nov '22

26 Nov '22

Kapil Porwal has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/70023 ) Change subject: drivers/{wifi,wwan}: Use helper function to add DmaProperty in _DSD ...................................................................... drivers/{wifi,wwan}: Use helper function to add DmaProperty in _DSD BUG=b:259716145 TEST=Build google/rex Signed-off-by: Kapil Porwal <kapilporwal(a)google.com> Change-Id: I991bc822fbb72cfaa9485abe882950fc7bcef498 --- M src/drivers/wifi/generic/acpi.c M src/drivers/wwan/fm/acpi_fm350gl.c 2 files changed, 17 insertions(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/70023/1 diff --git a/src/drivers/wifi/generic/acpi.c b/src/drivers/wifi/generic/acpi.c index 57b7f5f..3996739 100644 --- a/src/drivers/wifi/generic/acpi.c +++ b/src/drivers/wifi/generic/acpi.c @@ -30,9 +30,6 @@ /* Unique ID for the WIFI _DSM */ #define ACPI_DSM_OEM_WIFI_UUID "F21202BF-8F78-4DC6-A5B3-1F738E285ADE" -/* ID for the Wifi DmaProperty _DSD */ -#define ACPI_DSD_DMA_PROPERTY_UUID "70D24161-6DD5-4C9E-8070-705531292865" - /* Unique ID for CnviDdrRfim entry in WIFI _DSM */ #define ACPI_DSM_RFIM_WIFI_UUID "7266172C-220B-4B29-814F-75E4DD26B5FD" @@ -522,15 +519,8 @@ acpigen_write_PRW(config->wake, ACPI_S3); /* Add _DSD for DmaProperty property. */ - if (config->add_acpi_dma_property) { - struct acpi_dp *dsd, *pkg; - - dsd = acpi_dp_new_table("_DSD"); - pkg = acpi_dp_new_table(ACPI_DSD_DMA_PROPERTY_UUID); - acpi_dp_add_integer(pkg, "DmaProperty", 1); - acpi_dp_add_package(dsd, pkg); - acpi_dp_write(dsd); - } + if (config->add_acpi_dma_property) + acpi_device_add_dma_property(NULL); } /* Fill regulatory domain structure */ diff --git a/src/drivers/wwan/fm/acpi_fm350gl.c b/src/drivers/wwan/fm/acpi_fm350gl.c index 7ff8b2b..6e36888 100644 --- a/src/drivers/wwan/fm/acpi_fm350gl.c +++ b/src/drivers/wwan/fm/acpi_fm350gl.c @@ -5,9 +5,6 @@ #include "chip.h" #include "soc/intel/common/block/pcie/rtd3/chip.h" -/* ID for the DmaProperty in _DSD */ -#define ACPI_DSD_DMA_PROPERTY_UUID "70D24161-6DD5-4C9E-8070-705531292865" - /* FCPO# to RESET# delay time during WWAN ON */ #define FM350GL_TN2B 20 /* RESET# to PERST# delay time during WWAN ON */ @@ -245,14 +242,8 @@ wwan_fm350gl_acpi_method_rst(parent, config); wwan_fm350gl_acpi_method_dpts(parent, config); - if (config->add_acpi_dma_property) { - struct acpi_dp *dsd, *pkg; - dsd = acpi_dp_new_table("_DSD"); - pkg = acpi_dp_new_table(ACPI_DSD_DMA_PROPERTY_UUID); - acpi_dp_add_integer(pkg, "DmaProperty", 1); - acpi_dp_add_package(dsd, pkg); - acpi_dp_write(dsd); - } + if (config->add_acpi_dma_property) + acpi_device_add_dma_property(NULL); /* NOTE: the 5G driver will call MRST._RST to trigger a cold reset * during firmware update. -- To view, visit https://review.coreboot.org/c/coreboot/+/70023 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I991bc822fbb72cfaa9485abe882950fc7bcef498 Gerrit-Change-Number: 70023 Gerrit-PatchSet: 1 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: acpi: Create a common method to add DmaProperty
by Kapil Porwal (Code Review) 26 Nov '22

26 Nov '22

Attention is currently required from: Lance Zhao, Kapil Porwal, Tim Wawrzynczak. Hello Lance Zhao, build bot (Jenkins), Subrata Banik, Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/70022 to look at the new patch set (#5). Change subject: acpi: Create a common method to add DmaProperty ...................................................................... acpi: Create a common method to add DmaProperty Create a common method to add DmaProperty. BUG=b:259716145 TEST=Verified SSDT on google/osiris. Signed-off-by: Kapil Porwal <kapilporwal(a)google.com> Change-Id: I75b3f22ad29f90f3c3b251bd0d70bae9d75f71fe --- M src/acpi/device.c M src/include/acpi/acpi_device.h 2 files changed, 40 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/70022/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/70022 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I75b3f22ad29f90f3c3b251bd0d70bae9d75f71fe Gerrit-Change-Number: 70022 Gerrit-PatchSet: 5 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/amd/cezanne: Update XHCI GPE to use constant
by Angel Pons (Code Review) 26 Nov '22

26 Nov '22

Attention is currently required from: Robert Zieba, Jason Glenesk, Raul Rangel, Fred Reitberger, Felix Held. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69917 ) Change subject: soc/amd/cezanne: Update XHCI GPE to use constant ...................................................................... Patch Set 3: (1 comment) File src/soc/amd/cezanne/xhci.c: https://review.coreboot.org/c/coreboot/+/69917/comment/f92d5228_077d1b40 PS3, Line 14: GEVENT_31 > Is this macro still needed? Apparently it still needs to be defined because `XHCI_GEVENT` is defined as `GEVENT_31`: https://review.coreboot.org/c/coreboot/+/67936/10/src/soc/amd/common/block/… -- To view, visit https://review.coreboot.org/c/coreboot/+/69917 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c2a44f7d2eb47422ae8c585e5e01ea0b420d461 Gerrit-Change-Number: 69917 Gerrit-PatchSet: 3 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Robert Zieba <robertzieba(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sat, 26 Nov 2022 14:45:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/amd/common/xhci: Add support for logging XHCI wake events
by Angel Pons (Code Review) 26 Nov '22

26 Nov '22

Attention is currently required from: Robert Zieba, Jason Glenesk, Raul Rangel, Matt DeVillier, Martin Roth, Fred Reitberger, Karthik Ramasubramanian, Felix Held. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67936 ) Change subject: soc/amd/common/xhci: Add support for logging XHCI wake events ...................................................................... Patch Set 10: (1 comment) File src/soc/amd/common/block/include/amdblocks/xhci.h: https://review.coreboot.org/c/coreboot/+/67936/comment/fdd0cdc8_e4783ea6 PS7, Line 19: #if CONFIG(SOC_AMD_COMMON_BLOCK_XHCI_ELOG) && ENV_SMM > We shouldn't ever need to hide the declarations this way. It's best to rely on the linker optimizing away unreachable function calls. The only reason we have this pattern elsewhere is for optional functionality where calls aren't guarded, e.g. console drivers. -- To view, visit https://review.coreboot.org/c/coreboot/+/67936 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic0489e1df55c4e63cb8a306099e3f31c82eebd58 Gerrit-Change-Number: 67936 Gerrit-PatchSet: 10 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Robert Zieba <robertzieba(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sat, 26 Nov 2022 14:44:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/cezanne: Update XHCI GPE to use constant
by Angel Pons (Code Review) 26 Nov '22

26 Nov '22

Attention is currently required from: Robert Zieba, Jason Glenesk, Raul Rangel, Fred Reitberger, Felix Held. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69917 ) Change subject: soc/amd/cezanne: Update XHCI GPE to use constant ...................................................................... Patch Set 3: Code-Review+1 (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/69917/comment/961cad72_b723ce48 PS3, Line 10: CL 67936 nit: use CB:67936 so that Gerrit highlights it as a link. For submitted commits, it's best to use the commit hash instead (but this is not the case). File src/soc/amd/cezanne/xhci.c: https://review.coreboot.org/c/coreboot/+/69917/comment/53980ca4_00756723 PS3, Line 14: GEVENT_31 Is this macro still needed? -- To view, visit https://review.coreboot.org/c/coreboot/+/69917 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c2a44f7d2eb47422ae8c585e5e01ea0b420d461 Gerrit-Change-Number: 69917 Gerrit-PatchSet: 3 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Robert Zieba <robertzieba(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sat, 26 Nov 2022 14:41:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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