coreboot-gerrit November 2022

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[M] Change in coreboot[master]: mb/intel/mtlrvp: Add romstage and configure DDR5 memory parts
by Harsha B R (Code Review) 26 Nov '22

26 Nov '22

Attention is currently required from: Tarun Tuli, Jamie Ryu, Wonkyu Kim, Tim Wawrzynczak, Ravishankar Sarawadi, Kapil Porwal, Angel Pons, Nick Vaccaro, Raj Astekar. Harsha B R has uploaded a new patch set (#2) to the change originally created by Jamie Ryu. ( https://review.coreboot.org/c/coreboot/+/66190 ) Change subject: mb/intel/mtlrvp: Add romstage and configure DDR5 memory parts ...................................................................... mb/intel/mtlrvp: Add romstage and configure DDR5 memory parts This patch adds initial romstage code and spd data for DDR5 memory parts for MTL-RVP. This also configures memory based on the board id. BUG=b:224325352 TEST=FW_NAME=mtlrvp_p emerge-rex coreboot chromeos-bootimage Signed-off-by: Jamie Ryu <jamie.m.ryu(a)intel.com> Change-Id: I0e1a26d99e170311a89412f44b7cbb0430788f58 --- M src/mainboard/intel/mtlrvp/Kconfig M src/mainboard/intel/mtlrvp/Makefile.inc A src/mainboard/intel/mtlrvp/romstage_fsp_params.c A src/mainboard/intel/mtlrvp/spd/Makefile.inc A src/mainboard/intel/mtlrvp/spd/empty.spd.hex A src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp/Makefile.inc A src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp/memory.c 7 files changed, 156 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/66190/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/66190 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0e1a26d99e170311a89412f44b7cbb0430788f58 Gerrit-Change-Number: 66190 Gerrit-PatchSet: 2 Gerrit-Owner: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Raj Astekar <raj.astekar(a)intel.com> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[master]: aopen/dxplplusu: Support SMM_ASEG and SMM_TSEG
by build bot (Jenkins) (Code Review) 26 Nov '22

26 Nov '22

Attention is currently required from: Angel Pons, Patrick Rudolph, Elyes Haouas. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61517 ) Change subject: aopen/dxplplusu: Support SMM_ASEG and SMM_TSEG ...................................................................... Patch Set 7: (2 comments) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164597): https://review.coreboot.org/c/coreboot/+/61517/comment/740b1368_a82aa794 PS7, Line 13: 'occuring' may be misspelled - perhaps 'occurring'? File src/northbridge/intel/e7505/memmap.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164597): https://review.coreboot.org/c/coreboot/+/61517/comment/6437da39_cc4863a5 PS7, Line 42: return 512 *KiB; need consistent spacing around '*' (ctx:WxV) -- To view, visit https://review.coreboot.org/c/coreboot/+/61517 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If20a7092117612a1a9e25eb6ac480e105acd57d7 Gerrit-Change-Number: 61517 Gerrit-PatchSet: 7 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Sat, 26 Nov 2022 18:32:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel: Adopt new common/pmbase
by Kyösti Mälkki (Code Review) 26 Nov '22

26 Nov '22

Attention is currently required from: Sean Rhodes. Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/70050 ) Change subject: soc/intel: Adopt new common/pmbase ...................................................................... soc/intel: Adopt new common/pmbase Change-Id: I473ebefcf8e0c929f6cbf6b5c0d7e8f5af72856d Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/acer/aspire_vn7_572g/mainboard.c M src/soc/intel/apollolake/pmutil.c M src/soc/intel/common/block/pmc/pmclib.c M src/soc/intel/common/block/smm/smihandler.c M src/soc/intel/common/block/smm/smitraphandler.c M src/soc/intel/skylake/pmc.c 6 files changed, 39 insertions(+), 51 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/70050/1 diff --git a/src/mainboard/acer/aspire_vn7_572g/mainboard.c b/src/mainboard/acer/aspire_vn7_572g/mainboard.c index eba9e98..171b193 100644 --- a/src/mainboard/acer/aspire_vn7_572g/mainboard.c +++ b/src/mainboard/acer/aspire_vn7_572g/mainboard.c @@ -126,9 +126,10 @@ /* Clear below events and go back to sleep */ /* Clear ABase PM1_STS - RW/1C set bits */ pmc_clear_pm1_status(); + /* Clear ABase GPE0_STS[127:96] - RW/1C set bits */ - uint32_t gpe_sts = inl(ACPI_BASE_ADDRESS + GPE0_STS(GPE_STD)); - outl(gpe_sts, ACPI_BASE_ADDRESS + GPE0_STS(GPE_STD)); + pm_rwc32(GPE0_STS(GPE_STD)); + /* Clear xHCI PM_CS[PME_Status] - RW/1C - and disable xHCI PM_CS[PME_En] */ pci_update_config16(PCH_DEV_XHCI, 0x74, ~0x100, 0x8000); diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c index 765b2c8..1f641de 100644 --- a/src/soc/intel/apollolake/pmutil.c +++ b/src/soc/intel/apollolake/pmutil.c @@ -79,7 +79,7 @@ uint32_t soc_get_smi_status(uint32_t generic_sts) { if (generic_sts == 0 && !(pmc_read_pm1_control() & SCI_EN)) { - uint16_t pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS); + uint16_t pm1_sts = pm_read16(PM1_STS); /* Fake PM1 status bit if power button pressed. */ if (pm1_sts & PWRBTN_STS) diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c index ea365d0..87056c5 100644 --- a/src/soc/intel/common/block/pmc/pmclib.c +++ b/src/soc/intel/common/block/pmc/pmclib.c @@ -124,10 +124,7 @@ static uint32_t pmc_reset_smi_status(void) { - uint32_t smi_sts = inl(ACPI_BASE_ADDRESS + SMI_STS); - outl(smi_sts, ACPI_BASE_ADDRESS + SMI_STS); - - return soc_get_smi_status(smi_sts); + return soc_get_smi_status(pm_rwc32(SMI_STS)); } static uint32_t print_smi_status(uint32_t smi_sts) @@ -162,7 +159,7 @@ /* Read events set in PM1_EN register. */ uint16_t pmc_read_pm1_enable(void) { - return inw(ACPI_BASE_ADDRESS + PM1_EN); + return pm_read16(PM1_EN); } uint32_t pmc_clear_smi_status(void) @@ -174,58 +171,48 @@ uint32_t pmc_get_smi_en(void) { - return inl(ACPI_BASE_ADDRESS + SMI_EN); + return pm_read32(SMI_EN); } void pmc_enable_smi(uint32_t mask) { - uint32_t smi_en = inl(ACPI_BASE_ADDRESS + SMI_EN); - smi_en |= mask; - outl(smi_en, ACPI_BASE_ADDRESS + SMI_EN); + pm_setbits32(SMI_EN, mask); } void pmc_disable_smi(uint32_t mask) { - uint32_t smi_en = inl(ACPI_BASE_ADDRESS + SMI_EN); - smi_en &= ~mask; - outl(smi_en, ACPI_BASE_ADDRESS + SMI_EN); + pm_clrbits32(SMI_EN, mask); } /* PM1 */ void pmc_enable_pm1(uint16_t events) { - outw(events, ACPI_BASE_ADDRESS + PM1_EN); + pm_write16(PM1_EN, events); } uint32_t pmc_read_pm1_control(void) { - return inl(ACPI_BASE_ADDRESS + PM1_CNT); + return pm_read32(PM1_CNT); } void pmc_write_pm1_control(uint32_t pm1_cnt) { - outl(pm1_cnt, ACPI_BASE_ADDRESS + PM1_CNT); + pm_write32(PM1_CNT, pm1_cnt); } void pmc_enable_pm1_control(uint32_t mask) { - uint32_t pm1_cnt = pmc_read_pm1_control(); - pm1_cnt |= mask; - pmc_write_pm1_control(pm1_cnt); + pm_setbits32(PM1_CNT, mask); } void pmc_disable_pm1_control(uint32_t mask) { - uint32_t pm1_cnt = pmc_read_pm1_control(); - pm1_cnt &= ~mask; - pmc_write_pm1_control(pm1_cnt); + pm_clrbits32(PM1_CNT, mask); } static uint16_t reset_pm1_status(void) { - uint16_t pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS); - outw(pm1_sts, ACPI_BASE_ADDRESS + PM1_STS); - return pm1_sts; + return pm_rwc16(PM1_STS); } static uint16_t print_pm1_status(uint16_t pm1_sts) @@ -284,16 +271,12 @@ /* GPE */ static void pmc_enable_gpe(int gpe, uint32_t mask) { - uint32_t gpe0_en = inl(ACPI_BASE_ADDRESS + GPE0_EN(gpe)); - gpe0_en |= mask; - outl(gpe0_en, ACPI_BASE_ADDRESS + GPE0_EN(gpe)); + pm_setbits32(GPE0_EN(gpe), mask); } static void pmc_disable_gpe(int gpe, uint32_t mask) { - uint32_t gpe0_en = inl(ACPI_BASE_ADDRESS + GPE0_EN(gpe)); - gpe0_en &= ~mask; - outl(gpe0_en, ACPI_BASE_ADDRESS + GPE0_EN(gpe)); + pm_clrbits32(GPE0_EN(gpe), mask); } void pmc_enable_std_gpe(uint32_t mask) @@ -322,16 +305,13 @@ /* This is reserved GPE block and specific to chipset */ if (i == GPE_STD) continue; - uint32_t gpe_sts = inl(ACPI_BASE_ADDRESS + GPE0_STS(i)); - outl(gpe_sts, ACPI_BASE_ADDRESS + GPE0_STS(i)); + pm_rwc32(GPE0_STS(i)); } } static uint32_t reset_std_gpe_status(void) { - uint32_t gpe_sts = inl(ACPI_BASE_ADDRESS + GPE0_STS(GPE_STD)); - outl(gpe_sts, ACPI_BASE_ADDRESS + GPE0_STS(GPE_STD)); - return gpe_sts; + return pm_rwc32(GPE0_STS(GPE_STD)); } static uint32_t print_std_gpe_sts(uint32_t gpe_sts) @@ -423,16 +403,16 @@ memset(ps, 0, sizeof(*ps)); - ps->pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS); - ps->pm1_en = inw(ACPI_BASE_ADDRESS + PM1_EN); + ps->pm1_sts = pm_read16(PM1_STS); + ps->pm1_en = pm_read16(PM1_EN); ps->pm1_cnt = pmc_read_pm1_control(); printk(BIOS_DEBUG, "pm1_sts: %04x pm1_en: %04x pm1_cnt: %08x\n", ps->pm1_sts, ps->pm1_en, ps->pm1_cnt); for (i = 0; i < GPE0_REG_MAX; i++) { - ps->gpe0_sts[i] = inl(ACPI_BASE_ADDRESS + GPE0_STS(i)); - ps->gpe0_en[i] = inl(ACPI_BASE_ADDRESS + GPE0_EN(i)); + ps->gpe0_sts[i] = pm_read32(GPE0_STS(i)); + ps->gpe0_en[i] = pm_read32(GPE0_EN(i)); printk(BIOS_DEBUG, "gpe0_sts[%d]: %08x gpe0_en[%d]: %08x\n", i, ps->gpe0_sts[i], i, ps->gpe0_en[i]); } @@ -480,7 +460,7 @@ return acpi_get_sleep_type() == ACPI_S3; /* Read power state from PMC ABASE */ - if (!(inw(ACPI_BASE_ADDRESS + PM1_STS) & WAK_STS)) + if (!(pm_read16(PM1_STS) & WAK_STS)) return 0; return acpi_sleep_from_pm1(pmc_read_pm1_control()) == ACPI_S3; @@ -506,9 +486,9 @@ if (stopwatch_expired(&sw)) return rc; - sts = inl(ACPI_BASE_ADDRESS + GPE0_STS(bank)); + sts = pm_read32(GPE0_STS(bank)); if (sts & mask) { - outl(mask, ACPI_BASE_ADDRESS + GPE0_STS(bank)); + pm_write32(GPE0_STS(bank), mask); rc = 1; } } while (sts & mask); diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c index 0a277f0..f5e3e37 100644 --- a/src/soc/intel/common/block/smm/smihandler.c +++ b/src/soc/intel/common/block/smm/smihandler.c @@ -156,7 +156,7 @@ /* First, disable further SMIs */ pmc_disable_smi(SLP_SMI_EN); /* Figure out SLP_TYP */ - reg32 = inl(ACPI_BASE_ADDRESS + PM1_CNT); + reg32 = pm_read32(PM1_CNT); printk(BIOS_SPEW, "SMI#: SLP = 0x%08x\n", reg32); slp_typ = acpi_sleep_from_pm1(reg32); diff --git a/src/soc/intel/common/block/smm/smitraphandler.c b/src/soc/intel/common/block/smm/smitraphandler.c index 99825f1..2d26f94 100644 --- a/src/soc/intel/common/block/smm/smitraphandler.c +++ b/src/soc/intel/common/block/smm/smitraphandler.c @@ -43,7 +43,7 @@ void smihandler_southbridge_mc( const struct smm_save_state_ops *save_state_ops) { - u32 reg32 = inl(ACPI_BASE_ADDRESS + SMI_EN); + u32 reg32 = pm_read32(SMI_EN); /* Are microcontroller SMIs enabled? */ if ((reg32 & MCSMI_EN) == 0) diff --git a/src/soc/intel/skylake/pmc.c b/src/soc/intel/skylake/pmc.c index 61662d2..bf2357c 100644 --- a/src/soc/intel/skylake/pmc.c +++ b/src/soc/intel/skylake/pmc.c @@ -84,10 +84,7 @@ S4MAW_4S | SLP_S3_MIN_ASST_WDTH_50MS | DIS_SLP_X_STRCH_SUS_UP); /* Enable SCI and clear SLP requests. */ - reg32 = inl(ACPI_BASE_ADDRESS + PM1_CNT); - reg32 &= ~SLP_TYP; - reg32 |= SCI_EN; - outl(reg32, ACPI_BASE_ADDRESS + PM1_CNT); + pm_clrsetbits32(PM1_CNT, SLP_TYP, SCI_EN); pmc_set_acpi_mode(); -- To view, visit https://review.coreboot.org/c/coreboot/+/70050 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I473ebefcf8e0c929f6cbf6b5c0d7e8f5af72856d Gerrit-Change-Number: 70050 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: [WIP] sb/intel/common: Rename and inline {read,write}_pmbaseX()
by Kyösti Mälkki (Code Review) 26 Nov '22

26 Nov '22

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/70049 ) Change subject: [WIP] sb/intel/common: Rename and inline {read,write}_pmbaseX() ...................................................................... [WIP] sb/intel/common: Rename and inline {read,write}_pmbaseX() Renames {read,write}_pmbaseX to pm_{read,write}X. Inlining allows for static, compile-time assertions and possibility to easily add register tracing for debugging. Change-Id: Ia3b88e93b9dca298585e6906f92842f4cafab2e2 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/southbridge/intel/common/pmbase.c M src/southbridge/intel/common/pmbase.h 2 files changed, 119 insertions(+), 52 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/70049/1 diff --git a/src/southbridge/intel/common/pmbase.c b/src/southbridge/intel/common/pmbase.c index ba7111b..46b8518 100644 --- a/src/southbridge/intel/common/pmbase.c +++ b/src/southbridge/intel/common/pmbase.c @@ -1,8 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> -#include <arch/io.h> -#include <assert.h> #include <bootmode.h> #include <device/pci_ops.h> #include <device/pci_type.h> @@ -11,8 +9,6 @@ #include "pmbase.h" #include "pmutil.h" -#define PMSIZE 0x80 - #if !CONFIG(SOUTHBRIDGE_INTEL_LYNXPOINT) && !CONFIG(SOC_INTEL_BAYTRAIL) && \ !CONFIG(SOC_INTEL_BRASWELL) @@ -46,48 +42,6 @@ } #endif -void write_pmbase32(const u8 addr, const u32 val) -{ - ASSERT(addr <= (PMSIZE - sizeof(u32))); - - outl(val, get_pmbase() + addr); -} - -void write_pmbase16(const u8 addr, const u16 val) -{ - ASSERT(addr <= (PMSIZE - sizeof(u16))); - - outw(val, get_pmbase() + addr); -} - -void write_pmbase8(const u8 addr, const u8 val) -{ - ASSERT(addr <= (PMSIZE - sizeof(u8))); - - outb(val, get_pmbase() + addr); -} - -u32 read_pmbase32(const u8 addr) -{ - ASSERT(addr <= (PMSIZE - sizeof(u32))); - - return inl(get_pmbase() + addr); -} - -u16 read_pmbase16(const u8 addr) -{ - ASSERT(addr <= (PMSIZE - sizeof(u16))); - - return inw(get_pmbase() + addr); -} - -u8 read_pmbase8(const u8 addr) -{ - ASSERT(addr <= (PMSIZE - sizeof(u8))); - - return inb(get_pmbase() + addr); -} - int acpi_get_sleep_type(void) { return acpi_sleep_from_pm1(read_pmbase32(PM1_CNT)); diff --git a/src/southbridge/intel/common/pmbase.h b/src/southbridge/intel/common/pmbase.h index 451c3f5..171ce4a 100644 --- a/src/southbridge/intel/common/pmbase.h +++ b/src/southbridge/intel/common/pmbase.h @@ -3,8 +3,24 @@ #ifndef __INTEL_COMMON_PMBASE__ #define __INTEL_COMMON_PMBASE__ +#include <arch/io_bitops.h> +#include <assert.h> #include <stdint.h> +#if CONFIG(SOUTHBRIDGE_INTEL_LYNXPOINT) || CONFIG(SOC_INTEL_BROADWELL) +/* Wider GPIO space, TCO range is in the middle 0x60..0x80. */ +#define PMSIZE 0x100 +#elif CONFIG(TCO_SPACE_NOT_YET_SPLIT) +/* Must let TCO registers 0x60..0x80 through. */ +#define PMSIZE 0x80 +#elif CONFIG(SOC_INTEL_COMMON_BLOCK_TCO_ENABLE_THROUGH_SMBUS) +/* TCO registers 0x60..0x80 moved, these are now GPEs. */ +#define PMSIZE 0x80 +#else +/* Only allow true PM registers, the ones below TCO. */ +#define PMSIZE 0x60 +#endif + /* FIXME: ENV_SMM must reload base on each entry to SMI ? */ #define HAVE_DYNAMIC_ACPI_BASE_ADDRESS ENV_SMM @@ -45,12 +61,94 @@ } #endif -void write_pmbase32(const u8 addr, const u32 val); -void write_pmbase16(const u8 addr, const u16 val); -void write_pmbase8(const u8 addr, const u8 val); +static __always_inline void pm_write32(const u16 addr, const u32 val) +{ + ASSERT(addr <= (PMSIZE - sizeof(u32))); + io_write32(get_pmbase() + addr, val); +} -u32 read_pmbase32(const u8 addr); -u16 read_pmbase16(const u8 addr); -u8 read_pmbase8(const u8 addr); +static __always_inline void pm_write16(const u16 addr, const u16 val) +{ + ASSERT(addr <= (PMSIZE - sizeof(u16))); + io_write16(get_pmbase() + addr, val); +} + +static __always_inline void pm_write8(const u16 addr, const u8 val) +{ + ASSERT(addr <= (PMSIZE - sizeof(u8))); + io_write8(get_pmbase() + addr, val); +} + +static __always_inline u32 pm_read32(const u16 addr) +{ + ASSERT(addr <= (PMSIZE - sizeof(u32))); + return io_read32(get_pmbase() + addr); +} + +static __always_inline u16 pm_read16(const u16 addr) +{ + ASSERT(addr <= (PMSIZE - sizeof(u16))); + return io_read16(get_pmbase() + addr); +} + +static __always_inline u8 pm_read8(const u16 addr) +{ + ASSERT(addr <= (PMSIZE - sizeof(u8))); + return io_read8(get_pmbase() + addr); +} + +static __always_inline u32 pm_rwc32(const u16 addr) +{ + ASSERT(addr <= (PMSIZE - sizeof(u32))); + return io_rwc32(get_pmbase() + addr); +} + +static __always_inline u16 pm_rwc16(const u16 addr) +{ + ASSERT(addr <= (PMSIZE - sizeof(u16))); + return io_rwc16(get_pmbase() + addr); +} + +static __always_inline u8 pm_rwc8(const u16 addr) +{ + ASSERT(addr <= (PMSIZE - sizeof(u8))); + return io_rwc8(get_pmbase() + addr); +} + +static __always_inline void pm_clrsetbits32(const u16 addr, const u32 clr, const u32 set) +{ + ASSERT(addr <= (PMSIZE - sizeof(u32))); + io_clrsetbits32(get_pmbase() + addr, clr, set); +} + +static __always_inline void pm_clrsetbits16(const u16 addr, const u16 clr, const u16 set) +{ + ASSERT(addr <= (PMSIZE - sizeof(u16))); + io_clrsetbits16(get_pmbase() + addr, clr, set); +} + +static __always_inline void pm_clrsetbits8(const u16 addr, const u8 clr, const u8 set) +{ + ASSERT(addr <= (PMSIZE - sizeof(u8))); + io_clrsetbits8(get_pmbase() + addr, clr, set); +} + +#define pm_setbits32(addr, set) pm_clrsetbits32(addr, 0, set) +#define pm_setbits16(addr, set) pm_clrsetbits16(addr, 0, set) +#define pm_setbits8(addr, set) pm_clrsetbits8(addr, 0, set) + +#define pm_clrbits32(addr, clr) pm_clrsetbits32(addr, clr, 0) +#define pm_clrbits16(addr, clr) pm_clrsetbits16(addr, clr, 0) +#define pm_clrbits8(addr, clr) pm_clrsetbits8(addr, clr, 0) + + + +/* Transitional macros */ +#define write_pmbase32 pm_write32 +#define write_pmbase16 pm_write16 +#define write_pmbase8 pm_write8 +#define read_pmbase32 pm_read32 +#define read_pmbase16 pm_read16 +#define read_pmbase8 pm_read8 #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/70049 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia3b88e93b9dca298585e6906f92842f4cafab2e2 Gerrit-Change-Number: 70049 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: sb,soc/intel/common: Add common get_pmbase()
by Kyösti Mälkki (Code Review) 26 Nov '22

26 Nov '22

Attention is currently required from: Tarun Tuli, Sean Rhodes, Subrata Banik, Jonathan Zhang, Johnny Lin, Kapil Porwal, Christian Walter, Angel Pons, Arthur Heymans, Lean Sheng Tan, Werner Zeh, Tim Chu. Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/70048 ) Change subject: sb,soc/intel/common: Add common get_pmbase() ...................................................................... sb,soc/intel/common: Add common get_pmbase() Change-Id: Idda34aa376caef94383699e6c17ed1f588bca37e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/northbridge/intel/haswell/gma.c M src/soc/intel/alderlake/acpi.c M src/soc/intel/alderlake/include/soc/pm.h M src/soc/intel/alderlake/pmutil.c M src/soc/intel/apollolake/acpi.c M src/soc/intel/apollolake/include/soc/pm.h M src/soc/intel/apollolake/pmutil.c M src/soc/intel/cannonlake/acpi.c M src/soc/intel/cannonlake/include/soc/pm.h M src/soc/intel/cannonlake/pmutil.c M src/soc/intel/common/block/acpi/acpi.c M src/soc/intel/elkhartlake/acpi.c M src/soc/intel/elkhartlake/include/soc/pm.h M src/soc/intel/elkhartlake/pmutil.c M src/soc/intel/icelake/acpi.c M src/soc/intel/icelake/include/soc/pm.h M src/soc/intel/icelake/pmutil.c M src/soc/intel/jasperlake/acpi.c M src/soc/intel/jasperlake/include/soc/pm.h M src/soc/intel/jasperlake/pmutil.c M src/soc/intel/meteorlake/acpi.c M src/soc/intel/meteorlake/include/soc/pm.h M src/soc/intel/meteorlake/pmutil.c M src/soc/intel/quark/include/soc/pm.h M src/soc/intel/skylake/fadt.c M src/soc/intel/skylake/include/soc/pm.h M src/soc/intel/skylake/pmutil.c M src/soc/intel/tigerlake/acpi.c M src/soc/intel/tigerlake/include/soc/pm.h M src/soc/intel/tigerlake/pmutil.c M src/soc/intel/xeon_sp/include/soc/pm.h M src/soc/intel/xeon_sp/pmutil.c M src/soc/intel/xeon_sp/skx/soc_acpi.c M src/southbridge/intel/common/pmbase.c M src/southbridge/intel/common/pmbase.h M src/southbridge/intel/common/pmutil.h M src/southbridge/intel/common/smi.c M src/southbridge/intel/common/smihandler.c M src/southbridge/intel/lynxpoint/elog.c M src/southbridge/intel/lynxpoint/fadt.c M src/southbridge/intel/lynxpoint/lpc.c M src/southbridge/intel/lynxpoint/pch.c M src/southbridge/intel/lynxpoint/pch.h M src/southbridge/intel/lynxpoint/pmutil.c M src/southbridge/intel/lynxpoint/smi.c M src/southbridge/intel/lynxpoint/smihandler.c 46 files changed, 108 insertions(+), 127 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/70048/1 diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index 6e6948b..7e48f5c 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -15,6 +15,7 @@ #include <drivers/intel/gma/libgfxinit.h> #include <cpu/intel/haswell/haswell.h> #include <drivers/intel/gma/opregion.h> +#include <southbridge/intel/common/pmbase.h> #include <southbridge/intel/lynxpoint/pch.h> #include <types.h> diff --git a/src/soc/intel/alderlake/acpi.c b/src/soc/intel/alderlake/acpi.c index 1c820c2..7e5f6ac 100644 --- a/src/soc/intel/alderlake/acpi.c +++ b/src/soc/intel/alderlake/acpi.c @@ -163,7 +163,7 @@ void soc_fill_fadt(acpi_fadt_t *fadt) { - const uint16_t pmbase = ACPI_BASE_ADDRESS; + const uint16_t pmbase = get_pmbase(); config_t *config = config_of_soc(); diff --git a/src/soc/intel/alderlake/include/soc/pm.h b/src/soc/intel/alderlake/include/soc/pm.h index 98843d1..7a00444 100644 --- a/src/soc/intel/alderlake/include/soc/pm.h +++ b/src/soc/intel/alderlake/include/soc/pm.h @@ -137,6 +137,7 @@ #include <soc/iomap.h> #include <soc/smbus.h> #include <soc/pmc.h> +#include <southbridge/intel/common/pmbase.h> struct chipset_power_state { uint16_t pm1_sts; @@ -162,7 +163,5 @@ /* Set the DISB after DRAM init */ void pmc_set_disb(void); -/* STM Support */ -uint16_t get_pmbase(void); #endif /* !defined(__ACPI__) */ #endif diff --git a/src/soc/intel/alderlake/pmutil.c b/src/soc/intel/alderlake/pmutil.c index 9389322..300ac71 100644 --- a/src/soc/intel/alderlake/pmutil.c +++ b/src/soc/intel/alderlake/pmutil.c @@ -250,12 +250,6 @@ printk(BIOS_DEBUG, "HPR_CAUSE0: %08x\n", ps->hpr_cause0); } -/* STM Support */ -uint16_t get_pmbase(void) -{ - return (uint16_t) ACPI_BASE_ADDRESS; -} - /* * Set which power state system will be after reapplying * the power (from G3 State) diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index 811c762..d601f93 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -98,7 +98,7 @@ const struct soc_intel_apollolake_config *cfg; cfg = config_of_soc(); - fadt->pm_tmr_blk = ACPI_BASE_ADDRESS + PM1_TMR; + fadt->pm_tmr_blk = get_pmbase() + PM1_TMR; fadt->pm_tmr_len = 4; diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h index c1dee0c..3cd5c8d 100644 --- a/src/soc/intel/apollolake/include/soc/pm.h +++ b/src/soc/intel/apollolake/include/soc/pm.h @@ -7,6 +7,7 @@ #include <acpi/acpi.h> #include <soc/gpe.h> #include <soc/iomap.h> +#include <southbridge/intel/common/pmbase.h> /* ACPI_BASE_ADDRESS */ @@ -244,7 +245,4 @@ /* Get base address PMC memory mapped registers. */ uint8_t *pmc_mmio_regs(void); -/* STM Support */ -uint16_t get_pmbase(void); - #endif diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c index f474553..765b2c8 100644 --- a/src/soc/intel/apollolake/pmutil.c +++ b/src/soc/intel/apollolake/pmutil.c @@ -218,12 +218,6 @@ return rtc_failure; } -/* STM Support */ -uint16_t get_pmbase(void) -{ - return (uint16_t) ACPI_BASE_ADDRESS; -} - void pmc_soc_set_afterg3_en(const bool on) { const uintptr_t gen_pmcon1 = soc_read_pmc_base() + GEN_PMCON1; diff --git a/src/soc/intel/cannonlake/acpi.c b/src/soc/intel/cannonlake/acpi.c index 0b898a8..e6eebf4 100644 --- a/src/soc/intel/cannonlake/acpi.c +++ b/src/soc/intel/cannonlake/acpi.c @@ -147,7 +147,7 @@ void soc_fill_fadt(acpi_fadt_t *fadt) { - const uint16_t pmbase = ACPI_BASE_ADDRESS; + const uint16_t pmbase = get_pmbase(); const struct soc_intel_cannonlake_config *config; config = config_of_soc(); diff --git a/src/soc/intel/cannonlake/include/soc/pm.h b/src/soc/intel/cannonlake/include/soc/pm.h index 863d9f9..3b0c14d 100644 --- a/src/soc/intel/cannonlake/include/soc/pm.h +++ b/src/soc/intel/cannonlake/include/soc/pm.h @@ -131,6 +131,7 @@ #include <soc/iomap.h> #include <soc/smbus.h> #include <soc/pmc.h> +#include <southbridge/intel/common/pmbase.h> struct chipset_power_state { uint16_t pm1_sts; @@ -156,8 +157,5 @@ /* Set the DISB after DRAM init */ void pmc_set_disb(void); -/* STM Support */ -uint16_t get_pmbase(void); - #endif /* !defined(__ACPI__) */ #endif diff --git a/src/soc/intel/cannonlake/pmutil.c b/src/soc/intel/cannonlake/pmutil.c index 7df8d47..2219f65 100644 --- a/src/soc/intel/cannonlake/pmutil.c +++ b/src/soc/intel/cannonlake/pmutil.c @@ -243,12 +243,6 @@ printk(BIOS_DEBUG, "HPR_CAUSE0: %08x\n", ps->hpr_cause0); } -/* STM Support */ -uint16_t get_pmbase(void) -{ - return (uint16_t) ACPI_BASE_ADDRESS; -} - /* * Set which power state system will be after reapplying * the power (from G3 State) diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index 860c868..ece3d11 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -107,7 +107,7 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) { - const uint16_t pmbase = ACPI_BASE_ADDRESS; + const uint16_t pmbase = get_pmbase(); fadt->sci_int = acpi_sci_irq(); diff --git a/src/soc/intel/elkhartlake/acpi.c b/src/soc/intel/elkhartlake/acpi.c index 091b785..3842391 100644 --- a/src/soc/intel/elkhartlake/acpi.c +++ b/src/soc/intel/elkhartlake/acpi.c @@ -146,7 +146,7 @@ void soc_fill_fadt(acpi_fadt_t *fadt) { - const uint16_t pmbase = ACPI_BASE_ADDRESS; + const uint16_t pmbase = get_pmbase(); config_t *config = config_of_soc(); diff --git a/src/soc/intel/elkhartlake/include/soc/pm.h b/src/soc/intel/elkhartlake/include/soc/pm.h index 6a86787..4a3fde2 100644 --- a/src/soc/intel/elkhartlake/include/soc/pm.h +++ b/src/soc/intel/elkhartlake/include/soc/pm.h @@ -131,6 +131,7 @@ #include <soc/iomap.h> #include <soc/smbus.h> #include <soc/pmc.h> +#include <southbridge/intel/common/pmbase.h> struct chipset_power_state { uint16_t pm1_sts; @@ -155,7 +156,5 @@ /* Set the DISB after DRAM init */ void pmc_set_disb(void); -/* STM Support */ -uint16_t get_pmbase(void); #endif /* !defined(__ACPI__) */ #endif diff --git a/src/soc/intel/elkhartlake/pmutil.c b/src/soc/intel/elkhartlake/pmutil.c index 76a9cd3..7dee348 100644 --- a/src/soc/intel/elkhartlake/pmutil.c +++ b/src/soc/intel/elkhartlake/pmutil.c @@ -256,12 +256,6 @@ ps->gblrst_cause[0], ps->gblrst_cause[1]); } -/* STM Support */ -uint16_t get_pmbase(void) -{ - return (uint16_t) ACPI_BASE_ADDRESS; -} - /* * Set which power state system will be after reapplying * the power (from G3 State) diff --git a/src/soc/intel/icelake/acpi.c b/src/soc/intel/icelake/acpi.c index 9781927..cc95445 100644 --- a/src/soc/intel/icelake/acpi.c +++ b/src/soc/intel/icelake/acpi.c @@ -143,7 +143,7 @@ void soc_fill_fadt(acpi_fadt_t *fadt) { - const uint16_t pmbase = ACPI_BASE_ADDRESS; + const uint16_t pmbase = get_pmbase(); config_t *config = config_of_soc(); diff --git a/src/soc/intel/icelake/include/soc/pm.h b/src/soc/intel/icelake/include/soc/pm.h index 05db830..d4a385a 100644 --- a/src/soc/intel/icelake/include/soc/pm.h +++ b/src/soc/intel/icelake/include/soc/pm.h @@ -131,6 +131,7 @@ #include <soc/iomap.h> #include <soc/smbus.h> #include <soc/pmc.h> +#include <southbridge/intel/common/pmbase.h> struct chipset_power_state { uint16_t pm1_sts; @@ -155,8 +156,5 @@ /* Set the DISB after DRAM init */ void pmc_set_disb(void); -/* STM Support */ -uint16_t get_pmbase(void); - #endif /* !defined(__ACPI__) */ #endif diff --git a/src/soc/intel/icelake/pmutil.c b/src/soc/intel/icelake/pmutil.c index 9297ffd..f1d4d21 100644 --- a/src/soc/intel/icelake/pmutil.c +++ b/src/soc/intel/icelake/pmutil.c @@ -256,12 +256,6 @@ ps->gblrst_cause[0], ps->gblrst_cause[1]); } -/* STM Support */ -uint16_t get_pmbase(void) -{ - return (uint16_t) ACPI_BASE_ADDRESS; -} - /* * Set which power state system will be after reapplying * the power (from G3 State) diff --git a/src/soc/intel/jasperlake/acpi.c b/src/soc/intel/jasperlake/acpi.c index 369eb02..cf69825 100644 --- a/src/soc/intel/jasperlake/acpi.c +++ b/src/soc/intel/jasperlake/acpi.c @@ -146,7 +146,7 @@ void soc_fill_fadt(acpi_fadt_t *fadt) { - const uint16_t pmbase = ACPI_BASE_ADDRESS; + const uint16_t pmbase = get_pmbase(); config_t *config = config_of_soc(); diff --git a/src/soc/intel/jasperlake/include/soc/pm.h b/src/soc/intel/jasperlake/include/soc/pm.h index eea875b..d4a385a 100644 --- a/src/soc/intel/jasperlake/include/soc/pm.h +++ b/src/soc/intel/jasperlake/include/soc/pm.h @@ -131,6 +131,7 @@ #include <soc/iomap.h> #include <soc/smbus.h> #include <soc/pmc.h> +#include <southbridge/intel/common/pmbase.h> struct chipset_power_state { uint16_t pm1_sts; @@ -155,7 +156,5 @@ /* Set the DISB after DRAM init */ void pmc_set_disb(void); -/* STM Support */ -uint16_t get_pmbase(void); #endif /* !defined(__ACPI__) */ #endif diff --git a/src/soc/intel/jasperlake/pmutil.c b/src/soc/intel/jasperlake/pmutil.c index f2a4c90..7e00ca5 100644 --- a/src/soc/intel/jasperlake/pmutil.c +++ b/src/soc/intel/jasperlake/pmutil.c @@ -256,12 +256,6 @@ ps->gblrst_cause[0], ps->gblrst_cause[1]); } -/* STM Support */ -uint16_t get_pmbase(void) -{ - return (uint16_t) ACPI_BASE_ADDRESS; -} - /* * Set which power state system will be after reapplying * the power (from G3 State) diff --git a/src/soc/intel/meteorlake/acpi.c b/src/soc/intel/meteorlake/acpi.c index 54de566..f7d1de7 100644 --- a/src/soc/intel/meteorlake/acpi.c +++ b/src/soc/intel/meteorlake/acpi.c @@ -149,7 +149,7 @@ void soc_fill_fadt(acpi_fadt_t *fadt) { - const uint16_t pmbase = ACPI_BASE_ADDRESS; + const uint16_t pmbase = get_pmbase(); config_t *config = config_of_soc(); diff --git a/src/soc/intel/meteorlake/include/soc/pm.h b/src/soc/intel/meteorlake/include/soc/pm.h index c486232..e23b96c 100644 --- a/src/soc/intel/meteorlake/include/soc/pm.h +++ b/src/soc/intel/meteorlake/include/soc/pm.h @@ -131,6 +131,7 @@ #include <soc/iomap.h> #include <soc/smbus.h> #include <soc/pmc.h> +#include <southbridge/intel/common/pmbase.h> struct chipset_power_state { uint16_t pm1_sts; @@ -156,7 +157,5 @@ /* Set the DISB after DRAM init */ void pmc_set_disb(void); -/* STM Support */ -uint16_t get_pmbase(void); #endif /* !defined(__ACPI__) */ #endif diff --git a/src/soc/intel/meteorlake/pmutil.c b/src/soc/intel/meteorlake/pmutil.c index 974f966..29ef32f 100644 --- a/src/soc/intel/meteorlake/pmutil.c +++ b/src/soc/intel/meteorlake/pmutil.c @@ -241,12 +241,6 @@ printk(BIOS_DEBUG, "HPR_CAUSE0: %08x\n", ps->hpr_cause0); } -/* STM Support */ -uint16_t get_pmbase(void) -{ - return (uint16_t) ACPI_BASE_ADDRESS; -} - /* * Set which power state system will be after reapplying * the power (from G3 State) diff --git a/src/soc/intel/quark/include/soc/pm.h b/src/soc/intel/quark/include/soc/pm.h index 7a08c6e..408feb3 100644 --- a/src/soc/intel/quark/include/soc/pm.h +++ b/src/soc/intel/quark/include/soc/pm.h @@ -13,7 +13,5 @@ struct chipset_power_state *get_power_state(void); int fill_power_state(void); -/* STM Support */ -uint16_t get_pmbase(void); #endif /* _SOC_PM_H_ */ diff --git a/src/soc/intel/skylake/fadt.c b/src/soc/intel/skylake/fadt.c index a1b3e43..99a02df 100644 --- a/src/soc/intel/skylake/fadt.c +++ b/src/soc/intel/skylake/fadt.c @@ -8,7 +8,7 @@ void soc_fill_fadt(acpi_fadt_t *fadt) { - const uint16_t pmbase = ACPI_BASE_ADDRESS; + const uint16_t pmbase = get_pmbase(); config_t *config = config_of_soc(); fadt->pm2_cnt_blk = pmbase + PM2_CNT; diff --git a/src/soc/intel/skylake/include/soc/pm.h b/src/soc/intel/skylake/include/soc/pm.h index f0ce146..02bd555 100644 --- a/src/soc/intel/skylake/include/soc/pm.h +++ b/src/soc/intel/skylake/include/soc/pm.h @@ -8,6 +8,7 @@ #include <soc/gpe.h> #include <soc/iomap.h> #include <soc/pmc.h> +#include <southbridge/intel/common/pmbase.h> #include <soc/smbus.h> /* ACPI_BASE_ADDRESS / PMBASE */ @@ -186,7 +187,4 @@ return !!(deep_s5_pol & (S5DC_GATE_SUS | S5AC_GATE_SUS)); } -/* STM Support */ -uint16_t get_pmbase(void); - #endif diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c index fe26ebf..c234e30 100644 --- a/src/soc/intel/skylake/pmutil.c +++ b/src/soc/intel/skylake/pmutil.c @@ -243,12 +243,6 @@ ps->gblrst_cause[0], ps->gblrst_cause[1]); } -/* STM Support */ -uint16_t get_pmbase(void) -{ - return ACPI_BASE_ADDRESS; -} - /* * Set which power state system will be after reapplying * the power (from G3 State) diff --git a/src/soc/intel/tigerlake/acpi.c b/src/soc/intel/tigerlake/acpi.c index 573dc5f..68d2452 100644 --- a/src/soc/intel/tigerlake/acpi.c +++ b/src/soc/intel/tigerlake/acpi.c @@ -146,7 +146,7 @@ void soc_fill_fadt(acpi_fadt_t *fadt) { - const uint16_t pmbase = ACPI_BASE_ADDRESS; + const uint16_t pmbase = get_pmbase(); config_t *config = config_of_soc(); diff --git a/src/soc/intel/tigerlake/include/soc/pm.h b/src/soc/intel/tigerlake/include/soc/pm.h index cb0781a..d782464 100644 --- a/src/soc/intel/tigerlake/include/soc/pm.h +++ b/src/soc/intel/tigerlake/include/soc/pm.h @@ -137,6 +137,7 @@ #include <soc/iomap.h> #include <soc/smbus.h> #include <soc/pmc.h> +#include <southbridge/intel/common/pmbase.h> struct chipset_power_state { uint16_t pm1_sts; @@ -162,7 +163,5 @@ /* Set the DISB after DRAM init */ void pmc_set_disb(void); -/* STM Support */ -uint16_t get_pmbase(void); #endif /* !defined(__ACPI__) */ #endif diff --git a/src/soc/intel/tigerlake/pmutil.c b/src/soc/intel/tigerlake/pmutil.c index 9aca5c2..1fb2b07 100644 --- a/src/soc/intel/tigerlake/pmutil.c +++ b/src/soc/intel/tigerlake/pmutil.c @@ -265,12 +265,6 @@ printk(BIOS_DEBUG, "HPR_CAUSE0: %08x\n", ps->hpr_cause0); } -/* STM Support */ -uint16_t get_pmbase(void) -{ - return (uint16_t) ACPI_BASE_ADDRESS; -} - /* * Set which power state system will be after reapplying * the power (from G3 State) diff --git a/src/soc/intel/xeon_sp/include/soc/pm.h b/src/soc/intel/xeon_sp/include/soc/pm.h index b4d6df9..a3f2d68 100644 --- a/src/soc/intel/xeon_sp/include/soc/pm.h +++ b/src/soc/intel/xeon_sp/include/soc/pm.h @@ -7,6 +7,7 @@ #include <soc/gpe.h> #include <soc/iomap.h> #include <soc/pmc.h> +#include <southbridge/intel/common/pmbase.h> /* ACPI_BASE_ADDRESS / PMBASE */ #define PM1_STS 0x00 @@ -117,8 +118,6 @@ /* Get base address PMC memory mapped registers. */ uint8_t *pmc_mmio_regs(void); -uint16_t get_pmbase(void); - void pmc_lock_smi(void); #endif diff --git a/src/soc/intel/xeon_sp/pmutil.c b/src/soc/intel/xeon_sp/pmutil.c index c63285c..0051e04 100644 --- a/src/soc/intel/xeon_sp/pmutil.c +++ b/src/soc/intel/xeon_sp/pmutil.c @@ -159,12 +159,6 @@ ps->gblrst_cause[0], ps->gblrst_cause[1]); } -/* STM Support */ -uint16_t get_pmbase(void) -{ - return ACPI_BASE_ADDRESS; -} - /* * Set which power state system will be after reapplying * the power (from G3 State) diff --git a/src/soc/intel/xeon_sp/skx/soc_acpi.c b/src/soc/intel/xeon_sp/skx/soc_acpi.c index 88f24d4..7358693 100644 --- a/src/soc/intel/xeon_sp/skx/soc_acpi.c +++ b/src/soc/intel/xeon_sp/skx/soc_acpi.c @@ -36,7 +36,7 @@ void soc_fill_fadt(acpi_fadt_t *fadt) { - const uint16_t pmbase = ACPI_BASE_ADDRESS; + const uint16_t pmbase = get_pmbase(); /* Fix flags set by common/block/acpi/acpi.c acpi_fill_fadt() */ fadt->flags &= ~(ACPI_FADT_SEALED_CASE); diff --git a/src/southbridge/intel/common/pmbase.c b/src/southbridge/intel/common/pmbase.c index 2fddfc9..ba7111b 100644 --- a/src/southbridge/intel/common/pmbase.c +++ b/src/southbridge/intel/common/pmbase.c @@ -11,9 +11,13 @@ #include "pmbase.h" #include "pmutil.h" +#define PMSIZE 0x80 + +#if !CONFIG(SOUTHBRIDGE_INTEL_LYNXPOINT) && !CONFIG(SOC_INTEL_BAYTRAIL) && \ + !CONFIG(SOC_INTEL_BRASWELL) + /* LPC PM Base Address Register */ #define PMBASE 0x40 -#define PMSIZE 0x80 u16 lpc_get_pmbase(void) { @@ -21,57 +25,67 @@ /* Don't assume PMBASE is still the same */ return pci_read_config16(PCI_DEV(0, 0x1f, 0), PMBASE) & 0xfffc; #else + return pci_read_config16(pcidev_on_root(0x1f, 0), PMBASE) & 0xfffc; +#endif +} +#endif + +#if HAVE_DYNAMIC_ACPI_BASE_ADDRESS +u16 get_pmbase(void) +{ static u16 pmbase; + if (ENV_SMM) + return lpc_get_pmbase(); + if (pmbase) return pmbase; - - pmbase = pci_read_config16(pcidev_on_root(0x1f, 0), PMBASE) & 0xfffc; + pmbase = lpc_get_pmbase(); return pmbase; -#endif } +#endif void write_pmbase32(const u8 addr, const u32 val) { ASSERT(addr <= (PMSIZE - sizeof(u32))); - outl(val, lpc_get_pmbase() + addr); + outl(val, get_pmbase() + addr); } void write_pmbase16(const u8 addr, const u16 val) { ASSERT(addr <= (PMSIZE - sizeof(u16))); - outw(val, lpc_get_pmbase() + addr); + outw(val, get_pmbase() + addr); } void write_pmbase8(const u8 addr, const u8 val) { ASSERT(addr <= (PMSIZE - sizeof(u8))); - outb(val, lpc_get_pmbase() + addr); + outb(val, get_pmbase() + addr); } u32 read_pmbase32(const u8 addr) { ASSERT(addr <= (PMSIZE - sizeof(u32))); - return inl(lpc_get_pmbase() + addr); + return inl(get_pmbase() + addr); } u16 read_pmbase16(const u8 addr) { ASSERT(addr <= (PMSIZE - sizeof(u16))); - return inw(lpc_get_pmbase() + addr); + return inw(get_pmbase() + addr); } u8 read_pmbase8(const u8 addr) { ASSERT(addr <= (PMSIZE - sizeof(u8))); - return inb(lpc_get_pmbase() + addr); + return inb(get_pmbase() + addr); } int acpi_get_sleep_type(void) diff --git a/src/southbridge/intel/common/pmbase.h b/src/southbridge/intel/common/pmbase.h index febcff2..451c3f5 100644 --- a/src/southbridge/intel/common/pmbase.h +++ b/src/southbridge/intel/common/pmbase.h @@ -1,9 +1,50 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef __INTEL_COMMON_PMBASE__ +#define __INTEL_COMMON_PMBASE__ + #include <stdint.h> +/* FIXME: ENV_SMM must reload base on each entry to SMI ? */ +#define HAVE_DYNAMIC_ACPI_BASE_ADDRESS ENV_SMM + u16 lpc_get_pmbase(void); +/* FIXME: Implement <soc/iomap.h>, only DEFAULT_PMBASE needed. + We already have <soc/nvs.h> for similar case on GNVS. */ +#if CONFIG(SOUTHBRIDGE_INTEL_I82371EB) +#include <southbridge/intel/i82371eb/i82371eb.h> +#elif CONFIG(SOUTHBRIDGE_INTEL_I82801DX) +#include <southbridge/intel/i82801dx/i82801dx.h> +#elif CONFIG(SOUTHBRIDGE_INTEL_I82801GX) +#include <southbridge/intel/i82801gx/i82801gx.h> +#elif CONFIG(SOUTHBRIDGE_INTEL_I82801IX) +#include <southbridge/intel/i82801ix/i82801ix.h> +#elif CONFIG(SOUTHBRIDGE_INTEL_I82801JX) +#include <southbridge/intel/i82801jx/i82801jx.h> +#elif CONFIG(SOUTHBRIDGE_INTEL_BD82X6X) || CONFIG(SOUTHBRIDGE_INTEL_C216) +#include <southbridge/intel/bd82x6x/pch.h> +#elif CONFIG(SOUTHBRIDGE_INTEL_LYNXPOINT) +#include <southbridge/intel/lynxpoint/pch.h> +#else + +/* ENV_SMM can use static value if PM BAR is locked? */ +#undef HAVE_DYNAMIC_ACPI_BASE_ADDRESS +#define HAVE_DYNAMIC_ACPI_BASE_ADDRESS 0 + +#include <soc/iomap.h> +#define DEFAULT_PMBASE ACPI_BASE_ADDRESS +#endif + +#if HAVE_DYNAMIC_ACPI_BASE_ADDRESS +u16 get_pmbase(void); +#else +static __always_inline u16 get_pmbase(void) +{ + return DEFAULT_PMBASE; +} +#endif + void write_pmbase32(const u8 addr, const u32 val); void write_pmbase16(const u8 addr, const u16 val); void write_pmbase8(const u8 addr, const u8 val); @@ -11,3 +52,5 @@ u32 read_pmbase32(const u8 addr); u16 read_pmbase16(const u8 addr); u8 read_pmbase8(const u8 addr); + +#endif diff --git a/src/southbridge/intel/common/pmutil.h b/src/southbridge/intel/common/pmutil.h index 744b1c1..9c06112 100644 --- a/src/southbridge/intel/common/pmutil.h +++ b/src/southbridge/intel/common/pmutil.h @@ -114,8 +114,6 @@ #define TCO2_CNT 0x6a #endif -u16 get_pmbase(void); - u16 reset_pm1_status(void); void dump_pm1_status(u16 pm1_sts); void dump_tco_status(u32 tco_sts); diff --git a/src/southbridge/intel/common/smi.c b/src/southbridge/intel/common/smi.c index a6e000b..00441ce 100644 --- a/src/southbridge/intel/common/smi.c +++ b/src/southbridge/intel/common/smi.c @@ -10,11 +10,6 @@ #include "pmutil.h" -u16 get_pmbase(void) -{ - return lpc_get_pmbase(); -} - static int smi_enabled(void) { u32 smi_en; diff --git a/src/southbridge/intel/common/smihandler.c b/src/southbridge/intel/common/smihandler.c index 798f2f1..c7853eb 100644 --- a/src/southbridge/intel/common/smihandler.c +++ b/src/southbridge/intel/common/smihandler.c @@ -17,11 +17,6 @@ #include "pmutil.h" -u16 get_pmbase(void) -{ - return lpc_get_pmbase(); -} - void gpi_route_interrupt(u8 gpi, u8 mode) { u32 gpi_rout; diff --git a/src/southbridge/intel/lynxpoint/elog.c b/src/southbridge/intel/lynxpoint/elog.c index a775146..fa06759 100644 --- a/src/southbridge/intel/lynxpoint/elog.c +++ b/src/southbridge/intel/lynxpoint/elog.c @@ -5,6 +5,7 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ops.h> +#include <southbridge/intel/common/pmbase.h> #include <southbridge/intel/common/pmutil.h> #include <stdint.h> #include <elog.h> diff --git a/src/southbridge/intel/lynxpoint/fadt.c b/src/southbridge/intel/lynxpoint/fadt.c index 2051223..d9e3619 100644 --- a/src/southbridge/intel/lynxpoint/fadt.c +++ b/src/southbridge/intel/lynxpoint/fadt.c @@ -3,6 +3,7 @@ #include <device/pci_ops.h> #include <acpi/acpi.h> #include <cpu/x86/smm.h> +#include <southbridge/intel/common/pmbase.h> #include <southbridge/intel/lynxpoint/pch.h> #include "chip.h" diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index b8e9d5f..3476db2 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -17,6 +17,7 @@ #include "pch.h" #include <acpi/acpigen.h> #include <southbridge/intel/common/acpi_pirq_gen.h> +#include <southbridge/intel/common/pmbase.h> #include <southbridge/intel/common/rcba_pirq.h> #include <southbridge/intel/common/rtc.h> #include <southbridge/intel/common/spi.h> diff --git a/src/southbridge/intel/lynxpoint/pch.c b/src/southbridge/intel/lynxpoint/pch.c index 8f7cdb8..448f74c8 100644 --- a/src/southbridge/intel/lynxpoint/pch.c +++ b/src/southbridge/intel/lynxpoint/pch.c @@ -5,6 +5,7 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_def.h> +#include <southbridge/intel/common/pmbase.h> #include "iobp.h" #include "pch.h" @@ -56,14 +57,9 @@ return PCH_TYPE_DESKTOP; } -u16 get_pmbase(void) +u16 lpc_get_pmbase(void) { - static u16 pmbase; - - if (!pmbase) - pmbase = pci_read_config16(pch_get_lpc_device(), - PMBASE) & 0xfffc; - return pmbase; + return pci_read_config16(pch_get_lpc_device(), PMBASE) & 0xfffc; } u16 get_gpiobase(void) diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 3ed434a..3f78534 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -120,7 +120,6 @@ enum pch_platform_type get_pch_platform_type(void); int pch_silicon_revision(void); int pch_silicon_id(void); -u16 get_pmbase(void); u16 get_gpiobase(void); /* Power Management register handling in pmutil.c */ diff --git a/src/southbridge/intel/lynxpoint/pmutil.c b/src/southbridge/intel/lynxpoint/pmutil.c index dd7f199..fa62eca 100644 --- a/src/southbridge/intel/lynxpoint/pmutil.c +++ b/src/southbridge/intel/lynxpoint/pmutil.c @@ -12,6 +12,7 @@ #include <console/console.h> #include <security/vboot/vbnv.h> #include <security/vboot/vboot_common.h> +#include <southbridge/intel/common/pmbase.h> #include <southbridge/intel/common/rtc.h> #include "pch.h" diff --git a/src/southbridge/intel/lynxpoint/smi.c b/src/southbridge/intel/lynxpoint/smi.c index 280235f..327058f 100644 --- a/src/southbridge/intel/lynxpoint/smi.c +++ b/src/southbridge/intel/lynxpoint/smi.c @@ -6,6 +6,7 @@ #include <arch/io.h> #include <cpu/intel/smm_reloc.h> #include <cpu/x86/smm.h> +#include <southbridge/intel/common/pmbase.h> #include <southbridge/intel/common/pmutil.h> #include "pch.h" diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c index 769cacb..8edd986 100644 --- a/src/southbridge/intel/lynxpoint/smihandler.c +++ b/src/southbridge/intel/lynxpoint/smihandler.c @@ -12,6 +12,7 @@ #include <halt.h> #include <option.h> #include <southbridge/intel/common/finalize.h> +#include <southbridge/intel/common/pmbase.h> #include <northbridge/intel/haswell/haswell.h> #include <cpu/intel/haswell/haswell.h> #include <soc/nvs.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/70048 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idda34aa376caef94383699e6c17ed1f588bca37e Gerrit-Change-Number: 70048 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: sb,soc/intel: Drop spurious SMI entry message
by Kyösti Mälkki (Code Review) 26 Nov '22

26 Nov '22

Attention is currently required from: Jeff Daly, Vanessa Eusebio. Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/70047 ) Change subject: sb,soc/intel: Drop spurious SMI entry message ...................................................................... sb,soc/intel: Drop spurious SMI entry message The message only makes sense if ACPI PM base address is allowed to be dynamic. If requested, it can be logged in common code. Change-Id: Iad7a60098c0391cc23384035af49e373dad90233 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/intel/baytrail/smm.c M src/soc/intel/braswell/smm.c M src/soc/intel/broadwell/pch/smi.c M src/soc/intel/denverton_ns/smm.c M src/southbridge/intel/common/smi.c M src/southbridge/intel/lynxpoint/smi.c 6 files changed, 15 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/70047/1 diff --git a/src/soc/intel/baytrail/smm.c b/src/soc/intel/baytrail/smm.c index 3f3c53f..ed83173 100644 --- a/src/soc/intel/baytrail/smm.c +++ b/src/soc/intel/baytrail/smm.c @@ -27,8 +27,6 @@ if (CONFIG(ELOG)) southcluster_log_state(); - printk(BIOS_DEBUG, "Initializing Southbridge SMI..."); - printk(BIOS_SPEW, " pmbase = 0x%04x\n", get_pmbase()); smi_en = inl(get_pmbase() + SMI_EN); if (smi_en & APMC_EN) { diff --git a/src/soc/intel/braswell/smm.c b/src/soc/intel/braswell/smm.c index 3f3c53f..64e560e 100644 --- a/src/soc/intel/braswell/smm.c +++ b/src/soc/intel/braswell/smm.c @@ -27,9 +27,6 @@ if (CONFIG(ELOG)) southcluster_log_state(); - printk(BIOS_DEBUG, "Initializing Southbridge SMI..."); - printk(BIOS_SPEW, " pmbase = 0x%04x\n", get_pmbase()); - smi_en = inl(get_pmbase() + SMI_EN); if (smi_en & APMC_EN) { printk(BIOS_INFO, "SMI# handler already enabled?\n"); diff --git a/src/soc/intel/broadwell/pch/smi.c b/src/soc/intel/broadwell/pch/smi.c index d7704fd..51f31a1 100644 --- a/src/soc/intel/broadwell/pch/smi.c +++ b/src/soc/intel/broadwell/pch/smi.c @@ -14,17 +14,12 @@ { u32 smi_en; - printk(BIOS_DEBUG, "Initializing Southbridge SMI..."); - printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", ACPI_BASE_ADDRESS); - smi_en = inl(ACPI_BASE_ADDRESS + SMI_EN); if (smi_en & APMC_EN) { printk(BIOS_INFO, "SMI# handler already enabled?\n"); return; } - printk(BIOS_DEBUG, "\n"); - /* Dump and clear status registers */ clear_smi_status(); clear_pm1_status(); diff --git a/src/soc/intel/denverton_ns/smm.c b/src/soc/intel/denverton_ns/smm.c index e7ed28d..bb399e8 100644 --- a/src/soc/intel/denverton_ns/smm.c +++ b/src/soc/intel/denverton_ns/smm.c @@ -16,9 +16,6 @@ { uint32_t smi_en; - printk(BIOS_DEBUG, "Initializing Southbridge SMI..."); - printk(BIOS_SPEW, " pmbase = 0x%04x\n", get_pmbase()); - smi_en = inl((uint16_t)(get_pmbase() + SMI_EN)); if (smi_en & APMC_EN) { printk(BIOS_INFO, "SMI# handler already enabled?\n"); diff --git a/src/southbridge/intel/common/smi.c b/src/southbridge/intel/common/smi.c index 20926e5..a6e000b 100644 --- a/src/southbridge/intel/common/smi.c +++ b/src/southbridge/intel/common/smi.c @@ -23,15 +23,12 @@ if (CONFIG(ELOG)) pch_log_state(); - printk(BIOS_DEBUG, "Initializing southbridge SMI..."); - printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", lpc_get_pmbase()); - smi_en = read_pmbase32(SMI_EN); if (smi_en & APMC_EN) { printk(BIOS_INFO, "SMI# handler already enabled?\n"); return 1; } - printk(BIOS_DEBUG, "\n"); + return 0; } diff --git a/src/southbridge/intel/lynxpoint/smi.c b/src/southbridge/intel/lynxpoint/smi.c index 70d9dc1..280235f 100644 --- a/src/southbridge/intel/lynxpoint/smi.c +++ b/src/southbridge/intel/lynxpoint/smi.c @@ -18,17 +18,12 @@ if (CONFIG(ELOG)) pch_log_state(); - printk(BIOS_DEBUG, "Initializing Southbridge SMI..."); - printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", get_pmbase()); - smi_en = inl(get_pmbase() + SMI_EN); if (smi_en & APMC_EN) { printk(BIOS_INFO, "SMI# handler already enabled?\n"); return; } - printk(BIOS_DEBUG, "\n"); - /* Dump and clear status registers */ clear_smi_status(); clear_pm1_status(); -- To view, visit https://review.coreboot.org/c/coreboot/+/70047 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iad7a60098c0391cc23384035af49e373dad90233 Gerrit-Change-Number: 70047 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: sb/intel/lynxpoint: Get pch_log_state() from pmutil.h
by Kyösti Mälkki (Code Review) 26 Nov '22

26 Nov '22

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/70046 ) Change subject: sb/intel/lynxpoint: Get pch_log_state() from pmutil.h ...................................................................... sb/intel/lynxpoint: Get pch_log_state() from pmutil.h Change-Id: Ifa9ce168225e4fe880ce6da4971cc5cff456215a Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/southbridge/intel/lynxpoint/elog.c M src/southbridge/intel/lynxpoint/pch.h M src/southbridge/intel/lynxpoint/smi.c 3 files changed, 12 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/70046/1 diff --git a/src/southbridge/intel/lynxpoint/elog.c b/src/southbridge/intel/lynxpoint/elog.c index e73a7ed..a775146 100644 --- a/src/southbridge/intel/lynxpoint/elog.c +++ b/src/southbridge/intel/lynxpoint/elog.c @@ -5,6 +5,7 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ops.h> +#include <southbridge/intel/common/pmutil.h> #include <stdint.h> #include <elog.h> #include "pch.h" diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 35649f6..3ed434a 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -150,7 +150,6 @@ void pch_enable(struct device *dev); void pch_disable_devfn(struct device *dev); -void pch_log_state(void); void acpi_create_serialio_ssdt(acpi_header_t *ssdt); void enable_usb_bar(void); diff --git a/src/southbridge/intel/lynxpoint/smi.c b/src/southbridge/intel/lynxpoint/smi.c index 6edf5c1..70d9dc1 100644 --- a/src/southbridge/intel/lynxpoint/smi.c +++ b/src/southbridge/intel/lynxpoint/smi.c @@ -6,6 +6,7 @@ #include <arch/io.h> #include <cpu/intel/smm_reloc.h> #include <cpu/x86/smm.h> +#include <southbridge/intel/common/pmutil.h> #include "pch.h" -- To view, visit https://review.coreboot.org/c/coreboot/+/70046 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifa9ce168225e4fe880ce6da4971cc5cff456215a Gerrit-Change-Number: 70046 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: sb/intel/common: Rename TCO timeout
by Kyösti Mälkki (Code Review) 26 Nov '22

26 Nov '22

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/70045 ) Change subject: sb/intel/common: Rename TCO timeout ...................................................................... sb/intel/common: Rename TCO timeout Rename TCO1_TIMEOUT to TCO_TIMEOUT to match rest of the tree. Change-Id: Ib136e9b2d0006eb4ceceb298b557644760d1185c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/southbridge/intel/bd82x6x/pch.h M src/southbridge/intel/common/tco.h M src/southbridge/intel/common/watchdog.c 3 files changed, 15 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/70045/1 diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 3aef48a..8155479 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -466,7 +466,7 @@ #if CONFIG(TCO_SPACE_NOT_YET_SPLIT) #define TCO1_STS 0x64 -#define TCO1_TIMEOUT (1 << 3) +#define TCO_TIMEOUT (1 << 3) #define DMISCI_STS (1 << 9) #define TCO2_STS 0x66 #define TCO2_STS_SECOND_TO (1 << 1) diff --git a/src/southbridge/intel/common/tco.h b/src/southbridge/intel/common/tco.h index 168971e..5bf386f 100644 --- a/src/southbridge/intel/common/tco.h +++ b/src/southbridge/intel/common/tco.h @@ -13,7 +13,7 @@ #define PMBASE_TCO_OFFSET 0x60 #define TCO1_STS 0x04 -#define TCO1_TIMEOUT (1 << 3) +#define TCO_TIMEOUT (1 << 3) #define TCO2_STS 0x06 #define TCO2_STS_SECOND_TO (1 << 1) #define TCO1_CNT 0x08 diff --git a/src/southbridge/intel/common/watchdog.c b/src/southbridge/intel/common/watchdog.c index a988691..e22dbfb 100644 --- a/src/southbridge/intel/common/watchdog.c +++ b/src/southbridge/intel/common/watchdog.c @@ -32,7 +32,7 @@ write_pmbase16(PMBASE_TCO_OFFSET + TCO1_CNT, value); /* Clear TCO timeout status. */ - write_pmbase16(PMBASE_TCO_OFFSET + TCO1_STS, TCO1_TIMEOUT); + write_pmbase16(PMBASE_TCO_OFFSET + TCO1_STS, TCO_TIMEOUT); write_pmbase16(PMBASE_TCO_OFFSET + TCO2_STS, TCO2_STS_SECOND_TO); printk(BIOS_DEBUG, "ICH-NM10-PCH: watchdog disabled\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/70045 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib136e9b2d0006eb4ceceb298b557644760d1185c Gerrit-Change-Number: 70045 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: sb,soc/intel: Address TCO SECOND_TO_STS name collision
by Kyösti Mälkki (Code Review) 26 Nov '22

26 Nov '22

Attention is currently required from: Tarun Tuli, Sean Rhodes, Subrata Banik, Jonathan Zhang, Johnny Lin, Kapil Porwal, Christian Walter, Arthur Heymans, Tim Chu. Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/70044 ) Change subject: sb,soc/intel: Address TCO SECOND_TO_STS name collision ...................................................................... sb,soc/intel: Address TCO SECOND_TO_STS name collision Later soc/intel/common/smbus addresses TCO2_STS as a separate 16-bit register, while baytrail and braswell assumes 32-bit wide TCO1_STS to extend as TCO2_STS. In src/soc/intel/denverton_ns: #define TCO2_STS_SECOND_TO 0x02 In soc/intel/baytrail,braswell: #define SECOND_TO_STS (1 << 17) Elsewehere #define SECOND_TO_STS (1 << 1) It's expected that we remove the first (1 << 17) case and only access TCO2_STS as a separate 16-bit register. For now, use unique names to avoid confusion. Change-Id: I07cc46a9d600b2bf2f23588b26891268e9ce4de0 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/intel/alderlake/elog.c M src/soc/intel/apollolake/include/soc/smbus.h M src/soc/intel/baytrail/elog.c M src/soc/intel/baytrail/include/soc/pm.h M src/soc/intel/braswell/elog.c M src/soc/intel/braswell/include/soc/pm.h M src/soc/intel/cannonlake/elog.c M src/soc/intel/common/block/smbus/tco.c M src/soc/intel/common/pch/include/intelpch/smbus.h M src/soc/intel/icelake/elog.c M src/soc/intel/jasperlake/elog.c M src/soc/intel/meteorlake/elog.c M src/soc/intel/skylake/elog.c M src/soc/intel/tigerlake/elog.c M src/soc/intel/xeon_sp/include/soc/smbus.h M src/southbridge/intel/bd82x6x/pch.h M src/southbridge/intel/common/tco.h M src/southbridge/intel/common/watchdog.c M src/southbridge/intel/lynxpoint/elog.c M src/southbridge/intel/lynxpoint/pch.h 20 files changed, 47 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/70044/1 diff --git a/src/soc/intel/alderlake/elog.c b/src/soc/intel/alderlake/elog.c index 7f79d94..b87130f 100644 --- a/src/soc/intel/alderlake/elog.c +++ b/src/soc/intel/alderlake/elog.c @@ -170,7 +170,7 @@ /* TCO Timeout */ if (ps->prev_sleep_state != ACPI_S3 && - ps->tco2_sts & TCO_STS_SECOND_TO) + ps->tco2_sts & TCO2_STS_SECOND_TO) elog_add_event(ELOG_TYPE_TCO_RESET); /* Power Button Override */ diff --git a/src/soc/intel/apollolake/include/soc/smbus.h b/src/soc/intel/apollolake/include/soc/smbus.h index e11119c..a87211a 100644 --- a/src/soc/intel/apollolake/include/soc/smbus.h +++ b/src/soc/intel/apollolake/include/soc/smbus.h @@ -7,7 +7,7 @@ #define TCO1_STS 0x04 #define TCO_TIMEOUT (1 << 3) #define TCO2_STS 0x06 -#define TCO_STS_SECOND_TO (1 << 1) +#define TCO2_STS_SECOND_TO (1 << 1) #define TCO_INTRD_DET (1 << 0) #define TCO1_CNT 0x08 #define TCO_LOCK (1 << 12) diff --git a/src/soc/intel/baytrail/elog.c b/src/soc/intel/baytrail/elog.c index f732fab..ecdbfca 100644 --- a/src/soc/intel/baytrail/elog.c +++ b/src/soc/intel/baytrail/elog.c @@ -22,7 +22,7 @@ if (ps->gen_pmcon1 & RPS) elog_add_event(ELOG_TYPE_RTC_RESET); - if (ps->tco_sts & SECOND_TO_STS) + if (ps->tco_sts & TCO1_32_STS_SECOND_TO_STS) elog_add_event(ELOG_TYPE_TCO_RESET); if (ps->pm1_sts & PRBTNOR_STS) diff --git a/src/soc/intel/baytrail/include/soc/pm.h b/src/soc/intel/baytrail/include/soc/pm.h index 1db5038..5154105 100644 --- a/src/soc/intel/baytrail/include/soc/pm.h +++ b/src/soc/intel/baytrail/include/soc/pm.h @@ -226,7 +226,7 @@ #if CONFIG(TCO_SPACE_NOT_YET_SPLIT) #define TCO_RLD 0x60 #define TCO_STS 0x64 -# define SECOND_TO_STS (1 << 17) +# define TCO1_32_STS_SECOND_TO_STS (1 << 17) # define TCO_TIMEOUT (1 << 3) #define TCO1_CNT 0x68 # define TCO_LOCK (1 << 12) diff --git a/src/soc/intel/braswell/elog.c b/src/soc/intel/braswell/elog.c index f732fab..ecdbfca 100644 --- a/src/soc/intel/braswell/elog.c +++ b/src/soc/intel/braswell/elog.c @@ -22,7 +22,7 @@ if (ps->gen_pmcon1 & RPS) elog_add_event(ELOG_TYPE_RTC_RESET); - if (ps->tco_sts & SECOND_TO_STS) + if (ps->tco_sts & TCO1_32_STS_SECOND_TO_STS) elog_add_event(ELOG_TYPE_TCO_RESET); if (ps->pm1_sts & PRBTNOR_STS) diff --git a/src/soc/intel/braswell/include/soc/pm.h b/src/soc/intel/braswell/include/soc/pm.h index 131a996..b918577 100644 --- a/src/soc/intel/braswell/include/soc/pm.h +++ b/src/soc/intel/braswell/include/soc/pm.h @@ -188,7 +188,7 @@ #if CONFIG(TCO_SPACE_NOT_YET_SPLIT) #define TCO_RLD 0x60 #define TCO_STS 0x64 -# define SECOND_TO_STS (1 << 17) +# define TCO1_32_STS_SECOND_TO_STS (1 << 17) # define TCO_TIMEOUT (1 << 3) #define TCO1_CNT 0x68 # define TCO_LOCK (1 << 12) diff --git a/src/soc/intel/cannonlake/elog.c b/src/soc/intel/cannonlake/elog.c index dcc1a79..f8d0651 100644 --- a/src/soc/intel/cannonlake/elog.c +++ b/src/soc/intel/cannonlake/elog.c @@ -135,7 +135,7 @@ /* TCO Timeout */ if (ps->prev_sleep_state != ACPI_S3 && - ps->tco2_sts & TCO_STS_SECOND_TO) + ps->tco2_sts & TCO2_STS_SECOND_TO) elog_add_event(ELOG_TYPE_TCO_RESET); /* Power Button Override */ diff --git a/src/soc/intel/common/block/smbus/tco.c b/src/soc/intel/common/block/smbus/tco.c index 1ca8842..12b176c 100644 --- a/src/soc/intel/common/block/smbus/tco.c +++ b/src/soc/intel/common/block/smbus/tco.c @@ -72,7 +72,7 @@ /* TCO Status 2 register */ tco2_sts = tco_read_reg(TCO2_STS); - tco_write_reg(TCO2_STS, tco2_sts | TCO_STS_SECOND_TO); + tco_write_reg(TCO2_STS, tco2_sts | TCO2_STS_SECOND_TO); return (tco2_sts << 16) | tco1_sts; } diff --git a/src/soc/intel/common/pch/include/intelpch/smbus.h b/src/soc/intel/common/pch/include/intelpch/smbus.h index 238da2b..78b7953 100644 --- a/src/soc/intel/common/pch/include/intelpch/smbus.h +++ b/src/soc/intel/common/pch/include/intelpch/smbus.h @@ -7,7 +7,7 @@ #define TCO1_STS 0x04 #define TCO_TIMEOUT (1 << 3) #define TCO2_STS 0x06 -#define TCO_STS_SECOND_TO (1 << 1) +#define TCO2_STS_SECOND_TO (1 << 1) #define TCO_INTRD_DET (1 << 0) #define TCO1_CNT 0x08 #define TCO_LOCK (1 << 12) diff --git a/src/soc/intel/icelake/elog.c b/src/soc/intel/icelake/elog.c index 4967fde..01f133a 100644 --- a/src/soc/intel/icelake/elog.c +++ b/src/soc/intel/icelake/elog.c @@ -70,7 +70,7 @@ /* TCO Timeout */ if (ps->prev_sleep_state != ACPI_S3 && - ps->tco2_sts & TCO_STS_SECOND_TO) + ps->tco2_sts & TCO2_STS_SECOND_TO) elog_add_event(ELOG_TYPE_TCO_RESET); /* Power Button Override */ diff --git a/src/soc/intel/jasperlake/elog.c b/src/soc/intel/jasperlake/elog.c index 0e4b2c5..f42e06c 100644 --- a/src/soc/intel/jasperlake/elog.c +++ b/src/soc/intel/jasperlake/elog.c @@ -143,7 +143,7 @@ /* TCO Timeout */ if (ps->prev_sleep_state != ACPI_S3 && - ps->tco2_sts & TCO_STS_SECOND_TO) + ps->tco2_sts & TCO2_STS_SECOND_TO) elog_add_event(ELOG_TYPE_TCO_RESET); /* Power Button Override */ diff --git a/src/soc/intel/meteorlake/elog.c b/src/soc/intel/meteorlake/elog.c index 35100f9..14d086c 100644 --- a/src/soc/intel/meteorlake/elog.c +++ b/src/soc/intel/meteorlake/elog.c @@ -173,7 +173,7 @@ /* TCO Timeout */ if (ps->prev_sleep_state != ACPI_S3 && - ps->tco2_sts & TCO_STS_SECOND_TO) + ps->tco2_sts & TCO2_STS_SECOND_TO) elog_add_event(ELOG_TYPE_TCO_RESET); /* Power Button Override */ diff --git a/src/soc/intel/skylake/elog.c b/src/soc/intel/skylake/elog.c index 1761671..325bacb 100644 --- a/src/soc/intel/skylake/elog.c +++ b/src/soc/intel/skylake/elog.c @@ -202,7 +202,7 @@ /* TCO Timeout */ if (ps->prev_sleep_state != ACPI_S3 && - ps->tco2_sts & TCO_STS_SECOND_TO) + ps->tco2_sts & TCO2_STS_SECOND_TO) elog_add_event(ELOG_TYPE_TCO_RESET); /* Power Button Override */ diff --git a/src/soc/intel/tigerlake/elog.c b/src/soc/intel/tigerlake/elog.c index 29f1712..650d1cd 100644 --- a/src/soc/intel/tigerlake/elog.c +++ b/src/soc/intel/tigerlake/elog.c @@ -178,7 +178,7 @@ /* TCO Timeout */ if (ps->prev_sleep_state != ACPI_S3 && - ps->tco2_sts & TCO_STS_SECOND_TO) + ps->tco2_sts & TCO2_STS_SECOND_TO) elog_add_event(ELOG_TYPE_TCO_RESET); /* Power Button Override */ diff --git a/src/soc/intel/xeon_sp/include/soc/smbus.h b/src/soc/intel/xeon_sp/include/soc/smbus.h index 00aae2c..7ef9d0b 100644 --- a/src/soc/intel/xeon_sp/include/soc/smbus.h +++ b/src/soc/intel/xeon_sp/include/soc/smbus.h @@ -7,7 +7,7 @@ #define TCO1_STS 0x04 #define TCO_TIMEOUT (1 << 3) #define TCO2_STS 0x06 -#define TCO_STS_SECOND_TO (1 << 1) +#define TCO2_STS_SECOND_TO (1 << 1) #define TCO_INTRD_DET (1 << 0) #define TCO1_CNT 0x08 #define TCO_LOCK (1 << 12) diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index b5e05f6..3aef48a 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -469,7 +469,7 @@ #define TCO1_TIMEOUT (1 << 3) #define DMISCI_STS (1 << 9) #define TCO2_STS 0x66 -#define SECOND_TO_STS (1 << 1) +#define TCO2_STS_SECOND_TO (1 << 1) #define TCO1_CNT 0x68 #define TCO_TMR_HLT (1 << 11) #define TCO_LOCK (1 << 12) diff --git a/src/southbridge/intel/common/tco.h b/src/southbridge/intel/common/tco.h index 4c3f639..168971e 100644 --- a/src/southbridge/intel/common/tco.h +++ b/src/southbridge/intel/common/tco.h @@ -15,7 +15,7 @@ #define TCO1_STS 0x04 #define TCO1_TIMEOUT (1 << 3) #define TCO2_STS 0x06 -#define SECOND_TO_STS (1 << 1) +#define TCO2_STS_SECOND_TO (1 << 1) #define TCO1_CNT 0x08 #define TCO_TMR_HLT (1 << 11) diff --git a/src/southbridge/intel/common/watchdog.c b/src/southbridge/intel/common/watchdog.c index b40c5fe..a988691 100644 --- a/src/southbridge/intel/common/watchdog.c +++ b/src/southbridge/intel/common/watchdog.c @@ -33,7 +33,7 @@ /* Clear TCO timeout status. */ write_pmbase16(PMBASE_TCO_OFFSET + TCO1_STS, TCO1_TIMEOUT); - write_pmbase16(PMBASE_TCO_OFFSET + TCO2_STS, SECOND_TO_STS); + write_pmbase16(PMBASE_TCO_OFFSET + TCO2_STS, TCO2_STS_SECOND_TO); printk(BIOS_DEBUG, "ICH-NM10-PCH: watchdog disabled\n"); } diff --git a/src/southbridge/intel/lynxpoint/elog.c b/src/southbridge/intel/lynxpoint/elog.c index 839773a..e73a7ed 100644 --- a/src/southbridge/intel/lynxpoint/elog.c +++ b/src/southbridge/intel/lynxpoint/elog.c @@ -124,7 +124,7 @@ elog_add_event(ELOG_TYPE_PWROK_FAIL); /* Second TCO Timeout */ - if (tco2_sts & SECOND_TO_STS) + if (tco2_sts & TCO2_STS_SECOND_TO) elog_add_event(ELOG_TYPE_TCO_RESET); /* Power Button Override */ diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 0d8be7b..35649f6 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -623,7 +623,7 @@ #define TCO1_STS 0x64 #define DMISCI_STS (1 << 9) #define TCO2_STS 0x66 -#define SECOND_TO_STS (1 << 1) +#define TCO2_STS_SECOND_TO (1 << 1) #endif #define ALT_GP_SMI_EN2 0x5c -- To view, visit https://review.coreboot.org/c/coreboot/+/70044 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I07cc46a9d600b2bf2f23588b26891268e9ce4de0 Gerrit-Change-Number: 70044 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: sb,soc/intel: Apply transitional flag TCO_SPACE_NOT_YET_SPLIT
by Kyösti Mälkki (Code Review) 26 Nov '22

26 Nov '22

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/70043 ) Change subject: sb,soc/intel: Apply transitional flag TCO_SPACE_NOT_YET_SPLIT ...................................................................... sb,soc/intel: Apply transitional flag TCO_SPACE_NOT_YET_SPLIT Tree is inconsistent with the use of TCO register space offsets and related preprocessor defines. The legacy space was offset from ACPI PM base by 0x60, but this changed with later platforms. The convenient way is to define the TCO registers relative to its base address and subtract 0x60 here, but this change cannot be easily done tree-wide or in one go. For the transient period, apply TCO_SPACE_NOT_YET_SPLIT flag until all platforms use a clean style of tco_{read,write} accessor functions instead of {read,write}_pmbase16(), or worse, inw/outl(). Change-Id: I16213cdb13f98fccb261004b31e81a9a44cb6e3b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/intel/baytrail/Kconfig M src/soc/intel/baytrail/include/soc/pm.h M src/soc/intel/braswell/Kconfig M src/soc/intel/braswell/include/soc/pm.h M src/soc/intel/broadwell/Kconfig M src/soc/intel/broadwell/include/soc/pm.h M src/soc/intel/broadwell/pch/Kconfig M src/southbridge/intel/bd82x6x/Kconfig M src/southbridge/intel/bd82x6x/pch.h M src/southbridge/intel/common/Kconfig.common M src/southbridge/intel/common/pmutil.h M src/southbridge/intel/common/tco.h M src/southbridge/intel/i82801dx/Kconfig M src/southbridge/intel/i82801dx/i82801dx.h M src/southbridge/intel/i82801gx/Kconfig M src/southbridge/intel/i82801gx/i82801gx.h M src/southbridge/intel/i82801ix/Kconfig M src/southbridge/intel/i82801jx/Kconfig M src/southbridge/intel/ibexpeak/Kconfig M src/southbridge/intel/ibexpeak/pch.h M src/southbridge/intel/lynxpoint/Kconfig M src/southbridge/intel/lynxpoint/pch.h 22 files changed, 66 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/70043/1 diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index c2d24b2..5ecfe3e 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -34,6 +34,7 @@ select INTEL_GMA_SWSMISCI select CPU_INTEL_COMMON select CPU_HAS_L2_ENABLE_MSR + select TCO_SPACE_NOT_YET_SPLIT config VBOOT select VBOOT_MUST_REQUEST_DISPLAY diff --git a/src/soc/intel/baytrail/include/soc/pm.h b/src/soc/intel/baytrail/include/soc/pm.h index dc8a7fa..1db5038 100644 --- a/src/soc/intel/baytrail/include/soc/pm.h +++ b/src/soc/intel/baytrail/include/soc/pm.h @@ -222,6 +222,8 @@ # define UPRWC_WR_EN (1 << 1) /* USB Per-Port Registers Write Enable */ #define GPE_CTRL 0x40 #define PM2A_CNT_BLK 0x50 + +#if CONFIG(TCO_SPACE_NOT_YET_SPLIT) #define TCO_RLD 0x60 #define TCO_STS 0x64 # define SECOND_TO_STS (1 << 17) @@ -230,6 +232,7 @@ # define TCO_LOCK (1 << 12) # define TCO_TMR_HALT (1 << 11) #define TCO_TMR 0x70 +#endif /* I/O ports */ #define RST_CNT 0xcf9 diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index f297b8f..c35fa74 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -42,6 +42,7 @@ select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SPI_SILVERMONT select NO_CBFS_MCACHE + select TCO_SPACE_NOT_YET_SPLIT config DCACHE_BSP_STACK_SIZE hex diff --git a/src/soc/intel/braswell/include/soc/pm.h b/src/soc/intel/braswell/include/soc/pm.h index 6cb8d55..131a996 100644 --- a/src/soc/intel/braswell/include/soc/pm.h +++ b/src/soc/intel/braswell/include/soc/pm.h @@ -184,6 +184,8 @@ # define UPRWC_WR_EN (1 << 1) /* USB Per-Port Registers Write Enable */ #define GPE_CTRL 0x40 #define PM2A_CNT_BLK 0x50 + +#if CONFIG(TCO_SPACE_NOT_YET_SPLIT) #define TCO_RLD 0x60 #define TCO_STS 0x64 # define SECOND_TO_STS (1 << 17) @@ -192,6 +194,7 @@ # define TCO_LOCK (1 << 12) # define TCO_TMR_HALT (1 << 11) #define TCO_TMR 0x70 +#endif #if !defined(__ASSEMBLER__) && !defined(__ACPI__) diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 5b73f4f..3878f14 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -12,6 +12,7 @@ select INTEL_GMA_ACPI select MRC_SETTINGS_PROTECT select REG_SCRIPT + select TCO_SPACE_NOT_YET_SPLIT config BROADWELL_LPDDR3 bool diff --git a/src/soc/intel/broadwell/include/soc/pm.h b/src/soc/intel/broadwell/include/soc/pm.h index 52fd364..8bbc2de 100644 --- a/src/soc/intel/broadwell/include/soc/pm.h +++ b/src/soc/intel/broadwell/include/soc/pm.h @@ -53,12 +53,15 @@ #define SWGPE_CTRL (1 << 1) #define DEVACT_STS 0x44 #define PM2_CNT 0x50 + +#if CONFIG(TCO_SPACE_NOT_YET_SPLIT) #define TCO1_CNT 0x60 #define TCO_TMR_HLT (1 << 11) #define TCO1_STS 0x64 #define DMISCI_STS (1 << 9) #define TCO2_STS 0x66 #define TCO2_STS_SECOND_TO (1 << 1) +#endif #define GPE0_REG_MAX 4 #define GPE0_REG_SIZE 32 diff --git a/src/soc/intel/broadwell/pch/Kconfig b/src/soc/intel/broadwell/pch/Kconfig index 4e187ff..4800f3f 100644 --- a/src/soc/intel/broadwell/pch/Kconfig +++ b/src/soc/intel/broadwell/pch/Kconfig @@ -23,6 +23,7 @@ select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9 select SPI_FLASH + select TCO_SPACE_NOT_YET_SPLIT config EHCI_BAR hex diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig index 168c18e..7fee1f1 100644 --- a/src/southbridge/intel/bd82x6x/Kconfig +++ b/src/southbridge/intel/bd82x6x/Kconfig @@ -36,6 +36,7 @@ select SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG + select TCO_SPACE_NOT_YET_SPLIT config EHCI_BAR hex diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 2ebec62..b5e05f6 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -464,6 +464,7 @@ #define PM2_CNT 0x50 // mobile only #define C3_RES 0x54 +#if CONFIG(TCO_SPACE_NOT_YET_SPLIT) #define TCO1_STS 0x64 #define TCO1_TIMEOUT (1 << 3) #define DMISCI_STS (1 << 9) @@ -473,6 +474,7 @@ #define TCO_TMR_HLT (1 << 11) #define TCO_LOCK (1 << 12) #define TCO2_CNT 0x6a +#endif #define SPIBAR_HSFS 0x3804 /* SPI hardware sequence status */ #define SPIBAR_HSFS_SCIP (1 << 5) /* SPI Cycle In Progress */ diff --git a/src/southbridge/intel/common/Kconfig.common b/src/southbridge/intel/common/Kconfig.common index 5d7a4ee..0caf964 100644 --- a/src/southbridge/intel/common/Kconfig.common +++ b/src/southbridge/intel/common/Kconfig.common @@ -103,6 +103,9 @@ and S3 resume (always done by coreboot). Select this to let coreboot to do this on normal boot path. +config TCO_SPACE_NOT_YET_SPLIT + bool + config SOUTHBRIDGE_INTEL_COMMON_WATCHDOG bool depends on SOUTHBRIDGE_INTEL_COMMON_PMBASE diff --git a/src/southbridge/intel/common/pmutil.h b/src/southbridge/intel/common/pmutil.h index 5cf76b6..744b1c1 100644 --- a/src/southbridge/intel/common/pmutil.h +++ b/src/southbridge/intel/common/pmutil.h @@ -104,6 +104,7 @@ #define GPE_CNTL 0x42 #define DEVACT_STS 0x44 +#if CONFIG(TCO_SPACE_NOT_YET_SPLIT) #define TCO1_STS 0x64 #define DMISCI_STS (1 << 9) #define BOOT_STS (1 << 18) @@ -111,6 +112,7 @@ #define TCO1_CNT 0x68 #define TCO_LOCK (1 << 12) #define TCO2_CNT 0x6a +#endif u16 get_pmbase(void); diff --git a/src/southbridge/intel/common/tco.h b/src/southbridge/intel/common/tco.h index 03d3122..4c3f639 100644 --- a/src/southbridge/intel/common/tco.h +++ b/src/southbridge/intel/common/tco.h @@ -3,7 +3,15 @@ #ifndef SOUTHBRIDGE_INTEL_COMMON_TCO_H #define SOUTHBRIDGE_INTEL_COMMON_TCO_H +#if CONFIG(TCO_SPACE_NOT_YET_SPLIT) +/* Could get conflicting values. */ +#undef TCO1_STS +#undef TCO2_STS +#undef TCO1_CNT +#endif + #define PMBASE_TCO_OFFSET 0x60 + #define TCO1_STS 0x04 #define TCO1_TIMEOUT (1 << 3) #define TCO2_STS 0x06 diff --git a/src/southbridge/intel/i82801dx/Kconfig b/src/southbridge/intel/i82801dx/Kconfig index 391a59f..3916b41 100644 --- a/src/southbridge/intel/i82801dx/Kconfig +++ b/src/southbridge/intel/i82801dx/Kconfig @@ -13,6 +13,7 @@ select HAVE_POWER_STATE_AFTER_FAILURE select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE select BOOT_DEVICE_NOT_SPI_FLASH + select TCO_SPACE_NOT_YET_SPLIT if SOUTHBRIDGE_INTEL_I82801DX diff --git a/src/southbridge/intel/i82801dx/i82801dx.h b/src/southbridge/intel/i82801dx/i82801dx.h index 4c1366e..99f3af3 100644 --- a/src/southbridge/intel/i82801dx/i82801dx.h +++ b/src/southbridge/intel/i82801dx/i82801dx.h @@ -140,8 +140,10 @@ #define DEVACT_STS 0x44 #define SS_CNT 0x50 +#if CONFIG(TCO_SPACE_NOT_YET_SPLIT) /* TCO1 Control Register */ #define TCO1_CNT 0x68 +#endif #define GEN_PMCON_1 0xa0 #define GEN_PMCON_2 0xa2 diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig index 9e7259f..b1b885b 100644 --- a/src/southbridge/intel/i82801gx/Kconfig +++ b/src/southbridge/intel/i82801gx/Kconfig @@ -22,6 +22,7 @@ select SOUTHBRIDGE_INTEL_COMMON_RESET select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG select SOUTHBRIDGE_INTEL_COMMON_HPET + select TCO_SPACE_NOT_YET_SPLIT if SOUTHBRIDGE_INTEL_I82801GX diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index ee34f74..7088b64 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -323,7 +323,10 @@ #define DEVACT_STS 0x44 #define SS_CNT 0x50 #define C3_RES 0x54 + +#if CONFIG(TCO_SPACE_NOT_YET_SPLIT) #define TCO1_CNT 0x68 +#endif #endif /* __ACPI__ */ #endif /* SOUTHBRIDGE_INTEL_I82801GX_I82801GX_H */ diff --git a/src/southbridge/intel/i82801ix/Kconfig b/src/southbridge/intel/i82801ix/Kconfig index 0b45016..4d6b097 100644 --- a/src/southbridge/intel/i82801ix/Kconfig +++ b/src/southbridge/intel/i82801ix/Kconfig @@ -20,6 +20,7 @@ select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9 if !BOARD_EMULATION_QEMU_X86_Q35 select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG + select TCO_SPACE_NOT_YET_SPLIT select USE_WATCHDOG_ON_BOOT if SOUTHBRIDGE_INTEL_I82801IX diff --git a/src/southbridge/intel/i82801jx/Kconfig b/src/southbridge/intel/i82801jx/Kconfig index 13357c7..b189852 100644 --- a/src/southbridge/intel/i82801jx/Kconfig +++ b/src/southbridge/intel/i82801jx/Kconfig @@ -21,6 +21,7 @@ select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9 select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG + select TCO_SPACE_NOT_YET_SPLIT select USE_WATCHDOG_ON_BOOT if SOUTHBRIDGE_INTEL_I82801JX diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig index a79b3f7..fd5e322 100644 --- a/src/southbridge/intel/ibexpeak/Kconfig +++ b/src/southbridge/intel/ibexpeak/Kconfig @@ -32,6 +32,7 @@ select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG + select TCO_SPACE_NOT_YET_SPLIT config EHCI_BAR hex diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h index c42fe0f..5371641 100644 --- a/src/southbridge/intel/ibexpeak/pch.h +++ b/src/southbridge/intel/ibexpeak/pch.h @@ -445,9 +445,11 @@ #define PM2_CNT 0x50 // mobile only #define C3_RES 0x54 +#if CONFIG(TCO_SPACE_NOT_YET_SPLIT) #define TCO1_STS 0x64 #define DMISCI_STS (1 << 9) #define TCO2_STS 0x66 +#endif #define SPIBAR_HSFS 0x3804 /* SPI hardware sequence status */ #define SPIBAR_HSFS_SCIP (1 << 5) /* SPI Cycle In Progress */ diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig index b188251..ecfdea2 100644 --- a/src/southbridge/intel/lynxpoint/Kconfig +++ b/src/southbridge/intel/lynxpoint/Kconfig @@ -34,6 +34,7 @@ select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG + select TCO_SPACE_NOT_YET_SPLIT config INTEL_LYNXPOINT_LP bool diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index dcd3ce5..0d8be7b 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -619,10 +619,13 @@ #define PM2_CNT 0x50 // mobile only #define C3_RES 0x54 +#if CONFIG(TCO_SPACE_NOT_YET_SPLIT) #define TCO1_STS 0x64 #define DMISCI_STS (1 << 9) #define TCO2_STS 0x66 #define SECOND_TO_STS (1 << 1) +#endif + #define ALT_GP_SMI_EN2 0x5c #define ALT_GP_SMI_STS2 0x5e -- To view, visit https://review.coreboot.org/c/coreboot/+/70043 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I16213cdb13f98fccb261004b31e81a9a44cb6e3b Gerrit-Change-Number: 70043 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit November 2022