coreboot-gerrit November 2022

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: mb/google/skyrim: Store XHCI PCI BARs
by Robert Zieba (Code Review) 29 Nov '22

29 Nov '22

Attention is currently required from: Raul Rangel, Jason Nien, Martin Roth, Karthik Ramasubramanian. Robert Zieba has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68325 ) Change subject: mb/google/skyrim: Store XHCI PCI BARs ...................................................................... Patch Set 11: (2 comments) File src/mainboard/google/skyrim/mainboard.c: https://review.coreboot.org/c/coreboot/+/68325/comment/ef6f545e_e5995106 PS6, Line 133: const struct device *xhci[] = { : DEV_PTR(xhci_0), : DEV_PTR(xhci_1), : DEV_PTR(xhci_2) : }; > any reason to put this inside the function rather than above the function? Done https://review.coreboot.org/c/coreboot/+/68325/comment/97993eb5_bba1d6ca PS6, Line 138: > What about returning if elog isn't enabled? […] What's the concern with not returning early? If ELOG isn't selected then the BARs will be stored, but won't be used. -- To view, visit https://review.coreboot.org/c/coreboot/+/68325 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I529f541a8932267a8825773ddc582beafb27da63 Gerrit-Change-Number: 68325 Gerrit-PatchSet: 11 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 28 Nov 2022 23:25:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/amd/common/xhci: Add support for logging XHCI wake events
by Robert Zieba (Code Review) 29 Nov '22

29 Nov '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Angel Pons, Martin Roth, Fred Reitberger, Karthik Ramasubramanian, Felix Held. Robert Zieba has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67936 ) Change subject: soc/amd/common/xhci: Add support for logging XHCI wake events ...................................................................... Patch Set 12: (11 comments) File src/soc/amd/common/block/acpi/elog.c: https://review.coreboot.org/c/coreboot/+/67936/comment/789425e0_8eaf13f7 PS7, Line 34: if (i == XHCI_GEVENT) > can you use if (CONFIG(SOC_AMD_COMMON_BLOCK_XHCI_ELOG) && i == XHCI_GEVENT) so that this gets optimi […] Done File src/soc/amd/common/block/include/amdblocks/xhci.h: https://review.coreboot.org/c/coreboot/+/67936/comment/85722b60_ff84f1d9 PS10, Line 11: <stdint.h> > Isn't `size_t` in `<stddef.h>`? You can simply include `<types.h>` for convenience. Done https://review.coreboot.org/c/coreboot/+/67936/comment/a4026674_942c3afb PS10, Line 13: #define XHCI_GEVENT GEVENT_31 > Hmmm, what does this indirection achieve? This definition is just for clarity. When looking in source files it's much easier to see that `XHCI_GEVENT` is correct vs having to double check which event is used for XHCI events. File src/soc/amd/common/block/include/amdblocks/xhci.h: https://review.coreboot.org/c/coreboot/+/67936/comment/d681132e_0ae4d806 PS7, Line 19: #if CONFIG(SOC_AMD_COMMON_BLOCK_XHCI_ELOG) && ENV_SMM > It's best to rely on the linker optimizing away unreachable function calls. […] Done File src/soc/amd/common/block/xhci/Kconfig: https://review.coreboot.org/c/coreboot/+/67936/comment/9115d212_8561619e PS7, Line 9: && SMM_PCI_BAR_STORE > instead of making SMM_PCI_BAR_STORE a dependency, why not select it if this option is enabled? Done https://review.coreboot.org/c/coreboot/+/67936/comment/63316db6_b62a1be5 PS7, Line 9: SOC_AMD_COMMON_BLOCK_XHCI > I'd recommend that you use an `if SOC_AMD_COMMON_BLOCK_XHCI ... […] Done File src/soc/amd/common/block/xhci/elog.c: https://review.coreboot.org/c/coreboot/+/67936/comment/d1a7a033_48bf93f5 PS10, Line 20: base > Instead of incrementing the value of `base`, would it be clearer to write this as `base + i * PORTSC […] Done https://review.coreboot.org/c/coreboot/+/67936/comment/1c038ceb_0fce8337 PS10, Line 66: %d > nit: %u for unsigned types Done https://review.coreboot.org/c/coreboot/+/67936/comment/3ee640f5_8c870b06 PS10, Line 67: context->controller > reuse `controller` local variable? Done https://review.coreboot.org/c/coreboot/+/67936/comment/a2329917_6be92979 PS10, Line 93: %#lx > Hmmm, one would use `PRIxPTR` to display `uintptr_t` values Done https://review.coreboot.org/c/coreboot/+/67936/comment/6b7db4bd_1aa12412 PS10, Line 93: %d > nit: %u for unsigned types Done -- To view, visit https://review.coreboot.org/c/coreboot/+/67936 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic0489e1df55c4e63cb8a306099e3f31c82eebd58 Gerrit-Change-Number: 67936 Gerrit-PatchSet: 12 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 28 Nov 2022 23:24:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-MessageType: comment

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[L] Change in coreboot[master]: mb/amd/birman/gpio: Configure birman GPIOs
by Felix Held (Code Review) 29 Nov '22

29 Nov '22

Attention is currently required from: Jason Glenesk, Fred Reitberger. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69411 ) Change subject: mb/amd/birman/gpio: Configure birman GPIOs ...................................................................... Patch Set 4: Code-Review+1 (2 comments) File src/mainboard/amd/birman/gpio.c: https://review.coreboot.org/c/coreboot/+/69411/comment/feaf9d8f_4aeecad3 PS2, Line 31: PAD_SCI(GPIO_9, PULL_UP, EDGE_LOW), > I'm not 100% sure here either. […] hm, i'd change this to GPI and maybe leave a comment that it's unclear if that needs to generate SCIs. not getting SCIs when expecting to get SCIs is probably a slightly better failure case then getting spurious SCIs File src/mainboard/amd/birman/gpio.c: https://review.coreboot.org/c/coreboot/+/69411/comment/88b6b26b_1ae96ae0 PS4, Line 19: PAD_NF_SCI(GPIO_3, GPIOxx, PULL_NONE, EDGE_LOW), i'd use PAD_SCI(GPIO_3, PULL_NONE, EDGE_LOW) here; the PAD_NF_SCI macro is only needed when the gpio mux setting is != GPIOxx. for gpio2 above the PAD_NF_SCI is needed, since the gpio mux needs to ne WAKE_L there, but this isn't the case here -- To view, visit https://review.coreboot.org/c/coreboot/+/69411 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5459efb38431e568e25405c440b5b9cf1354f02f Gerrit-Change-Number: 69411 Gerrit-PatchSet: 4 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Mon, 28 Nov 2022 22:50:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Fred Reitberger <reitbergerfred(a)gmail.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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[L] Change in coreboot[master]: device/xhci: Refactor functions to work with a non-const device tree
by build bot (Jenkins) (Code Review) 28 Nov '22

28 Nov '22

Attention is currently required from: Raul Rangel, Martin Roth, Karthik Ramasubramanian. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69914 ) Change subject: device/xhci: Refactor functions to work with a non-const device tree ...................................................................... Patch Set 4: Verified+1 (2 comments) File src/device/xhci_const.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164703): https://review.coreboot.org/c/coreboot/+/69914/comment/b57cdf8c_c980ffcd PS4, Line 18: enum cb_err xhci_resource_for_each_ext_cap(const struct resource *res, void *context, that open brace { should be on the previous line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164703): https://review.coreboot.org/c/coreboot/+/69914/comment/6ce4934a_c68bfaad PS4, Line 95: enum cb_err xhci_resource_for_each_supported_usb_cap( that open brace { should be on the previous line -- To view, visit https://review.coreboot.org/c/coreboot/+/69914 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If5a74f9529d5dc6031ec968ef5f40a9cad5ffbc4 Gerrit-Change-Number: 69914 Gerrit-PatchSet: 4 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 28 Nov 2022 20:45:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/cezanne: Update XHCI GPE to use constant
by Robert Zieba (Code Review) 28 Nov '22

28 Nov '22

Attention is currently required from: Robert Zieba, Jason Glenesk, Raul Rangel, Fred Reitberger, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Matt DeVillier, Angel Pons, Fred Reitberger, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69917 to look at the new patch set (#5). Change subject: soc/amd/cezanne: Update XHCI GPE to use constant ...................................................................... soc/amd/cezanne: Update XHCI GPE to use constant The GPE number used for XHCI has now been defined in AMD's common code in CB:67936. Change over existing code to use this new definition. BRANCH=guybrush BUG=b:186792595 TEST=Ran on nipperkin device and verified that XHCI events string use GPE 31. Signed-off-by: Robert Zieba <robertzieba(a)google.com> Change-Id: I9c2a44f7d2eb47422ae8c585e5e01ea0b420d461 --- M src/soc/amd/cezanne/xhci.c 1 file changed, 21 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/69917/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/69917 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c2a44f7d2eb47422ae8c585e5e01ea0b420d461 Gerrit-Change-Number: 69917 Gerrit-PatchSet: 5 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Robert Zieba <robertzieba(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/amd/mendocino: Update XHCI GPE to use constant
by Robert Zieba (Code Review) 28 Nov '22

28 Nov '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Paul Menzel, Fred Reitberger, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69916 to look at the new patch set (#5). Change subject: soc/amd/mendocino: Update XHCI GPE to use constant ...................................................................... soc/amd/mendocino: Update XHCI GPE to use constant The GPE number used for XHCI has now been defined in AMD's common code in CB:67936. Change over existing code to use this new definition. BUG=b:186792595 TEST=Ran on skyrim device and verified XHCI GPE setting. Signed-off-by: Robert Zieba <robertzieba(a)google.com> Change-Id: I3bfc2256ea2ca851afe88f2cdb419f39eee76fdd --- M src/soc/amd/mendocino/xhci.c 1 file changed, 20 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/69916/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/69916 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3bfc2256ea2ca851afe88f2cdb419f39eee76fdd Gerrit-Change-Number: 69916 Gerrit-PatchSet: 5 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: soc/amd/common/xhci: Add support for logging XHCI wake events
by Robert Zieba (Code Review) 28 Nov '22

28 Nov '22

Attention is currently required from: Robert Zieba, Jason Glenesk, Raul Rangel, Matt DeVillier, Martin Roth, Fred Reitberger, Karthik Ramasubramanian, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, Karthik Ramasubramanian, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/67936 to look at the new patch set (#11). Change subject: soc/amd/common/xhci: Add support for logging XHCI wake events ...................................................................... soc/amd/common/xhci: Add support for logging XHCI wake events AMD SoCs currently only log the GPE# when an XHCI controller wakes the system. Add code to log XHCI wake events to the elog. BRANCH=guybrush BUG=b:186792595 TEST=builds Change-Id: Ic0489e1df55c4e63cb8a306099e3f31c82eebd58 Signed-off-by: Robert Zieba <robertzieba(a)google.com> --- M src/soc/amd/common/block/acpi/elog.c A src/soc/amd/common/block/include/amdblocks/xhci.h A src/soc/amd/common/block/xhci/Kconfig A src/soc/amd/common/block/xhci/Makefile.inc A src/soc/amd/common/block/xhci/elog.c A src/soc/amd/common/block/xhci/xhci.c 6 files changed, 201 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/67936/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/67936 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic0489e1df55c4e63cb8a306099e3f31c82eebd58 Gerrit-Change-Number: 67936 Gerrit-PatchSet: 11 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Robert Zieba <robertzieba(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mb/system76/adl-p: Disable SATA DevSlp
by Tim Crawford (Code Review) 28 Nov '22

28 Nov '22

Tim Crawford has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/70100 ) Change subject: mb/system76/adl-p: Disable SATA DevSlp ...................................................................... mb/system76/adl-p: Disable SATA DevSlp After changing EC detection of S0ix from CPU_C10_GATE# to SLP_S0# in system76/ec@cc3effb6a451 ("board/system76/common: use SLP_S0# pin for modern standby detection"), DevSlp blocks suspend entry. Disable it until it is fixed. Change-Id: I586245ebf9f9d5ad08f6745a450411f194a661da Signed-off-by: Tim Crawford <tcrawford(a)system76.com> --- M src/mainboard/system76/adl-p/devicetree.cb 1 file changed, 17 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/70100/1 diff --git a/src/mainboard/system76/adl-p/devicetree.cb b/src/mainboard/system76/adl-p/devicetree.cb index 6a9f362..c7085b4 100644 --- a/src/mainboard/system76/adl-p/devicetree.cb +++ b/src/mainboard/system76/adl-p/devicetree.cb @@ -73,7 +73,8 @@ device ref sata on register "sata_salp_support" = "1" register "sata_ports_enable[1]" = "1" # SSD1 - register "sata_ports_dev_slp[1]" = "1" # GPP_H12 (SATA1_DEVSLP1) + # FIXME: DevSlp breaks S0ix + #register "sata_ports_dev_slp[1]" = "1" # GPP_H12 (SATA1_DEVSLP1) end device ref pch_espi on register "gen1_dec" = "0x00040069" # EC PM channel -- To view, visit https://review.coreboot.org/c/coreboot/+/70100 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I586245ebf9f9d5ad08f6745a450411f194a661da Gerrit-Change-Number: 70100 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-MessageType: newchange

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[L] Change in coreboot[master]: mb/system76/cml-u: Convert lemp9 to a variant
by Tim Crawford (Code Review) 28 Nov '22

28 Nov '22

Attention is currently required from: Jeremy Soller. Tim Crawford has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64528 ) Change subject: mb/system76/cml-u: Convert lemp9 to a variant ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/64528 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I13777cf6f663ca8c52a059a60cfcdfe6ecc5b9ae Gerrit-Change-Number: 64528 Gerrit-PatchSet: 4 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Comment-Date: Mon, 28 Nov 2022 20:12:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/dedede/variants/sasukette: Disable PCIE RP8 and CLKSRC4
by Henry Sun (Code Review) 28 Nov '22

28 Nov '22

Attention is currently required from: Rui Zhou, Maulik Vaghela, Aamir Bohra. Henry Sun has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69848 ) Change subject: mb/google/dedede/variants/sasukette: Disable PCIE RP8 and CLKSRC4 ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Patchset: PS1: Wait for Aamir or Maulik to provide CR+2. Thanks! -- To view, visit https://review.coreboot.org/c/coreboot/+/69848 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I61bcefa128d4f39613a760b647048f9e19e262c2 Gerrit-Change-Number: 69848 Gerrit-PatchSet: 1 Gerrit-Owner: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Aamir Bohra <aamirbohra(a)google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Maulik Vaghela <maulikvaghela(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: zanxi chen <chenzanxi(a)huaqin.corp-partner.google.com> Gerrit-Attention: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Attention: Maulik Vaghela <maulikvaghela(a)google.com> Gerrit-Attention: Aamir Bohra <aamirbohra(a)google.com> Gerrit-Comment-Date: Mon, 28 Nov 2022 20:04:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit November 2022