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Change subject: soc/intel/meteorlake: Use index 0 instead of 0x10 for P2SB
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161771):
https://review.coreboot.org/c/coreboot/+/69041/comment/abc1dedc_d5980b01
PS1, Line 6:
Possible long commit subject (prefer a maximum 65 characters)
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Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69041 )
Change subject: soc/intel/meteorlake: Use index 0 instead of 0x10 for P2SB
......................................................................
soc/intel/meteorlake: Use index 0 instead of 0x10 for P2SB
This patch uses index 0 for P2SB memory resource allocation instead
of 0x10.
TEST=Able to build and boot Google/Rex and observed log as below.
Without the code change:
[SPEW ] Â Â PCI: 00:1f.1 resource base e0000000 size 1000000 align 0
gran 0 limit 0 flags f0000200 index 10
With the code change:
[SPEW ] Â Â PCI: 00:1f.1 resource base e0000000 size 1000000 align 0
gran 0 limit 0 flags f0000200 index 0
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: I44caac73e245f536f3a22baafa1a6a0370e1dd37
---
M src/soc/intel/meteorlake/p2sb.c
1 file changed, 26 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/69041/1
diff --git a/src/soc/intel/meteorlake/p2sb.c b/src/soc/intel/meteorlake/p2sb.c
index d700c70..72f7260 100644
--- a/src/soc/intel/meteorlake/p2sb.c
+++ b/src/soc/intel/meteorlake/p2sb.c
@@ -46,7 +46,7 @@
* The following code makes sure that it doesn't change even the
* resource allocator is being run.
*/
- mmio_range(dev, PCI_BASE_ADDRESS_0, P2SB_BAR, P2SB_SIZE);
+ mmio_range(dev, 0, P2SB_BAR, P2SB_SIZE);
}
struct device_operations ioe_p2sb_ops = {
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Change subject: soc/qualcomm/sc7280: Add socinfo_pro_part() function in coreboot
......................................................................
Patch Set 7:
(4 comments)
File src/soc/qualcomm/sc7280/socinfo.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161766):
https://review.coreboot.org/c/coreboot/+/68384/comment/ea040d91_4f601e7b
PS7, Line 50: for(i = 0; i < ARRAY_SIZE(chipinfolut); i++)
space required before the open parenthesis '('
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161766):
https://review.coreboot.org/c/coreboot/+/68384/comment/572f7f07_6c0c7115
PS7, Line 51: if(chipinfolut[i].jtagid == jtagid)
space required before the open parenthesis '('
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161766):
https://review.coreboot.org/c/coreboot/+/68384/comment/30056f74_3fe8be9f
PS7, Line 65: if(ret != -1)
space required before the open parenthesis '('
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161766):
https://review.coreboot.org/c/coreboot/+/68384/comment/bd5df736_1e3a6c15
PS7, Line 79: if(ret != -1)
space required before the open parenthesis '('
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Venkat Thogaru has uploaded a new patch set (#7) to the change originally created by Sudheer Amrabadi. ( https://review.coreboot.org/c/coreboot/+/68384 )
Change subject: soc/qualcomm/sc7280: Add socinfo_pro_part() function in coreboot
......................................................................
soc/qualcomm/sc7280: Add socinfo_pro_part() function in
coreboot
The API socinfo_pro_part is added to help to differentiate
between PRO and NON_PRO SKUs. Returns 1 for Pro
and 0 for NON_PRO SKUs.
BUG=b:248187555
TEST=Validate boards are detected correctly on PRO
and NO248187555N_PRO SKUs
Signed-off-by: Taniya Das <quic_tdas(a)quicinc.com>
Change-Id: Id9f23696384a6c1a89000292eafebd8a16c273ca
---
M src/soc/qualcomm/sc7280/include/soc/socinfo.h
M src/soc/qualcomm/sc7280/socinfo.c
2 files changed, 91 insertions(+), 34 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/68384/7
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Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68474 )
Change subject: util/inteltool: Add support for Elkhart lake
......................................................................
Patch Set 6:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/68474/comment/9da49e23_0effcfcb
PS1, Line 10:
> Added that information to the message.
It is not there. Have you pushed the changes?
File util/inteltool/gpio_names/elkhartlake.h:
https://review.coreboot.org/c/coreboot/+/68474/comment/2159fd18_5ccc7cd9
PS1, Line 150: "GP_DSW07","n/a",
> This made me wonder while making this file since there is no `GP_DSW06` in `614109`, but it is defin […]
Let's make it RSVD
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Jakub Czapiga has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/66909 )
Change subject: vboot: Add VBOOT_CBFS_INTEGRATION support
......................................................................
Patch Set 18:
(1 comment)
File src/security/vboot/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/66909/comment/4954d88c_be0e3d07
PS15, Line 104: bootblock-y += secdata_mock.c
> I changed the code as You suggested. […]
I built firmware with this change, but with CBFS_VERIFICATION=y and VBOOT_CBFS_INTEGRATION=n. That's the log:
```
[NOTE ] coreboot-coreboot-unknown.9999.a24b0c3 Mon Oct 31 10:27:52 UTC 2022 romstage starting (log level: 8)...
[INFO ] Waited 1553us to clear limit power flag.
[EMERG] TPM writeback in romstage?
```
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