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Change subject: mb/google/rex: Add fingerprint SPI
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Patch Set 14:
(1 comment)
File src/mainboard/google/rex/variants/rex0/gpio.c:
https://review.coreboot.org/c/coreboot/+/66992/comment/f2faca06_256c6784
PS14, Line 387: PAD_CFG_GPO(GPP_B11, 1, DEEP),
> Why just power off PWR here then you can remove the romstage?
This was a copy paste over from Brya where we couldn't change bootblock anymore? This isn't directly applicable to Rex as we still have the opportunity to update bootblock.
We should be leaving EN_FP_PWR=0 and FP_RST_ODL=0 in coreboot and allowing the ACPI to pass for the Kernel to handle it. I'd set these both in ramstage and don't touch them in other parts.
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Change subject: soc/intel/meteorlake: Implement SOC Die lock down configuration
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Patch Set 2: Code-Review+1
(1 comment)
Patchset:
PS2:
I have observed some instability after I cherrypicking this CL.
need some help from others to ensure this CL is good.
I know this CL is required as same changes are working for Brya.
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