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Change subject: mb/google/rex: Disable TBT PCIe rp1 and rp3 root ports
......................................................................
Patch Set 4:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/68854/comment/370aa3b2_048903d1
PS3, Line 9: Extra memory resource allocation is needed for bridge once a TBT PCIe
> > We should change the comment and test filed to fit the purpose. […]
Done
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Change subject: mb/google/rex: Disable TBT PCIe rp1 and rp3 root ports
......................................................................
mb/google/rex: Disable TBT PCIe rp1 and rp3 root ports
Rex board only uses TBT PCIe root ports 0 and 2. This change disables
rp1 and rp3 root ports.
BUG=b:254207628
TEST=Booted to OS and verified rp1 and rp3 root ports were disabled.
Change-Id: Ia5c1d657c0ad0482619d739f8949bc9168eac25b
Signed-off-by: zhaojohn <john.zhao(a)intel.com>
---
M src/mainboard/google/rex/variants/rex0/overridetree.cb
1 file changed, 16 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/68854/4
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Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68917 )
Change subject: mb/google/brya/variants/volmar: Add firmware config field for FP_MCU
......................................................................
Patch Set 2:
(1 comment)
File src/mainboard/google/brya/variants/volmar/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/68917/comment/42eea612_f5460690
PS2, Line 23: option FPMCU_ENABLED 0
Is there a reason these are backwards from all the others? It makes more sense for 0 to be disabled and for 1 to be enabled, like the others in this file.
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I'd like you to reexamine a change. Please visit
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Change subject: soc: Use a more qualified path for "../../chip.h"
......................................................................
soc: Use a more qualified path for "../../chip.h"
Also, sort includes.
Change-Id: I3e73e3599e65b82b70c33947683198778c1b3491
Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr>
---
M src/soc/intel/alderlake/include/soc/soc_chip.h
M src/soc/intel/apollolake/include/soc/soc_chip.h
M src/soc/intel/baytrail/romstage/pmc.c
M src/soc/intel/braswell/include/soc/ramstage.h
M src/soc/intel/braswell/romstage/romstage.c
M src/soc/intel/cannonlake/include/soc/ramstage.h
M src/soc/intel/cannonlake/include/soc/soc_chip.h
M src/soc/intel/cannonlake/romstage/fsp_params.c
M src/soc/intel/cannonlake/romstage/romstage.c
M src/soc/intel/denverton_ns/include/soc/soc_chip.h
M src/soc/intel/elkhartlake/include/soc/soc_chip.h
M src/soc/intel/icelake/include/soc/soc_chip.h
M src/soc/intel/jasperlake/include/soc/soc_chip.h
M src/soc/intel/meteorlake/include/soc/soc_chip.h
M src/soc/intel/quark/include/soc/ramstage.h
M src/soc/intel/quark/romstage/fsp_params.c
M src/soc/intel/skylake/bootblock/pch.c
M src/soc/intel/skylake/include/soc/ramstage.h
M src/soc/intel/skylake/include/soc/soc_chip.h
M src/soc/intel/tigerlake/include/soc/soc_chip.h
M src/soc/intel/xeon_sp/include/soc/soc_chip.h
M src/soc/mediatek/mt8195/include/soc/soc_chip.h
M src/soc/nvidia/tegra210/jdi_25x18_display/panel-jdi-lpm102a188a.c
23 files changed, 50 insertions(+), 44 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/69061/2
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Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69061 )
Change subject: soc: Use a more qualified path for "../../chip.h"
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
Thank you.
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Hello Frank Wu, build bot (Jenkins), Raul Rangel, Jason Nien, Martin Roth,
I'd like you to reexamine a change. Please visit
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Change subject: mb/google/skyrim: Use detect vs probed flag for touchscreens
......................................................................
mb/google/skyrim: Use detect vs probed flag for touchscreens
Now that coreboot performs the necessary power sequencing, switch
from using the 'probed' flag to 'detect' for all I2C touchscreens.
This alleviates ChromeOS from having to probe to see which
touchscreen model is actually present, prevents breaking ACPI spec
by generating device entries with status 'enabled and present'
which aren't actually present, and improves compatibility with
upstream Linux and Windows.
BUG=b:121309055
TEST=build/boot ChromeOS and Linux on skyrim, ensure touchscreen is
functional, and ACPI device entry generated for correct touchscreen
model.
Change-Id: Id9e3089decf0f94a1358929684ce248e52cbe41f
Signed-off-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com>
---
M src/mainboard/google/skyrim/variants/frostflow/overridetree.cb
M src/mainboard/google/skyrim/variants/skyrim/overridetree.cb
M src/mainboard/google/skyrim/variants/winterhold/overridetree.cb
3 files changed, 28 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/67779/6
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Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68929 )
Change subject: crossgcc: Upgrade IASL from 20220331 to 20221020
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
https://review.coreboot.org/c/coreboot/+/68936 is needed before current patch.
Thank you.
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Change subject: mb/google/brya : Set EPP value for Vell board
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/68900/comment/80d27609_1a2a2ab6
PS3, Line 11: TEST=Verified code build for Vell board
> do we have any specific test case that reflects the need to set the particular EPP value?
Please refer b:215526166 for details.
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Attention is currently required from: Shelley Chen, Taniya Das, Venkat Thogaru, Sudheer Amrabadi.
Venkat Thogaru has uploaded a new patch set (#8) to the change originally created by Sudheer Amrabadi. ( https://review.coreboot.org/c/coreboot/+/68384 )
Change subject: soc/qualcomm/sc7280: Add socinfo_pro_part() function in coreboot
......................................................................
soc/qualcomm/sc7280: Add socinfo_pro_part() function in
coreboot
The API socinfo_pro_part is added to help to differentiate
between PRO and NON_PRO SKUs. Returns 1 for Pro
and 0 for NON_PRO SKUs.
BUG=b:248187555
TEST=Validate boards are detected correctly on PRO
and NO248187555N_PRO SKUs
Signed-off-by: Taniya Das <quic_tdas(a)quicinc.com>
Change-Id: Id9f23696384a6c1a89000292eafebd8a16c273ca
---
M src/soc/qualcomm/sc7280/include/soc/socinfo.h
M src/soc/qualcomm/sc7280/socinfo.c
2 files changed, 90 insertions(+), 33 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/68384/8
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