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Change subject: mb/google/brya: enable PCIe RP12 for lisbon eMMC support
......................................................................
Patch Set 3: Code-Review+1
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Change subject: mb/google/brya/var/lisbon: Include driver for GL9763E for eMMC boot disk
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Patch Set 1: Code-Review+1
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Change subject: mb/google/brya/var/lisbon: Enable SaGv
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Patch Set 1: Code-Review+1
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Change subject: common/acpi/dptc: Dynamic Thermal Table Switching Proposal
......................................................................
Patch Set 14:
(6 comments)
File src/soc/amd/common/acpi/dptc.asl:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161749):
https://review.coreboot.org/c/coreboot/+/68471/comment/b9cbafc2_7872b7fd
PS14, Line 47: If(LGreaterEqual(\_SB.PCI0.LPCB.EC0.TIN4, 0x7B) ||
trailing whitespace
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https://review.coreboot.org/c/coreboot/+/68471/comment/5bf29579_00f7bfa8
PS14, Line 54:
trailing whitespace
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161749):
https://review.coreboot.org/c/coreboot/+/68471/comment/35257025_0c2c9a06
PS14, Line 56: If(LLessEqual(\_SB.PCI0.LPCB.EC0.TIN4, 0x76)||
trailing whitespace
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161749):
https://review.coreboot.org/c/coreboot/+/68471/comment/39fb3eb4_f97674d5
PS14, Line 71: }
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trailing whitespace
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https://review.coreboot.org/c/coreboot/+/68471/comment/d7df1e61_d3b25d26
PS14, Line 91: If(LLessEqual(\_SB.PCI0.LPCB.EC0.TIN4, 0x71)||
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I'd like you to reexamine a change. Please visit
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Change subject: common/acpi/dptc: Dynamic Thermal Table Switching Proposal
......................................................................
common/acpi/dptc: Dynamic Thermal Table Switching Proposal
Thermal table switches to different modes to meet 6
user experience.
BRANCH=none
BUG=b:232946420
TEST=emerge-skyrim coreboot
Signed-off-by: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com>
Change-Id: I866e5e497e2936984e713029b5f0b6d54cbc9622
---
M src/ec/google/chromeec/acpi/ec.asl
M src/soc/amd/common/acpi/dptc.asl
2 files changed, 95 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/68471/14
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Change subject: soc/amd/acpi: Expand 5 DPTC thermal profiles acpigen support for Alib
......................................................................
soc/amd/acpi: Expand 5 DPTC thermal profiles acpigen support for Alib
Update acpigen_write_alib_dptc() to support extra 5 thermal profiles.
User can use these profiles for dynamic thermal table switching support.
BUG=b:232946420
TEST=emerge-skyrim coreboot
Signed-off-by: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com>
Change-Id: I9e6d5c0fc6f492340c935899920d9ee7c9396256
---
M src/soc/amd/common/block/acpi/alib.c
M src/soc/amd/common/block/include/amdblocks/alib.h
2 files changed, 172 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/68470/17
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Kangheui Won has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68953 )
Change subject: security/vboot: Update build rules using x86 SHA extension
......................................................................
Patch Set 1:
(1 comment)
File src/security/vboot/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/68953/comment/db5f4a22_a6be9416
PS1, Line 26: ifeq ($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),y)
> Actually, the help text of `VBOOT_X86_SHA256_ACCELERATION` says `Use sha extension for sha256 hash c […]
With CBFS verification all stages may use the vboot verification functions. The main intention here is to enable `VBOOT_X86_SHA256_ACCELERATION` for other stages but disable it in verstage since psp-verstage runs on ARM PSP.
I don't know much about Kconfig so not sure if we can select different options for different stages, but AMD platforms should able to select `VBOOT_X86_SHA256_ACCELERATION` for other stages but disable it for psp-verstage.
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I'd like you to reexamine a change. Please visit
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Change subject: soc/amd/mendocino: Enhance DPTC_INPUT to support 13 DPTC thermal parameters
......................................................................
soc/amd/mendocino: Enhance DPTC_INPUT to support 13 DPTC thermal parameters
Expand DPTC_INPUT macro to supoort 13 DPTC thermal table parameters for
dynamic table switching support.
BRANCH=none
BUG=b:232946420
TEST=emerge-skyrim coreboot
Signed-off-by: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com>
Change-Id: I6d6a00f0eca0b0941860b9bc75da41d7a10d60e8
---
M src/soc/amd/mendocino/root_complex.c
1 file changed, 211 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/68649/12
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