coreboot-gerrit October 2022

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: mb/google/brya: enable PCIe RP12 for lisbon eMMC support
by Ricky Chang (Code Review) 31 Oct '22

31 Oct '22

Attention is currently required from: Kevin Chiu, Nick Vaccaro. Ricky Chang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68167 ) Change subject: mb/google/brya: enable PCIe RP12 for lisbon eMMC support ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/68167 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ief8ca9cf845156ac761556d0eb49edb65894c001 Gerrit-Change-Number: 68167 Gerrit-PatchSet: 3 Gerrit-Owner: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Ricky Chang <rickytlchang(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Mon, 31 Oct 2022 09:10:53 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/brya/var/lisbon: Include driver for GL9763E for eMMC boot disk
by Ricky Chang (Code Review) 31 Oct '22

31 Oct '22

Attention is currently required from: Kevin Chiu, Nick Vaccaro. Ricky Chang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68888 ) Change subject: mb/google/brya/var/lisbon: Include driver for GL9763E for eMMC boot disk ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/68888 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe579a913225b5241412bbb1b8ea995a5102a3bb Gerrit-Change-Number: 68888 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Ricky Chang <rickytlchang(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Mon, 31 Oct 2022 09:08:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[master]: drivers/ipmi/ocp: add PCIe SEL support
by Shuming Chu (Shuming) (Code Review) 31 Oct '22

31 Oct '22

Attention is currently required from: Jonathan Zhang, Rocky Phagura, Paul Menzel, Angel Pons, Tim Chu. Shuming Chu (Shuming) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68758 ) Change subject: drivers/ipmi/ocp: add PCIe SEL support ...................................................................... Patch Set 6: (1 comment) File src/drivers/ipmi/ocp/ipmi_ocp.h: https://review.coreboot.org/c/coreboot/+/68758/comment/b4857aca_01133ed8 PS3, Line 111: /* PCIE CE */ : #define RECEIVER_ERROR 0x00 : #define BAD_TLP 0x01 : #define BAD_DLLP 0x02 : #define REPLAY_TIME_OUT 0x03 : #define REPLAY_NUMBER_ROLLOVER 0x04 : #define ADVISORY_NONFATAL_ERROR_STATUS 0x05 : #define CORRECTED_INTERNAL_ERROR_STATUS 0x06 : #define HEADER_LOG_OVERFLOW_STATUS 0x07 : : /* PCIE UCE */ : #define PCI_EXPRESS_DATA_LINK_PROTOCOL_ERROR 0x20 : #define SURPRISE_DOWN_ERROR 0x21 : #define RECEIVED_PCI_EXPRESS_POISONED_TLP 0x22 : #define PCI_EXPRESS_FLOW_CONTROL_PROTOCOL_ERROR 0x23 : #define COMPLETION_TIMEOUT_ON_NP_TRANSACTIONS_OUTSTANDING_ON_PCI_EXPRESS_DMI 0x24 : #define RECEIVED_A_REQUEST_FROM_A_DOWNSTREAM_COMPONENT_THAT_IS_TO_BE_COMPLETER_ABORTED 0x25 : #define RECEIVED_PCI_EXPRESS_UNEXPECTED_COMPLETION 0x26 : #define PCI_EXPRESS_RECEIVER_OVERFLOW 0x27 : #define PCI_EXPRESS_MALFORMED_TLP 0x28 : #define ECRC_ERROR_STATUS 0x29 : #define RECEIVED_A_REQUEST_FROM_A_DOWNSTREAM_COMPONENT_THAT_IS_UNSUPPORTED 0x2A : #define ACS_VIOLATION 0x2B : #define UNCORRECTABLE_INTERNAL_ERROR_STATUS 0x2C : #define MC_BLOCKED_TLP 0x2D : #define ATOMICOP_EGRESS_BLOCKED_STATUS 0x2E : #define TLP_PREFIX_BLOCKED_ERROR_STATUS 0x2F : #define POISONED_TLP_EGRESS_BLOCKED 0x30 > I do not think they are part of the PCIe spec. […] As Jonathan mentioned, these macros are used for SEL (in Error ID field). They are different from PCIe error status registers. -- To view, visit https://review.coreboot.org/c/coreboot/+/68758 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1ee46c8da7dbccbe1e2cc00bfe62e5df2f072d65 Gerrit-Change-Number: 68758 Gerrit-PatchSet: 6 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Rocky Phagura <rphagura(a)fb.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Rocky Phagura <rphagura(a)fb.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 31 Oct 2022 09:06:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jonathan Zhang <jonzhang(a)fb.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/brya/var/lisbon: Enable SaGv
by Ricky Chang (Code Review) 31 Oct '22

31 Oct '22

Attention is currently required from: Kevin Chiu, Tarun Tuli, Nick Vaccaro. Ricky Chang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69013 ) Change subject: mb/google/brya/var/lisbon: Enable SaGv ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/69013 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic7d3203bfe06973b023a38d1aa3d69cce5c3a60c Gerrit-Change-Number: 69013 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Ricky Chang <rickytlchang(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Mon, 31 Oct 2022 09:03:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: common/acpi/dptc: Dynamic Thermal Table Switching Proposal
by build bot (Jenkins) (Code Review) 31 Oct '22

31 Oct '22

Attention is currently required from: Jason Glenesk, Matt DeVillier, Caveh Jalali, Tim Wawrzynczak, Eric Peers, Fred Reitberger, Karthikeyan Ramasubramanian, Boris Mittelberg, Felix Held. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68471 ) Change subject: common/acpi/dptc: Dynamic Thermal Table Switching Proposal ...................................................................... Patch Set 14: (6 comments) File src/soc/amd/common/acpi/dptc.asl: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161749): https://review.coreboot.org/c/coreboot/+/68471/comment/b9cbafc2_7872b7fd PS14, Line 47: If(LGreaterEqual(\_SB.PCI0.LPCB.EC0.TIN4, 0x7B) || trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161749): https://review.coreboot.org/c/coreboot/+/68471/comment/5bf29579_00f7bfa8 PS14, Line 54: trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161749): https://review.coreboot.org/c/coreboot/+/68471/comment/35257025_0c2c9a06 PS14, Line 56: If(LLessEqual(\_SB.PCI0.LPCB.EC0.TIN4, 0x76)|| trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161749): https://review.coreboot.org/c/coreboot/+/68471/comment/39fb3eb4_f97674d5 PS14, Line 71: } trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161749): https://review.coreboot.org/c/coreboot/+/68471/comment/ceab1e86_bd777714 PS14, Line 73: If(LLessEqual(\_SB.PCI0.LPCB.EC0.TIN4, 0x7B)|| trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161749): https://review.coreboot.org/c/coreboot/+/68471/comment/d7df1e61_d3b25d26 PS14, Line 91: If(LLessEqual(\_SB.PCI0.LPCB.EC0.TIN4, 0x71)|| trailing whitespace -- To view, visit https://review.coreboot.org/c/coreboot/+/68471 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I866e5e497e2936984e713029b5f0b6d54cbc9622 Gerrit-Change-Number: 68471 Gerrit-PatchSet: 14 Gerrit-Owner: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Eric Peers <epeers(a)google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 31 Oct 2022 09:03:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: common/acpi/dptc: Dynamic Thermal Table Switching Proposal
by EricKY Cheng (Code Review) 31 Oct '22

31 Oct '22

Attention is currently required from: Jason Glenesk, EricKY Cheng, Matt DeVillier, Tim Wawrzynczak, Eric Peers, Fred Reitberger, Karthikeyan Ramasubramanian, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Matt DeVillier, Tim Wawrzynczak, Eric Peers, Tim Van Patten, Fred Reitberger, Karthikeyan Ramasubramanian, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68471 to look at the new patch set (#14). Change subject: common/acpi/dptc: Dynamic Thermal Table Switching Proposal ...................................................................... common/acpi/dptc: Dynamic Thermal Table Switching Proposal Thermal table switches to different modes to meet 6 user experience. BRANCH=none BUG=b:232946420 TEST=emerge-skyrim coreboot Signed-off-by: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Change-Id: I866e5e497e2936984e713029b5f0b6d54cbc9622 --- M src/ec/google/chromeec/acpi/ec.asl M src/soc/amd/common/acpi/dptc.asl 2 files changed, 95 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/68471/14 -- To view, visit https://review.coreboot.org/c/coreboot/+/68471 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I866e5e497e2936984e713029b5f0b6d54cbc9622 Gerrit-Change-Number: 68471 Gerrit-PatchSet: 14 Gerrit-Owner: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Eric Peers <epeers(a)google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mb/google/skyrim/var/winterhold: Enable Dynamic DPTC config
by EricKY Cheng (Code Review) 31 Oct '22

31 Oct '22

Attention is currently required from: Jason Nien, Martin Roth. EricKY Cheng has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69024 ) Change subject: mb/google/skyrim/var/winterhold: Enable Dynamic DPTC config ...................................................................... mb/google/skyrim/var/winterhold: Enable Dynamic DPTC config Enable Dynamic DPTC support. Signed-off-by: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Change-Id: I957511c44278a7cffb7cb5d7e099eb13232b6a1a --- M src/mainboard/google/skyrim/Kconfig.name 1 file changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/69024/1 diff --git a/src/mainboard/google/skyrim/Kconfig.name b/src/mainboard/google/skyrim/Kconfig.name index f7f8d7c..d9008e8 100644 --- a/src/mainboard/google/skyrim/Kconfig.name +++ b/src/mainboard/google/skyrim/Kconfig.name @@ -9,6 +9,7 @@ bool "-> Winterhold" select BOARD_GOOGLE_BASEBOARD_SKYRIM select SOC_AMD_COMMON_BLOCK_ACPI_DPTC + select FEATURE_DYNAMIC_DPTC config BOARD_GOOGLE_MORTHAL bool "-> Morthal" -- To view, visit https://review.coreboot.org/c/coreboot/+/69024 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I957511c44278a7cffb7cb5d7e099eb13232b6a1a Gerrit-Change-Number: 69024 Gerrit-PatchSet: 1 Gerrit-Owner: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: soc/amd/acpi: Expand 5 DPTC thermal profiles acpigen support for Alib
by EricKY Cheng (Code Review) 31 Oct '22

31 Oct '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Nelson Ye, Tim Van Patten, Eric Peers, Fred Reitberger, Karthikeyan Ramasubramanian, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Matt DeVillier, Chris Wang, Tim Van Patten, Eric Peers, Fred Reitberger, Karthikeyan Ramasubramanian, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68470 to look at the new patch set (#17). Change subject: soc/amd/acpi: Expand 5 DPTC thermal profiles acpigen support for Alib ...................................................................... soc/amd/acpi: Expand 5 DPTC thermal profiles acpigen support for Alib Update acpigen_write_alib_dptc() to support extra 5 thermal profiles. User can use these profiles for dynamic thermal table switching support. BUG=b:232946420 TEST=emerge-skyrim coreboot Signed-off-by: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Change-Id: I9e6d5c0fc6f492340c935899920d9ee7c9396256 --- M src/soc/amd/common/block/acpi/alib.c M src/soc/amd/common/block/include/amdblocks/alib.h 2 files changed, 172 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/68470/17 -- To view, visit https://review.coreboot.org/c/coreboot/+/68470 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9e6d5c0fc6f492340c935899920d9ee7c9396256 Gerrit-Change-Number: 68470 Gerrit-PatchSet: 17 Gerrit-Owner: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nelson Ye <nelson_ye(a)compal.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Nelson Ye <nelson_ye(a)compal.corp-partner.google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Eric Peers <epeers(a)google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: security/vboot: Update build rules using x86 SHA extension
by Kangheui Won (Code Review) 31 Oct '22

31 Oct '22

Attention is currently required from: Raul Rangel, Julius Werner, Yu-Ping Wu, Karthik Ramasubramanian. Kangheui Won has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68953 ) Change subject: security/vboot: Update build rules using x86 SHA extension ...................................................................... Patch Set 1: (1 comment) File src/security/vboot/Makefile.inc: https://review.coreboot.org/c/coreboot/+/68953/comment/db5f4a22_a6be9416 PS1, Line 26: ifeq ($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),y) > Actually, the help text of `VBOOT_X86_SHA256_ACCELERATION` says `Use sha extension for sha256 hash c […] With CBFS verification all stages may use the vboot verification functions. The main intention here is to enable `VBOOT_X86_SHA256_ACCELERATION` for other stages but disable it in verstage since psp-verstage runs on ARM PSP. I don't know much about Kconfig so not sure if we can select different options for different stages, but AMD platforms should able to select `VBOOT_X86_SHA256_ACCELERATION` for other stages but disable it for psp-verstage. -- To view, visit https://review.coreboot.org/c/coreboot/+/68953 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4f388e963eb82990cda41d3880e66ad937334908 Gerrit-Change-Number: 68953 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 31 Oct 2022 08:46:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kangheui Won <khwon(a)chromium.org> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/amd/mendocino: Enhance DPTC_INPUT to support 13 DPTC thermal para...
by EricKY Cheng (Code Review) 31 Oct '22

31 Oct '22

Attention is currently required from: Jason Glenesk, Raul Rangel, EricKY Cheng, Matt DeVillier, Fred Reitberger, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/68649 to look at the new patch set (#12). Change subject: soc/amd/mendocino: Enhance DPTC_INPUT to support 13 DPTC thermal parameters ...................................................................... soc/amd/mendocino: Enhance DPTC_INPUT to support 13 DPTC thermal parameters Expand DPTC_INPUT macro to supoort 13 DPTC thermal table parameters for dynamic table switching support. BRANCH=none BUG=b:232946420 TEST=emerge-skyrim coreboot Signed-off-by: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Change-Id: I6d6a00f0eca0b0941860b9bc75da41d7a10d60e8 --- M src/soc/amd/mendocino/root_complex.c 1 file changed, 211 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/68649/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/68649 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6d6a00f0eca0b0941860b9bc75da41d7a10d60e8 Gerrit-Change-Number: 68649 Gerrit-PatchSet: 12 Gerrit-Owner: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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coreboot-gerrit October 2022