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Hello build bot (Jenkins), Jonathan Zhang, TangYiwei, Tim Chu,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/68910
to look at the new patch set (#4).
Change subject: drivers/ocp/dmi: Fix smbios type 11 get wrong ppin value for second socket
......................................................................
drivers/ocp/dmi: Fix smbios type 11 get wrong ppin value for second socket
The last logic cpu number not always comes from second socket, this may
cause the wrong smbios type 11 ppin value for second socket.
Add function to get logic cpu number from desired node. With this way,
can get ppin value from second socket.
TESTED=On not public yet system, can get correct ppin value for smbios
type 11.
Signed-off-by: Tim Chu <Tim.Chu(a)quantatw.com>
Change-Id: I9174522c57680a57e6e4629b4e81fd837c38d47a
---
M src/drivers/ocp/dmi/smbios.c
1 file changed, 31 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/68910/4
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Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68854 )
Change subject: mb/google/rex: Disable TBT PCIe rp1 and rp3 root ports
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/68854/comment/432925ac_1a7690fc
PS3, Line 9: Extra memory resource allocation is needed for bridge once a TBT PCIe
> We should change the comment and test filed to fit the purpose. Maybe just follow schematic to disable the unused TBT port?
I agree, the commit msg need to be rewritten alongside the TEST line.
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Change subject: mb/google/rex: Add fingerprint SPI
......................................................................
Patch Set 14:
(6 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/66992/comment/11b3dbe5_eed4e862
PS14, Line 10: CL:66915
need to add the commit sha and title
https://review.coreboot.org/c/coreboot/+/66992/comment/ea82bbde_b4d0f8d3
PS14, Line 12: TEST=None yet. Awaiting Hardware
do we have correct device now to test ?
File src/mainboard/google/rex/variants/rex0/gpio.c:
https://review.coreboot.org/c/coreboot/+/66992/comment/5b58dda2_804fde35
PS14, Line 435: A20
nit: please submit a separate CL to fix this typo
https://review.coreboot.org/c/coreboot/+/66992/comment/10743fbe_97f7dc99
PS14, Line 396: /* GPP_C23 : [] ==> FP_RST_ODL */
: PAD_CFG_GPO(GPP_C23, 0, DEEP),
line number 444, already drove this signal low. what is the point of doing the same again?
https://review.coreboot.org/c/coreboot/+/66992/comment/643eb359_50f98788
PS14, Line 439: /* GPP_B11 : [] ==> EN_FP_PWR */
: PAD_CFG_GPO(GPP_B11, 0, DEEP),
do u know the default state of this signal ?
https://review.coreboot.org/c/coreboot/+/66992/comment/7d358b9a_e85d0194
PS14, Line 443:
use tab
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Change subject: mb/google/rex: Disable TBT PCIe rp1 and rp3 root ports
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/68854/comment/d06e3d3c_2810e63c
PS3, Line 9: Extra memory resource allocation is needed for bridge once a TBT PCIe
We should change the comment and test filed to fit the purpose. Maybe just follow schematic to disable the unused TBT port?
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Change subject: soc/intel/xeon_sp: Add function to get apic id via cpu index
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Abandoned
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Change subject: soc/amd/acpi: Expand 5 DPTC thermal profiles acpigen support for Alib
......................................................................
Patch Set 14:
(1 comment)
File src/soc/amd/common/block/include/amdblocks/alib.h:
https://review.coreboot.org/c/coreboot/+/68470/comment/f2471787_2664de48
PS14, Line 28: ALIB_DPTC_STT_MIN_LIMIT_ID = 0x2E,
> Hi Tim, […]
Done
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