coreboot-gerrit October 2022

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[M] Change in coreboot[master]: Documentation: Add some more acronyms to the list
by Eric Lai (Code Review) 31 Oct '22

31 Oct '22

Attention is currently required from: Martin L Roth, Martin Roth. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67330 ) Change subject: Documentation: Add some more acronyms to the list ...................................................................... Patch Set 4: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/67330 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I417bb151afcb3e996d9a12b2274ef02f2126bc7d Gerrit-Change-Number: 67330 Gerrit-PatchSet: 4 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Mon, 31 Oct 2022 01:28:06 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/common/acpi: provide PTS/WAK hooks for ECs
by Eric Lai (Code Review) 31 Oct '22

31 Oct '22

Attention is currently required from: Felix Singer, Michał Żygowski, Tim Wawrzynczak, Michał Kopeć, Michael Niewöhner. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68788 ) Change subject: soc/intel/common/acpi: provide PTS/WAK hooks for ECs ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68788 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I687254362a896baa590959bd01ae49579ec12c94 Gerrit-Change-Number: 68788 Gerrit-PatchSet: 3 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Comment-Date: Mon, 31 Oct 2022 01:13:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/common: provide S0ix hooks in PEP for ECs
by Eric Lai (Code Review) 31 Oct '22

31 Oct '22

Attention is currently required from: Felix Singer, Michał Żygowski, Tim Wawrzynczak, Michał Kopeć, Michael Niewöhner. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68789 ) Change subject: soc/intel/common: provide S0ix hooks in PEP for ECs ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/68789/comment/1a38a69e_b06f51bb PS3, Line 7: S0ix Should be display from the comment? -- To view, visit https://review.coreboot.org/c/coreboot/+/68789 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icbfd294cdd238e63eb947c227a9cf73daca702ef Gerrit-Change-Number: 68789 Gerrit-PatchSet: 3 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Comment-Date: Mon, 31 Oct 2022 01:13:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: drivers/i2c/generic: Print error when using _CRS and PowerResource
by Eric Lai (Code Review) 31 Oct '22

31 Oct '22

Attention is currently required from: Tim Crawford, Raul Rangel, Tim Wawrzynczak, Tim Van Patten, Karthik Ramasubramanian. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60174 ) Change subject: drivers/i2c/generic: Print error when using _CRS and PowerResource ...................................................................... Patch Set 2: (1 comment) File src/drivers/i2c/generic/generic.c: https://review.coreboot.org/c/coreboot/+/60174/comment/c1d018bc_6f7b80ad PS2, Line 74: printk(BIOS_ERR, "%s: ERROR: Exposing GPIOs in Power Resource and _CRS\n", : dev_path(dev)); > Just saying that there are some tests that will grep for `ERROR`, so beware 😊 If we don't want this, why need check the flag? Just force set it in the I2C driver. -- To view, visit https://review.coreboot.org/c/coreboot/+/60174 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifcc42ed81fff295fb168a0b343e96b3a650b1c84 Gerrit-Change-Number: 60174 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 31 Oct 2022 01:05:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Tim Wawrzynczak <inforichland(a)gmail.com> Comment-In-Reply-To: Tim Van Patten <timvp(a)google.com> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: [TEST ONLY]Turn off camera and mic during S0ix
by Tony Tung (Code Review) 31 Oct '22

31 Oct '22

Attention is currently required from: Tony Tung. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69011 to look at the new patch set (#2). Change subject: [TEST ONLY]Turn off camera and mic during S0ix ...................................................................... [TEST ONLY]Turn off camera and mic during S0ix Change-Id: I42a33b6a8614ec9c7c978cd7af7d92bfed391ad8 --- A .vscode/settings.json M src/mainboard/google/brya/variants/gaelin/Makefile.inc A src/mainboard/google/brya/variants/gaelin/gpio.c M src/mainboard/google/brya/variants/gaelin/include/variant/gpio.h A src/mainboard/google/brya/variants/gaelin/variant.c 5 files changed, 248 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/69011/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/69011 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I42a33b6a8614ec9c7c978cd7af7d92bfed391ad8 Gerrit-Change-Number: 69011 Gerrit-PatchSet: 2 Gerrit-Owner: Tony Tung <tonytung(a)msi.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tony Tung <tonytung(a)msi.corp-partner.google.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: Turn off camera and mic during S0ix
by build bot (Jenkins) (Code Review) 31 Oct '22

31 Oct '22

Attention is currently required from: Tarun Tuli. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69011 ) Change subject: Turn off camera and mic during S0ix ...................................................................... Patch Set 1: (3 comments) File src/mainboard/google/brya/variants/gaelin/variant.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161729): https://review.coreboot.org/c/coreboot/+/69011/comment/645fa385_b1118ba8 PS1, Line 10: if (entry == S0IX_ENTRY) that open brace { should be on the previous line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161729): https://review.coreboot.org/c/coreboot/+/69011/comment/c3f48265_2f6d65fc PS1, Line 15: else if (entry == S0IX_EXIT) that open brace { should be on the previous line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-161729): https://review.coreboot.org/c/coreboot/+/69011/comment/7e41a95e_2c64d997 PS1, Line 15: else if (entry == S0IX_EXIT) else should follow close brace '}' -- To view, visit https://review.coreboot.org/c/coreboot/+/69011 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I42a33b6a8614ec9c7c978cd7af7d92bfed391ad8 Gerrit-Change-Number: 69011 Gerrit-PatchSet: 1 Gerrit-Owner: Tony Tung <tonytung(a)msi.corp-partner.google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Comment-Date: Mon, 31 Oct 2022 00:50:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: Turn off camera and mic during S0ix
by Tony Tung (Code Review) 31 Oct '22

31 Oct '22

Tony Tung has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69011 ) Change subject: Turn off camera and mic during S0ix ...................................................................... Turn off camera and mic during S0ix Change-Id: I42a33b6a8614ec9c7c978cd7af7d92bfed391ad8 --- A .vscode/settings.json M src/mainboard/google/brya/variants/gaelin/Makefile.inc A src/mainboard/google/brya/variants/gaelin/gpio.c M src/mainboard/google/brya/variants/gaelin/include/variant/gpio.h A src/mainboard/google/brya/variants/gaelin/variant.c 5 files changed, 248 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/69011/1 diff --git a/.vscode/settings.json b/.vscode/settings.json new file mode 100644 index 0000000..c50ba97 --- /dev/null +++ b/.vscode/settings.json @@ -0,0 +1,5 @@ +{ + "files.associations": { + "variants.h": "c" + } +} \ No newline at end of file diff --git a/src/mainboard/google/brya/variants/gaelin/Makefile.inc b/src/mainboard/google/brya/variants/gaelin/Makefile.inc index fd45b94..5c0b6da 100644 --- a/src/mainboard/google/brya/variants/gaelin/Makefile.inc +++ b/src/mainboard/google/brya/variants/gaelin/Makefile.inc @@ -1 +1,5 @@ romstage-y += memory.c +romstage-y += gpio.c + +ramstage-y += gpio.c +ramstage-y += variant.c diff --git a/src/mainboard/google/brya/variants/gaelin/gpio.c b/src/mainboard/google/brya/variants/gaelin/gpio.c new file mode 100644 index 0000000..bdf5125 --- /dev/null +++ b/src/mainboard/google/brya/variants/gaelin/gpio.c @@ -0,0 +1,207 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> +#include <soc/gpio.h> + +/* Pad configuration in ramstage */ +static const struct pad_config override_gpio_table[] = { + /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), + /* A17 : DISP_MISCC ==> EN_FCAM_PWR */ + PAD_CFG_GPO(GPP_A17, 1, DEEP), + /* A19 : DDSP_HPD1 ==> NC */ + PAD_NC(GPP_A19, NONE), + /* A20 : DDSP_HPD2 ==> NC */ + PAD_NC(GPP_A20, NONE), + /* A21 : DDPC_CTRCLK ==> NC */ + PAD_NC(GPP_A21, NONE), + /* A22 : DDPC_CTRLDATA ==> NC */ + PAD_NC(GPP_A22, NONE), + + /* B2 : VRALERT# ==> NC */ + PAD_NC(GPP_B2, NONE), + /* B3 : PROC_GP2 ==> NC */ + PAD_NC(GPP_B3, NONE), + /* B4 : PROC_GP3 ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_B4, 1, DEEP), + /* B7 : ISH_12C1_SDA ==> PCH_I2C_TCHSCR_SDA */ + PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2), /* //for Proto2 //raymondchung: ??? */ + /* B8 : ISH_I2C1_SCL ==> PCH_I2C_TCHSCR_SCL */ + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2), /* //for Proto2 //raymondchung: ??? */ + + /* C6 : SML1CLK ==> USI_RST_L */ + PAD_CFG_GPO(GPP_C6, 0, DEEP), /* //for Proto2 //raymondchung: ??? */ + /* C7 : SML1DATA ==> USI_INT_L */ + PAD_CFG_GPI_IRQ_WAKE(GPP_C7, NONE, DEEP, LEVEL, INVERT), /* //for Proto2 //raymondchung: ??? */ + + /* D0 : ISH_GP0 ==> NC */ + PAD_NC(GPP_D0, NONE), + /* D1 : ISH_GP1 ==> NC */ + PAD_NC(GPP_D1, NONE), + /* D2 : ISH_GP2 ==> NC */ + PAD_NC(GPP_D2, NONE), + /* D3 : ISH_GP3 ==> NC */ + PAD_NC(GPP_D3, NONE), + /* D8 : SRCCLKREQ3# ==> NC */ + PAD_NC(GPP_D8, NONE), + /* D9 : ISH_SPI_CS# ==> NC */ + PAD_NC(GPP_D9, NONE), + /* D11 : ISH_SPI_MISO ==> NC */ + PAD_NC(GPP_D11, NONE), + /* D12 : ISH_SPI_MOSI ==> GPP_D12_STRAP */ + PAD_NC(GPP_D12, NONE), + /* D17 : UART1_RXD ==> NC */ + PAD_NC(GPP_D17, NONE), + /* D18 : UART1_TXD ==> NC */ + PAD_NC(GPP_D18, NONE), + + /* E4 : SATA_DEVSLP0 ==> USB_A0_RT_RST_ODL */ + PAD_CFG_GPO(GPP_E4, 1, DEEP), + /* E5 : SATA_DEVSLP1 ==> USB_A1_RT_RST_ODL */ + PAD_CFG_GPO(GPP_E5, 1, DEEP), + /* E7 : PROC_GP1 ==> EN_MIC_PWR */ + PAD_CFG_GPO(GPP_E7, 1, DEEP), + /* E14 : DDSP_HPDA ==> EDP_HPD */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + /* E15 : RSVD_TP ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), + /* E18 : DDP1_CTRLCLK ==> NC */ + PAD_NC(GPP_E18, NONE), + /* E20 : DDP2_CTRLCLK ==> NC */ + PAD_NC(GPP_E20, NONE), + + /* F11 : THC1_SPI2_CLK ==> NC */ + PAD_NC(GPP_F11, NONE), + /* F12 : GSXDOUT ==> NC */ + PAD_NC(GPP_F12, NONE), + /* F13 : GSXDOUT ==> NC */ + PAD_NC(GPP_F13, NONE), + /* F14 : GSXDIN ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_F14, 1, DEEP), + /* F15 : GSXSRESET# ==> NC */ + PAD_NC(GPP_F15, NONE), + /* F16 : GSXCLK ==> NC */ + PAD_NC(GPP_F16, NONE), + /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F18, NONE, DEEP), + + /* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* H7 : I2C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), + /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), + /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), + /* H12 : I2C7_SDA ==> NC */ + PAD_NC(GPP_H12, NONE), + /* H13 : I2C7_SCL ==> NC */ + PAD_NC(GPP_H13, NONE), + + /* R6 : I2S2_TXD ==> NC */ + PAD_NC(GPP_R6, NONE), + /* R7 : I2S2_RXD ==> NC */ + PAD_NC(GPP_R7, NONE), + + /* S0 : SNDW0_CLK ==> I2S1_SPKR_SCLK_R */ + PAD_CFG_NF(GPP_S0, NONE, DEEP, NF4), + /* S1 : SNDW0_DATA ==> I2S1_SPKR_SFRM_R */ + PAD_CFG_NF(GPP_S1, NONE, DEEP, NF4), + /* S2 : SNDW1_CLK ==> I2S1_PCH_TX_SPKR_RX_R */ + PAD_CFG_NF(GPP_S2, NONE, DEEP, NF4), + /* S6 : SNDW3_CLK ==> DMIC_CLK1_R */ + PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), + /* S7 : SNDW3_DATA ==> DMIC_DATA1_R */ + PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), + + /* CPU PCIe VGPIO for PEG60 */ + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, PLTRST, NF1), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), + /* B4 : PROC_GP3 ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_B4, 0, DEEP), + /* E15 : RSVD_TP ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), + /* F14 : GSXDIN ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_F14, 1, DEEP), + /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F18, NONE, DEEP), + /* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* H7 : I2C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), + /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), + /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), + + /* CPU PCIe VGPIO for PEG60 */ + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, PLTRST, NF1), +}; + +static const struct pad_config romstage_gpio_table[] = { + /* B4 : PROC_GP3 ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_B4, 1, DEEP), +}; + +const struct pad_config *variant_gpio_override_table(size_t *num) +{ + *num = ARRAY_SIZE(override_gpio_table); + return override_gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +const struct pad_config *variant_romstage_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; +} diff --git a/src/mainboard/google/brya/variants/gaelin/include/variant/gpio.h b/src/mainboard/google/brya/variants/gaelin/include/variant/gpio.h index c4fe342..b3ae200 100644 --- a/src/mainboard/google/brya/variants/gaelin/include/variant/gpio.h +++ b/src/mainboard/google/brya/variants/gaelin/include/variant/gpio.h @@ -5,4 +5,7 @@ #include <baseboard/gpio.h> +#define FCAM_POWER GPP_A17 +#define MIC_POWER GPP_E7 + #endif diff --git a/src/mainboard/google/brya/variants/gaelin/variant.c b/src/mainboard/google/brya/variants/gaelin/variant.c new file mode 100644 index 0000000..808d7a1 --- /dev/null +++ b/src/mainboard/google/brya/variants/gaelin/variant.c @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <chip.h> +#include <baseboard/variants.h> +#include <variant/gpio.h> +#include <acpi/acpigen.h> + +void variant_generate_s0ix_hook(enum s0ix_entry entry) +{ + if (entry == S0IX_ENTRY) + { + acpigen_soc_clear_tx_gpio(FCAM_POWER); + acpigen_soc_clear_tx_gpio(MIC_POWER); + } + else if (entry == S0IX_EXIT) + { + acpigen_soc_set_tx_gpio(FCAM_POWER); + acpigen_soc_set_tx_gpio(MIC_POWER); + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/69011 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I42a33b6a8614ec9c7c978cd7af7d92bfed391ad8 Gerrit-Change-Number: 69011 Gerrit-PatchSet: 1 Gerrit-Owner: Tony Tung <tonytung(a)msi.corp-partner.google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/google/rex: Add fingerprint SPI
by Eric Lai (Code Review) 31 Oct '22

31 Oct '22

Attention is currently required from: Tarun Tuli, Eran Mitrani, Subrata Banik, Kapil Porwal. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/66992 ) Change subject: mb/google/rex: Add fingerprint SPI ...................................................................... Patch Set 14: (1 comment) File src/mainboard/google/rex/variants/rex0/gpio.c: https://review.coreboot.org/c/coreboot/+/66992/comment/cf9f686b_b4990254 PS14, Line 387: PAD_CFG_GPO(GPP_B11, 1, DEEP), Why just power off PWR here then you can remove the romstage? -- To view, visit https://review.coreboot.org/c/coreboot/+/66992 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4e6be24e72a8232ae2c958a01cf8ea9a272d7365 Gerrit-Change-Number: 66992 Gerrit-PatchSet: 14 Gerrit-Owner: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Mon, 31 Oct 2022 00:34:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: drivers/pc80/tpm: probe for TPM family of a device
by Sergii Dmytruk (Code Review) 30 Oct '22

30 Oct '22

Attention is currently required from: Michał Żygowski, Christian Walter, Julius Werner, Krystian Hebel. Hello Michał Żygowski, Julius Werner, Krystian Hebel, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/69023 to review the following change. Change subject: drivers/pc80/tpm: probe for TPM family of a device ...................................................................... drivers/pc80/tpm: probe for TPM family of a device This is to handle the situation when device ID is the same for TPM1 and TPM2 versions of a device. Important change of behaviour: the code now rejects unknown TPMs. Change-Id: I5464771836c66bcc441efb7189ded416b8f53827 Ticket: https://ticket.coreboot.org/issues/433 Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> --- M src/drivers/pc80/tpm/tis.c 1 file changed, 52 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/69023/1 diff --git a/src/drivers/pc80/tpm/tis.c b/src/drivers/pc80/tpm/tis.c index 9f5f9af..5d08346 100644 --- a/src/drivers/pc80/tpm/tis.c +++ b/src/drivers/pc80/tpm/tis.c @@ -54,6 +54,7 @@ #define TIS_REG_STS 0x18 #define TIS_REG_BURST_COUNT 0x19 #define TIS_REG_DATA_FIFO 0x24 +#define TIS_REG_INTF_ID 0x30 #define TIS_REG_DID_VID 0xf00 #define TIS_REG_RID 0xf04 @@ -89,11 +90,11 @@ /* * Structures defined below allow creating descriptions of TPM vendor/device - * ID information for run time discovery. The only device the system knows - * about at this time is Infineon slb9635 + * ID information for run time discovery. */ struct device_name { u16 dev_id; + int tpm_family; const char *const dev_name; }; @@ -104,36 +105,31 @@ }; static const struct device_name atmel_devices[] = { - {0x3204, "AT97SC3204"}, + {0x3204, 1, "AT97SC3204"}, {0xffff} }; static const struct device_name infineon_devices[] = { - {0x000b, "SLB9635 TT 1.2"}, -#if CONFIG(TPM2) - {0x001a, "SLB9665 TT 2.0"}, - {0x001b, "SLB9670 TT 2.0"}, -#else - {0x001a, "SLB9660 TT 1.2"}, - {0x001b, "SLB9670 TT 1.2"}, -#endif + {0x000b, 1, "SLB9635 TT 1.2"}, + {0x001a, 1, "SLB9660 TT 1.2"}, + {0x001b, 1, "SLB9670 TT 1.2"}, + {0x001a, 2, "SLB9665 TT 2.0"}, + {0x001b, 2, "SLB9670 TT 2.0"}, {0xffff} }; static const struct device_name nuvoton_devices[] = { - {0x00fe, "NPCT420AA V2"}, + {0x00fe, 1, "NPCT420AA V2"}, {0xffff} }; static const struct device_name stmicro_devices[] = { - {0x0000, "ST33ZP24" }, + {0x0000, 1, "ST33ZP24" }, {0xffff} }; static const struct device_name swtpm_devices[] = { -#if CONFIG(TPM2) - {0x0001, "SwTPM 2.0" }, -#endif + {0x0001, 2, "SwTPM 2.0" }, {0xffff} }; @@ -199,6 +195,13 @@ write8(TIS_REG(locality, TIS_REG_ACCESS), data); } +static inline u32 tpm_read_intf_id(int locality) +{ + u32 value = read32(TIS_REG(locality, TIS_REG_INTF_ID)); + TPM_DEBUG_IO_READ(TIS_REG_INTF_ID, value); + return value; +} + static inline u32 tpm_read_did_vid(int locality) { u32 value = read32(TIS_REG(locality, TIS_REG_DID_VID)); @@ -387,9 +390,9 @@ const char *device_name = "unknown"; const char *vendor_name = device_name; const struct device_name *dev; - u32 didvid; + u32 didvid, intf_id; u16 vid, did; - int i; + int i, tpm_family; if (vendor_dev_id) return 0; /* Already probed. */ @@ -400,21 +403,23 @@ return TPM_DRIVER_ERR; } + intf_id = be32_to_cpu(tpm_read_intf_id(0)); + tpm_family = ((intf_id & 0xf) == 0xf ? 1 : 2); + vendor_dev_id = didvid; vid = didvid & 0xffff; did = (didvid >> 16) & 0xffff; for (i = 0; i < ARRAY_SIZE(vendor_names); i++) { int j = 0; - u16 known_did; if (vid == vendor_names[i].vendor_id) { vendor_name = vendor_names[i].vendor_name; } else { continue; } dev = &vendor_names[i].dev_names[j]; - while ((known_did = dev->dev_id) != 0xffff) { - if (known_did == did) { + while (dev->dev_id != 0xffff) { + if (dev->dev_id == did && dev->tpm_family == tpm_family) { device_name = dev->dev_name; break; } @@ -423,7 +428,16 @@ } break; } - /* this will have to be converted into debug printout */ + + if (strcmp(vendor_name, "unknown") == 0) { + printk(BIOS_INFO, "Found unsupported TPM 0x%04x by 0x%04x\n", did, vid); + return TPM_DRIVER_ERR; + } + if (strcmp(device_name, "unknown") == 0) { + printk(BIOS_INFO, "Found unsupported TPM device by %s\n", vendor_name); + return TPM_DRIVER_ERR; + } + printk(BIOS_INFO, "Found TPM %s by %s\n", device_name, vendor_name); return 0; } -- To view, visit https://review.coreboot.org/c/coreboot/+/69023 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5464771836c66bcc441efb7189ded416b8f53827 Gerrit-Change-Number: 69023 Gerrit-PatchSet: 1 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: drivers/spi/tpm: verify device supports TPM2
by Sergii Dmytruk (Code Review) 30 Oct '22

30 Oct '22

Attention is currently required from: Michał Żygowski, Julius Werner, Krystian Hebel. Hello Michał Żygowski, Julius Werner, Krystian Hebel, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/69022 to review the following change. Change subject: drivers/spi/tpm: verify device supports TPM2 ...................................................................... drivers/spi/tpm: verify device supports TPM2 This is to handle the situation when device ID is the same for TPM1 and TPM2 versions of a device. Change-Id: Ib2840a21b3be8928d39570281f86a0e26b38b5f9 Ticket: https://ticket.coreboot.org/issues/433 Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> --- M src/drivers/spi/tpm/tpm.c 1 file changed, 25 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/69022/1 diff --git a/src/drivers/spi/tpm/tpm.c b/src/drivers/spi/tpm/tpm.c index 68f9588..8b390f0 100644 --- a/src/drivers/spi/tpm/tpm.c +++ b/src/drivers/spi/tpm/tpm.c @@ -28,6 +28,7 @@ #define TPM_ACCESS_REG (TPM_LOCALITY_0_SPI_BASE + 0) #define TPM_STS_REG (TPM_LOCALITY_0_SPI_BASE + 0x18) #define TPM_DATA_FIFO_REG (TPM_LOCALITY_0_SPI_BASE + 0x24) +#define TPM_INTF_ID_REG (TPM_LOCALITY_0_SPI_BASE + 0x30) #define TPM_DID_VID_REG (TPM_LOCALITY_0_SPI_BASE + 0xf00) #define TPM_RID_REG (TPM_LOCALITY_0_SPI_BASE + 0xf04) #define TPM_FW_VER (TPM_LOCALITY_0_SPI_BASE + 0xf90) @@ -412,7 +413,7 @@ int tpm2_init(struct spi_slave *spi_if) { - uint32_t did_vid, status; + uint32_t did_vid, status, intf_id; uint8_t cmd; int retries; @@ -454,6 +455,15 @@ printk(BIOS_INFO, " done!\n"); + if (tpm2_read_reg(TPM_INTF_ID_REG, &intf_id, sizeof(intf_id)) != CB_SUCCESS) { + printk(BIOS_ERR, "\n%s: Failed to read interface ID register\n", __func__); + return -1; + } + if ((be32toh(intf_id) & 0xF) == 0xF) { + printk(BIOS_DEBUG, "\n%s: Not a TPM2 device\n", __func__); + return -1; + } + // FIXME: Move this to tpm_setup() if (tpm_first_access_this_boot()) /* -- To view, visit https://review.coreboot.org/c/coreboot/+/69022 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib2840a21b3be8928d39570281f86a0e26b38b5f9 Gerrit-Change-Number: 69022 Gerrit-PatchSet: 1 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-MessageType: newchange

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