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Change subject: drivers/ipmi/ipmi_kcs_ops.c: accommodate BMC revision being 0
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Patch Set 5: Code-Review+2
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Change subject: security/vboot: Update build rules using x86 SHA extension
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Patch Set 1: Code-Review+1
(1 comment)
File src/security/vboot/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/68953/comment/0f2e31a6_56e72f28
PS1, Line 27: 0
Make it empty to be consistent with `$(CONFIG_VBOOT_X86_SHA256_ACCELERATION)`?
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Change subject: Add console deinit API, use in SMM handler
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Patch Set 11:
(1 comment)
Patchset:
PS11:
This change is replaced and merged by CB:68567
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Change subject: mb/google/skyrim: Use detect vs probed flag for touchscreens
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Patch Set 5: Code-Review+2
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Patch Set 2: Code-Review+1
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Change subject: soc/amd/acpi: Expand 5 DPTC thermal profiles acpigen support for Alib
......................................................................
Patch Set 14:
(1 comment)
File src/soc/amd/common/block/include/amdblocks/alib.h:
https://review.coreboot.org/c/coreboot/+/68470/comment/acb6a15e_10f89d6f
PS14, Line 28: ALIB_DPTC_STT_MIN_LIMIT_ID = 0x2E,
> The value provided by AMD Chris in b/232946420#comment121. […]
Hi Tim,
It documented in NbioDptciMdn.esl of the MDN AGESA-PI. the ID has been used in several non-Chrome project, but it haven't been update in AGESA V9 spec. We have a internal-JIRA to tracking that. but not sure when it will be update and release.
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Change subject: soc/amd/acpi: Expand 5 DPTC thermal profiles acpigen support for Alib
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Patch Set 14:
(1 comment)
File src/soc/amd/common/block/include/amdblocks/alib.h:
https://review.coreboot.org/c/coreboot/+/68470/comment/b7a1f9b9_5ad7668d
PS14, Line 28: ALIB_DPTC_STT_MIN_LIMIT_ID = 0x2E,
> Where is `0x2E` documented? Document 55483 only has: […]
The value provided by AMD Chris in b/232946420#comment121.
Hi Chris,
Could you help to share where to find `STT_MIN_LIMIT_ID` in 55483? I didn't find it in section 5.11.9 from document 55483_1.70.
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